WO2020107754A1 - Epitaxial layer structure for increasing threshold voltage of gan-enhanced mosfet and device fabrication method - Google Patents

Abstract

An epitaxial layer structure for increasing a threshold voltage of a GaN-enhanced MOSFET and a device fabrication method employing the structure, relating to the field of power electronic devices and power switches. A substrate, a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, a GaN channel layer, and an AlGaN barrier layer are sequentially provided, from bottom to top, in the epitaxial layer structure. A passivation layer, a recessed gate, planar isolation, an insulated gate medium layer, an ohmic contact, a gate ohmic metal electrode, and a source-drain ohmic metal electrode are formed on the structure by means of a recessed gate process, so as to fabricate a GaN-enhanced MOSFET having a high threshold voltage. In the present invention, the P-type GaN layer is inserted into the intrinsic GaN layer, and after etching has been completely performed thereon, a channel inversion region has the P-type GaN layer in addition to the intrinsic GaN layer, thereby greatly increasing a threshold voltage of a device. The invention facilitates an improvement in the reliability of a GaN-enhanced device in practical applications, and widens an application range of the device in the field of power switches.

Description

Epitaxial layer structure and device preparation for improving threshold voltage of GaN enhanced MOSFET Technical field

The invention belongs to the technical field of microelectronics, and relates to the field of power electronic devices and power switches based on compound semiconductor materials.

Background technique

Because of its outstanding material properties, such as high breakdown field strength, high electron saturation mobility, etc., wide band gap semiconductor GaN is considered to be a very promising competitor in the field of next-generation high-efficiency power switches. In addition, due to the strong spontaneous polarization effect, two-dimensional electron gas (2DEG) with a concentration of up to 10 ¹³ cm ^-2 naturally exists at the conventional AlGaN/GaN heterojunction interface, and the mobility of 2DEG can be as high as 2000 cm ² / V·S, this advantage allows GaN power electronic devices based on AlGaN/GaN heterojunction to have faster switching speed, but it also means that the conventional heterojunction high mobility transistor (HEMT) is a depletion type device, That is, at zero gate voltage, the device is normally open and the device threshold voltage is negative. However, in practical applications, for the safe operation of power electronic systems, in order to ensure that the device only has a working current when a positive gate voltage bias is applied, an enhanced device is indispensable. Therefore, many researchers at home and abroad have been committed to achieving high-performance enhanced GaN HEMT.

At present, there are two main ways to realize the enhanced operation of GaN-based devices. One is to integrate a low-voltage enhanced silicon-based MOSFET and a high-voltage depletion-mode GaN device into a cascode structure to achieve an enhanced operation. System; the second is to directly use enhanced high-voltage GaN power devices. The advantage of the cascode structure is that the gate is controlled on the silicon-based MOSFET, and the gate of the GaN-based device is not directly controlled, so that the system has no operating current at zero bias and is forward-biased above the threshold voltage When pressing, it can use the normally open GaN-based device to quickly open. However, after all, the gate control does not directly affect the GaN-based device, and the conversion efficiency control of the power switch is not very good, and this will greatly affect the safe operation of the system and the pulsating noise. Therefore, the direct gate-controlled high-voltage enhanced GaN power device It is still very necessary.

There are two main methods to realize the enhanced GaN power device: 1. Grow a layer of P-type GaN on the surface of AlGaN/GaN heterojunction, rationally design the thickness and doping of the layer to effectively deplete the different 2DEG at the junction interface to realize normally-off GaN power devices, although the P-Type GaN gate structure can obtain enhanced devices with good threshold voltage consistency, but due to the difficulty of P-type GaN growth and poor material quality, the gate is reliable Sex is not good. 2. Reduce the thickness of the AlGaN layer in the gate area, eliminate the inherent positive charge under the gate, thus depleting the 2DEG at the heterojunction interface, and realize the normally-off GaN power device. The metal-insulated gate structure (MIS) made by this method Although the device can obtain a good gate reliability device and the process is simple, the threshold voltage of the device is difficult to be very positive, in other words, it is difficult to ensure the absolute off state under zero bias.

Summary of the invention

In order to solve the shortcomings of the above method 2 to realize the enhanced GaN power device technology, the present invention focuses on the design of the AlGaN/GaN heterojunction epitaxial layer structure, and proposes a new epitaxial layer structure that uses a simple and easy to implement traditional dry etching process By removing the AlGaN barrier layer, an enhanced GaN power device with a very positive threshold voltage can be prepared.

The novel epitaxial layer structure proposed by the present invention includes: a substrate, a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer, as shown in the figure 1 shown. The new epitaxial layer structure inserts a layer of Mg-doped P-type GaN into the intrinsic GaN layer under 2DEG. Using the traditional gate trench etching process, the gate is etched below the Mg-doped P-type GaN layer to form a gate The lower channel, compared with the channel formed by removing the AlGaN barrier layer in the traditional epitaxial layer structure, the structure has more P-type GaN channels on both sides, that is, the device is fully turned on. For the inversion of the GaN layer, the inversion of the P-type GaN channel is also required, so that the threshold voltage of the device will be larger than that of the enhanced device prepared by the traditional epitaxial layer structure. At the same time, the p-type GaN inversion channel is located on the side, and its effective width is very narrow, which is determined by the thickness of the p-type GaN, which avoids facing a long lateral P-type GaN trench when only etching the upper layer of intrinsic GaN Road. Since the carrier mobility of the inversion channel on p-type GaN is less than that of the accumulation channel on intrinsic GaN, this etching scheme can effectively avoid the lateral p-type GaN inversion channel The problem of large on-resistance improves the output current capability of the device.

The formation of passivation layer, groove gate, plane isolation, insulating gate dielectric layer, ohmic contact, and gate and source-drain ohmic metal electrodes on the above new epitaxial layer structure using traditional groove gate process can form the enhancement of high threshold voltage Type GaN MOSFET. After inserting a P-type GaN layer into the intrinsic GaN layer and completely etching it, the channel inversion region has a P-type GaN layer in addition to the intrinsic GaN layer, which can greatly increase the threshold voltage of the device and help solve The reliability of GaN-enhanced devices in practical applications has broadened their application in the field of power switching.

Based on the above technical ideas, the present invention uses the Sentaurus TCAD simulation tool to simulate and verify a simple MOS gate trench type device based on the new epitaxial layer structure (as shown in FIG. 2). The resulting transfer characteristics of the device are shown in FIG. 3. It is seen that the threshold voltage is about 5V (extracted by linear extrapolation), which is greatly improved compared with the gate-groove device under the traditional structure, and preliminary simulation verification confirms the feasibility of the present invention. In order to realize the growth of the new epitaxial layer and ensure the performance of the device, the inserted Mg-doped P-type GaN layer needs to be designed with a reasonable thickness and doping concentration. In addition, in order to avoid the influence of P-type GaN on the GaN channel layer, The distance from the GaN channel layer should also be designed reasonably. Comprehensively considering the above effects, the composition and material types of the key layers of the new epitaxial layer structure are as follows:

The substrate material is preferably one of the following materials: Si, SiC, sapphire.

The doping concentration of the Mg-doped P-type GaN layer is preferably: 5E16～2E18cm ^-3 .

The thickness of the Mg-doped P-type GaN layer is preferably 50 nm to 300 nm.

The thickness of the intrinsic GaN channel layer on the Mg-doped P-type GaN layer is preferably: 100 nm to 300 nm.

The present invention provides a simple and easy-to-implement process based on the new GaN epitaxial layer structure to prepare GaN enhanced MOSFET, including the following steps:

(1) A GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer are sequentially grown on the substrate;

(2) Use PECVD, ICPCVD or LPCVD to grow a passivation layer on the AlGaN barrier layer;

(3) The gate pattern is lithographically etched, the dielectric passivation layer is etched first, and then the intrinsic GaN channel layer is etched until the Mg-doped P-type GaN layer is completely etched to form a groove, and then preferably at 650 ℃ ~ 800 ℃ Anneal in N ₂ protective gas for 15 minutes to activate P-type GaN;

(4) Photoetch and etch (or ion implantation) GaN wafers that have been annealed to activate the P-type GaN at the channel to form the active area mesa;

(5) Perform photolithography on the prepared GaN wafer in the active area mesa, etch the source-drain ohmic electrode area, prepare multiple layers of metal by electron beam evaporation or magnetron sputtering to form the source and drain, and in Annealing in protective gas for 30 seconds between 800℃ and 900℃ to form ohmic contact;

(6) After forming the ohmic contact, place the wafer into the atomic layer deposition equipment, grow an insulating gate dielectric layer on its surface, and then lithographically etch ohmic contact holes in the source and drain regions to remove the insulating gate dielectric of the ohmic contact holes Layer, so that the source-drain ohmic contact is exposed;

(7) The area of the gate electrode is etched, the gate electrode material is grown by electron beam evaporation or magnetron sputtering, then the device is subjected to a stripping process to form the gate electrode, and finally the entire wafer is annealed under a nitrogen atmosphere to complete the entire device Of preparation.

The material of the dielectric passivation layer in the above process method may be any one of the following materials: Si ₃ N ₄ , SiO ₂ , AlN, Al ₂ O ₃ , SiON.

In the above process method, step 3) the method of etching to form the groove may be any one of the following methods: ICP etching, wet etching.

The materials of the source electrode and the drain electrode in the above process method are: one or more alloys of titanium, aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, tungsten and the like.

The insulating gate dielectric layer in the above process method may be any one of the following materials: Si ₃ N ₄ , Al ₂ O ₃ , AlN, HfO ₂ , SiO ₂ , HfTiO, Sc ₂ O ₃ , Ga ₂ O ₃ , MgO, SiON.

The gate electrode material in the above process method is one or a combination of the following conductive materials: platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN, polysilicon, ITO.

From the perspective of the material structure design of compound semiconductors, the present invention proposes a new type of AlGaN/GaN heterojunction structure, on which the enhanced device with larger threshold voltage can be realized by the simplest gate trench etching process. This guarantees the absolute off-state of the device under zero bias and is expected to solve the related reliability problems of GaN devices in practical applications.

BRIEF DESCRIPTION

The accompanying drawings will explain in more detail the new epitaxial layer structure proposed by the present invention and a preparation example of a GaN enhanced device based on the epitaxial layer structure. The drawings are as follows:

FIG. 1 is a schematic cross-sectional structure diagram of a novel epitaxial layer structure proposed by the present invention.

2 is a schematic diagram of a cross-sectional structure of a simple MOS gate trench type GaN enhanced device based on the novel epitaxial layer structure of the present invention (sentaurus TCAD device simulation structure).

Fig. 3 is a comparison diagram of the device transfer characteristic curve obtained by computer simulation of the device structure shown in Fig. 2 with the use of Sentaurus TCAD simulation software and an ordinary device without a pGaN insertion layer. It can be seen that the threshold voltage of the device is greatly increased.

4 to 9 are schematic diagrams of device cross-sectional structures corresponding to each step of the process of preparing a trench-type GaN enhanced device based on the epitaxial layer structure proposed by the present invention, and reflect a specific implementation example of the present invention.

detailed description

In the following, the preparation of a gate trench type GaN enhanced device based on the novel epitaxial layer structure proposed by the present invention will be described in detail with reference to the accompanying drawings, so that the specific implementation method, process flow, and core technical points of the present invention are more easily understood. This example is only one implementation method of the present invention, that is, the structure proposed by the present invention should not be limited to the example set forth herein. Based on this example, the scope of the present invention is sufficiently conveyed to those skilled in the art.

FIG. 1 shows the novel epitaxial layer structure proposed by the present invention. The heterojunction structure smoothly includes the substrate, the GaN buffer layer, the intrinsic GaN layer, the Mg-doped P-type GaN layer, and the intrinsic GaN channel Layer and intrinsic AlGaN barrier layer. A specific implementation example of preparing a GaN enhanced device using a gate trench etching process based on the structure includes the following specific steps:

(1) Use PECVD, ICPCVD, or LPCVD to grow a Si ₃ N ₄ passivation layer on the AlGaN/GaN heterojunction structure wafer shown in Figure 1 to improve the reliability of the final device. As shown in Figure 4;

(2) On the basis of the structure shown in Fig. 4, first remove the Si ₃ N _{4 in the} gate trench area using an RIE etching machine, then remove the GaN in the gate trench area using an ICP etching machine, and etch to Mg doping under the gate Below the P-type GaN layer, form a channel under the gate, and finally anneal in N ₂ protective gas at 650°C to 800°C for 15 minutes to activate P-type GaN. The resulting structure cross-section is shown in Figure 5;

(3) Next, the active region is formed, and the GaN wafer that has been annealed to activate the P-type GaN at the channel is photolithographic and etched (or ion implanted) to form the active region mesa;

(4) Then photolithography the source-drain ohmic pattern in the active area, first remove the Si ₃ N ₄ covering it by RIE etching machine, and then evaporate Ti/Al/Ni/Au four metals by electron beam, A source-drain ohmic metal electrode was prepared by a stripping process, and finally annealed in a nitrogen atmosphere at 870°C for 30 seconds to form an ohmic contact. The schematic cross-sectional structure is shown in Figure 6;

(5) On the basis of step (4), an Al ₂ O ₃ insulating gate dielectric layer is grown on the wafer surface to form the structure shown in FIG. 7;

(6) On the basis of the structure shown in FIG. 7, the Al ₂ O ₃ covering the source-drain ohmic contact is removed by wet etching (as shown in FIG. 8), and then Ni is grown by electron beam evaporation in the gate region /Au alloy, and then continue to use the stripping process to form the gate metal electrode to form a T-gate structure, as shown in Figure 9. Finally, the entire wafer was annealed under N ₂ atmosphere and annealed at 400°C for 10 min.

Compared with the conventional enhanced device, the enhanced GaN prepared by the above process steps has a larger threshold voltage, which can ensure the absolute off state under zero bias.

Claims (14)

1. An epitaxial layer structure to increase the threshold voltage of GaN enhanced MOSFET, from bottom to top is substrate, GaN buffer layer, intrinsic GaN layer, Mg-doped P-type GaN layer, intrinsic GaN channel layer and intrinsic AlGaN Barrier layer.
2. The epitaxial layer structure for increasing the threshold voltage of a GaN enhanced MOSFET according to claim 1, wherein the material of the substrate is Si, SiC or sapphire.
3. The epitaxial layer structure for increasing the threshold voltage of a GaN-enhanced MOSFET according to claim 1, wherein the doping concentration of the Mg-doped P-type GaN layer is 5E16-2E18cm ^-3 .
4. The epitaxial layer structure for increasing the threshold voltage of a GaN-enhanced MOSFET according to claim 1, wherein the thickness of the Mg-doped P-type GaN layer is 50 nm to 300 nm.
5. The epitaxial layer structure for increasing the threshold voltage of a GaN-enhanced MOSFET according to claim 1, wherein the thickness of the intrinsic GaN channel layer is 100 nm to 300 nm.
6. A GaN-enhanced MOSFET is a gate-slot device, characterized in that the device has an epitaxial layer structure for increasing the threshold voltage of a GaN-enhanced MOSFET according to any one of claims 1 to 5, and the gate slot is etched to the Mg Below the doped P-type GaN layer.
7. A method for preparing a GaN-enhanced MOSFET. First, a GaN buffer layer, an intrinsic GaN layer, an Mg-doped P-type GaN layer, an intrinsic GaN channel layer, and an intrinsic AlGaN barrier layer are sequentially grown on a substrate to obtain rights The epitaxial layer structure for increasing the threshold voltage of the GaN enhanced MOSFET as described in any one of 1 to 5 is required, and then the GaN enhanced MOSFET is formed on the groove gate process.
8. The preparation method according to claim 7, wherein the preparation method comprises the following steps:

   1) GaN buffer layer, intrinsic GaN layer, Mg-doped P-type GaN layer, intrinsic GaN channel layer and intrinsic AlGaN barrier layer are sequentially grown on the substrate;

   2) Growing a dielectric passivation layer on the intrinsic AlGaN barrier layer;

   3) The gate pattern is lithographically etched, the dielectric passivation layer is etched first, and then the intrinsic GaN channel layer is etched until the Mg-doped P-type GaN layer is completely etched to form a groove, and then the P-type GaN is activated by annealing;

   4) Lithography and etching or ion implantation to form mesa in active area;

   5) Source and drain ohmic electrode regions are etched and etched in the active area, and metal source and drain electrodes are prepared by electron beam evaporation or magnetron sputtering, and annealed to form ohmic contacts;

   6) Use an atomic layer deposition equipment to grow an insulating gate dielectric layer on the surface, and then lithographically etch ohmic contact holes in the source and drain regions, and remove the insulating gate dielectric layer in the ohmic contact holes to expose the source-drain ohmic contacts;

   7) The gate electrode material is etched in the area of the gate electrode by electron beam evaporation or magnetron sputtering, and then the device is stripped to form the gate electrode, and finally annealed to complete the preparation of the overall device.
9. The preparation method according to claim 8, wherein the material of the dielectric passivation layer is any one of the following materials: Si ₃ N ₄ , AlN, Al ₂ O ₃ , SiO ₂ , SiON.
10. The preparation method according to claim 8, wherein: step 3) forming a groove by ICP etching or wet etching.
11. The preparation method according to claim 8, characterized in that: in step 3), the P-type GaN is activated by annealing in a N ₂ protective gas at 650°C to 800°C for 15 minutes.
12. The preparation method according to claim 8, wherein in step 6) the insulating gate dielectric layer is any one of the following materials: Si ₃ N ₄ , Al ₂ O ₃ , AlN, HfO ₂ , SiO ₂ , HfTiO, Sc ₂ O ₃ , Ga ₂ O ₃ , MgO, SiNO.
13. The preparation method according to claim 8, wherein the material of the source and drain is selected from titanium, aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium and tungsten One or more alloys.
14. The preparation method according to claim 8, wherein the gate electrode material is a combination of one or more of the following conductive materials: platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, TiN , Polysilicon, ITO.

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