CN109524462B - Fin type field effect transistor - Google Patents
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- CN109524462B CN109524462B CN201811629777.9A CN201811629777A CN109524462B CN 109524462 B CN109524462 B CN 109524462B CN 201811629777 A CN201811629777 A CN 201811629777A CN 109524462 B CN109524462 B CN 109524462B
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- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005457 optimization Methods 0.000 claims description 4
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 7
- 238000004364 calculation method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002939 conjugate gradient method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 nitride compound Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a fin field effect transistor, which is characterized by comprising the following components: a substrate, a buffer layer on the substrate, and a barrier layer on the buffer layer; a source, a drain, and a gate on the barrier layer, the gate being between the source and drain; the barrier layer comprises a plurality of fins which are arranged in parallel and at intervals, are positioned in a region between the source electrode and the drain electrode and are perpendicular to the grid electrode; the width (in nm) of the fins is a1, a2, a3, a4,..and an, the number of fins with a1 is b1, the number of fins with a2 is b2, the number of fins with a3 is b3, and so on, the number of fins with an is bn, wherein a1, a2, a3, a4,..and an are any integer between 10 and 200, and b1, b2, b3, b4,..and bn are any positive integer. According to the fin field effect transistor, the linearity of the device is improved by combining fins with various widths.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a fin field effect transistor.
Background
The third generation semiconductor materials represented by gallium nitride (GaN) have excellent characteristics such as wide forbidden band, high electron mobility, high breakdown voltage, etc., so that the high electron mobility field effect transistor (HEMT) based on the gallium nitride materials is widely used in the fields of radar, microwave communication and high voltage power devices. With the rapid development of modern wireless communication, various non-constant envelope modulation modes and multi-carrier technologies are widely applied, and the signals have the characteristics of wide bandwidth, peak-to-average ratio (PAR) and the like, so that the linearity of a field effect transistor in a radio frequency power amplifier circuit aiming at the signals becomes a very important index. If the linearity of the tube is poor, this can lead to spread spectrum beyond the signal bandwidth, interfering with adjacent channels, degrading Adjacent Channel Leakage Ratio (ACLR) performance. Even within the signal bandwidth, the linearity fluctuation of the power amplifier tube causes an increase in distortion, thereby reducing the Error Vector Magnitude (EVM) performance of the receiver and increasing the Bit Error Rate (BER). The gallium nitride-based HEMT device is mainly used for high-power, high-frequency and large-bandwidth application occasions, so that the linearity of the device is crucial to the performance of the whole radio frequency front end. When the dynamic range of an input signal is enlarged, the static working point of the gallium nitride HEMT device is influenced, so that the amplitude and phase transmission characteristics of the device are changed, distortion is generated on an output signal, and the problem of linearity is generated. How to improve the linearity performance of the HEMT device is always a technical difficulty of the gallium nitride radio frequency device. Most applications use methods such as power back-off, negative feedback, feedforward, digital Predistortion (DPD) and the like to match the nonlinearity of the tube from the system perspective, but to solve the problem fundamentally, the linearity performance of the tube needs to be improved from the device perspective.
Disclosure of Invention
Based on this, it is necessary to provide a fin field effect transistor capable of improving linearity against the problem of HEMT linearity.
A fin field effect transistor, comprising:
a substrate, a buffer layer on the substrate, and a barrier layer on the buffer layer;
a source, a drain, and a gate on the barrier layer, the gate being between the source and drain;
the barrier layer between the source electrode and the drain electrode comprises a plurality of fins which are arranged in parallel at intervals, are positioned in the region between the source electrode and the drain electrode and are perpendicular to the grid electrode;
the fins have widths (in nm) of a1, a2, a3, a4, an, the number of fins having a1 is b1, the number of fins having a2 is b2, the number of fins having a3 is b3, and so on, the number of fins having an width is bn, wherein a1, a2, a3, a4, an is any integer between 10 and 200, and b1, b2, b3, b4, bn is any positive integer.
In one embodiment, the gate surrounds the top surface and the opposite sides of the fin.
In one embodiment, grooves are provided between the fins, and the gate spans all grooves and fins.
In one embodiment, a portion of the gate electrode within the recess is in contact with the buffer layer.
In one embodiment, the a1, a2, a3, a4,..the arithmetic progression is satisfied, i.e., an=a1+d (n-1), where d is any integer between 5 and 60.
In one embodiment, the finfet satisfies the formula:
o(V)＝[c1·f 1 (V)+c2·f 2 (V)+…+cn·f n (V)] 2
where c1 is the proportionality coefficient of a1 width fins occupying the total number of fins, i.e., c1=b1/(b1+b2+ … +bn), c2 is the proportionality coefficient of a2 width fins, i.e., c2=b2/(b1+b2+ … +bn), and cn is the proportionality coefficient of an width fins, i.e., cn=bn/(b1+b2+ … +bn). o (V) is a target optimization function for calculating a scaling factor, f 1 (V) first derivative of transconductance of FET with fin width a1, f 2 (V) first derivative of transconductance of FET with fin width a2, f n (V) is the first derivative of the transconductance of the fin-wide an field effect transistor.
In one embodiment, the f 1 (V)＝dg 1 /dV,f 2 (V)＝dg 2 /dV,…,f n (V)＝dg n dV, g 1 (V),g 2 (V),…,g n (V) is the transconductance of the field effect transistors with fin widths a1, a2, …, an, respectively, and V is the gate voltage.
In one embodiment, the g 1 (V),g 2 (V),…,g n The available gate voltage ranges of (V) are: (V) min 1，V max 1),(V min 2，V max 2),…,(V min n，V max n), the corresponding transconductance reaches a maximum value in the available gate voltage range, and the fluctuation range of the transconductance is smaller than the proportion m%.
According to the fin field effect transistor, the linearity of the device is improved by combining fins with various widths.
Drawings
FIG. 1 is a cross-sectional view of a finfet in accordance with an embodiment;
FIG. 2 is a block diagram of a FinFET according to one embodiment;
FIG. 3 is a graph showing transconductance curves for three different FinFETs;
fig. 4 is a graph of transconductance curves of fin field effect transistors for three fin combinations.
Detailed Description
The fin field effect transistor provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the present invention, in a layer "formed on another layer," it may mean that a layer is formed over another layer, but not necessarily in direct physical or electrical contact with another layer (e.g., there may be one or more other layers between two layers). However, in some embodiments, "formed on" may mean that a layer is in direct physical contact with at least a portion of the top surface of another layer.
One embodiment of the fin field effect transistor is shown in fig. 1, and comprises a substrate 1, a buffer layer 2 positioned on the substrate, and a barrier layer 3 positioned on the buffer layer 2, wherein a source electrode 4, a drain electrode 6 and a gate electrode 5 are arranged on the barrier layer 3, and the gate electrode 5 is positioned between the source electrode 4 and the drain electrode 6. Two-dimensional electron gas exists at the interface between the barrier layer 3 and the buffer layer 2, and is generated by the piezoelectric strain effect between the barrier layer 3 and the buffer layer 2. The two-dimensional electron gas has high electron mobility and high electron density, and can be used as a conducting channel to conduct a device. The substrate 1 material may be silicon carbide, sapphire, silicon, etc. The buffer layer 2 may be a high quality gallium nitride material with a thickness of more than 1 micrometer. The barrier layer 3 may be a ternary or quaternary nitride compound semiconductor alloy, such as AlGaN, inGaN, or the like, having a thickness of 10nm to 100nm. The source electrode 4 and the drain electrode 6 are made of any one or a combination of multiple metals of Ti, pt, au, W and Ni. The gate 5 may be a metal stack of nickel/gold or platinum/gold.
Referring to fig. 2, the barrier layer 3 includes a plurality of fins (fin) 7 disposed in parallel, and the fins 7 are located in a region between the source electrode 4 and the drain electrode 6 and perpendicular to the gate electrode 5. The fins 7 have grooves therebetween, and the gate 5 spans all grooves and the fins 7, that is, a part of the gate 7 is located in the grooves, and the other part surrounds the top surface and two opposite side surfaces of the fins 7, so that the gate 5 and the fins 7 form a three-dimensional schottky contact. The portion of the gate 5 located in the recess is in direct contact with the buffer layer 2, and a portion surrounds the top surface and the opposite side surfaces of the fin 7, forming a door frame-shaped structure.
In order to improve the linearity of the device, the inventor of the application has found through long-term experiments that the device can be realized by combining fins with different widths and numbers into the same fin-HEMT. Also, the width and number of fins follow the following relationship:
let the width (unit nm) of the fins be a1, a2, a3, a4, & an, then the number of fins with a1 is b1, the number of fins with a2 is b2, the number of fins with a3 is b3, and so on, the number of fins with an is bn, wherein a1, a2, a3, a4, & an is any integer between 10-200, b1, b2, b3, b4, & bn is any positive integer.
Assuming widths of 80nm,120nm and 160nm, respectively, fig. 3 shows the transconductance of field effect transistors having widths of 80nm,120nm and 160nm, respectively, with the ordinate representing transconductance (S/mm) and the abscissa representing gate voltage (V). In the field of power amplifiers, gallium nitride-based radio-frequency power amplifiers generally work in an AB mode, the static point of the gallium nitride-based radio-frequency power amplifier is generally within 10% -20% of the maximum transconductance value, the grid voltage corresponding to the transconductance value is in an input level range, and the linearity of the device in the range is good. As can be seen from fig. 3, as the fin width is narrowed, the cut-off voltage of the fet is shifted in the forward direction, and the corresponding maximum value of transconductance and input level range are also shifted in the positive voltage direction. When these three different width fins are combined in a certain proportion in the same fet, the resulting transconductance of the new device is shown in fig. 4. It can be seen that the unit transconductance of the combined tube is reduced in maximum value, but the usable transconductance range is much larger than that of a fin field effect tube with a single fixed width, namely the dynamic range of an input signal is enlarged, and the linearity of the device is improved. In this example, the ratio of the number of three width fins is about 30%,20% and 50% by calculation, assuming a total of 10 fins, i.e., 3 fins with a width of 80nm, 2 fins with a width of 120nm, and 5 fins with a width of 160 nm. Specifically, when fins of different widths are used for combination, the fin type number ratio of the various widths is obtained by performing optimization calculation according to the transconductance curve of the fin-HEMT of each width. The algorithm for the calculation is as follows:
step 1: transconductance data determination of fin-HEMTs of different fin widths: the transconductance of fin-HEMTs of widths a1, a2, …, an are respectively: g 1 (V),g 2 (V),…,g n (V) as a function of the gate voltage V. Calculating the first derivative f of transconductance 1 (V)＝dg 1 /dV,f 2 (V)＝dg 2 /dV,…,f n (V)＝dg n /dV
Step 2: determining a gate voltage range corresponding to an available transconductance of the fin-HEMT for each fin width: g 1 (V),g 2 (V),…,g n The available transconductance of (V) corresponds to the gate voltage ranges of: (V) min 1，V max 1),(V min 2，V max 2),…,(V min n，V max n). The corresponding transconductance reaches a maximum value in the available gate voltage range, and the transconductance fluctuation range is smaller than a specific proportion m%, and the specific value can be manually specified. In this embodiment, the fluctuation ratio is 10% to 20%.
Step 3: determining a gate voltage range (Vmin, vmax) corresponding to the available transconductance of the combined fin-HEMT, wherein vmin=min (V min 1,V min 2,…,V min n),Vmax＝max(V max 1,V max 2,…,V max n)。
Step 4: the parameters to be solved are the scaling coefficients of fin-HEMTs for each fin width in the combined tube, namely: c1, c2, …, cn, wherein c1 is 0 or more, c2 is 0 or more, …, cn is 0 or more, and c1+c2+ … +cn=1.
Step 5: within a gate range (Vmin, vmax) corresponding to the available transconductance, an optimization objective function is defined: o (V) = [ c1·f ] 1 (V)+c2·f 2 (V)+…+cn·f n (V)] 2 。
Step 6: assuming an initial value of the scaling factor: c1 =c2= … =cn=1/n, and the extremum of the band constraint condition (step 4) is solved for the objective function o (V) in the available transconductance range (Vmin, vmax), and the specifically used mathematical calculation method may be newton method, conjugate gradient method, or the like.
The proportion of the fins with each width can be effectively obtained through the algorithm, and the number of the fins with each width is determined according to the total gain required to be achieved by the circuit system.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (6)
1. A fin field effect transistor, comprising:
a substrate, a buffer layer on the substrate, and a barrier layer on the buffer layer;
a source, a drain, and a gate on the barrier layer, the gate being between the source and drain;
the barrier layer comprises a plurality of fins which are arranged in parallel and at intervals, are positioned in a region between the source electrode and the drain electrode and are perpendicular to the grid electrode;
the fins have a width a1, a2, a3, a4, & an, the number of fins having a1 b1, the number of fins having a2 b2 a3 a bn a3 b, and so on, wherein a1, a2, a3, a4, & an is any integer between 10-200, b1, b2, b3, b4, & bn is any positive integer, and the width units are nm;
the ratio of the number of fins per width is calculated according to the following function:
o(V)＝[c1·f 1 (V)+c2·f 2 (V)+…+cn·f n (V)] 2
where c1 is the proportionality coefficient of a1 width fins occupying the total number of fins, i.e. c1=b1/(b1+b2+ … +bn), c2 is the proportionality coefficient of a2 width fins, i.e. c2=b2/(b1+b2+ … +bn), cn is the proportionality coefficient of an width fin, i.e. cn=bn/(b1+b2+ … +bn), o (V) is the target optimization function used to calculate the proportionality coefficient, f 1 (V) first derivative of transconductance of FET with fin width a1, f 2 (V) first derivative of transconductance of FET with fin width a2, f n (V) is the first derivative of the transconductance of the fin-wide an field effect transistor;
the gate surrounds the top surface and the opposite sides of the fin.
2. The finfet of claim 1, wherein grooves are provided between the fins, and the gate spans all grooves and fins.
3. The finfet of claim 2, wherein a portion of the gate electrode within the recess is in contact with the buffer layer.
4. The finfet of claim 1, wherein the a1, a2, a3, a4,..satisfy an arithmetic progression, i.e., an = a1+d (n-1), where d is any integer between 5 and 60.
5. The finfet of claim 1, wherein f 1 (V)＝dg 1 /dV，f 2 (V)＝dg 2 /dV，…，f n (V)＝dg n dV, g 1 (V)，g 2 (V)，…，g n (V) is the transconductance of the field effect transistors with fin widths a1, a2, …, an, respectively, and V is the gate voltage.
6. The finfet of claim 5, wherein g 1 (V)，g 2 (V)，…，g n The available gate voltage ranges of (V) are: (V) min 1，V max 1)，(V min 2，V max 2)，…，(V min n，V max n), the corresponding transconductance reaches a maximum value in the available gate voltage range, and the fluctuation range of the transconductance is smaller than the proportion m%.
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| CN110071172B (en) * | 2019-04-28 | 2022-03-18 | 苏州汉骅半导体有限公司 | Semiconductor device and method for manufacturing the same |
| CN111584619A (en) * | 2020-05-28 | 2020-08-25 | 浙江大学 | GaN device and preparation method |
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| CN105679824A (en) * | 2014-11-18 | 2016-06-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and fabrication method thereof |
| US9397099B1 (en) * | 2015-01-29 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a plurality of fins and method for fabricating the same |
| US9536989B1 (en) * | 2016-02-15 | 2017-01-03 | Globalfoundries Inc. | Field-effect transistors with source/drain regions of reduced topography |
| WO2018103606A1 (en) * | 2016-12-08 | 2018-06-14 | 中国电子科技集团公司第五十五研究所 | Gan fin-typed transistor having high linearity and high electron mobility, and manufacturing method thereof |
| CN209561415U (en) * | 2018-12-29 | 2019-10-29 | 苏州汉骅半导体有限公司 | A kind of fin field effect pipe |
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| US6864519B2 (en) * | 2002-11-26 | 2005-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS SRAM cell configured using multiple-gate transistors |
| US7332386B2 (en) * | 2004-03-23 | 2008-02-19 | Samsung Electronics Co., Ltd. | Methods of fabricating fin field transistors |
| US8881084B2 (en) * | 2010-05-14 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET boundary optimization |
| US8803247B2 (en) * | 2011-12-15 | 2014-08-12 | United Microelectronics Corporation | Fin-type field effect transistor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679824A (en) * | 2014-11-18 | 2016-06-15 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and fabrication method thereof |
| US9397099B1 (en) * | 2015-01-29 | 2016-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a plurality of fins and method for fabricating the same |
| US9536989B1 (en) * | 2016-02-15 | 2017-01-03 | Globalfoundries Inc. | Field-effect transistors with source/drain regions of reduced topography |
| WO2018103606A1 (en) * | 2016-12-08 | 2018-06-14 | 中国电子科技集团公司第五十五研究所 | Gan fin-typed transistor having high linearity and high electron mobility, and manufacturing method thereof |
| CN209561415U (en) * | 2018-12-29 | 2019-10-29 | 苏州汉骅半导体有限公司 | A kind of fin field effect pipe |
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