CN110071172B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN110071172B
CN110071172B CN201910348146.8A CN201910348146A CN110071172B CN 110071172 B CN110071172 B CN 110071172B CN 201910348146 A CN201910348146 A CN 201910348146A CN 110071172 B CN110071172 B CN 110071172B
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barrier layer
semiconductor structure
gate
semiconductor
layer
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CN110071172A (en
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范谦
倪贤锋
何伟
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Suzhou Han Hua Semiconductors Co Ltd
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Suzhou Han Hua Semiconductors Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, including: providing a wafer comprising N semiconductor structures, wherein each semiconductor structure comprises a bottom, a buffer layer positioned on the substrate, a barrier layer positioned on the buffer layer, and a source electrode and a drain electrode positioned on the barrier layer; forming a first gate on a gate region between a source and a drain on the first semiconductor structure; etching the barrier layers of the gate regions of the other semiconductor structures except the first semiconductor structure, forming grooves in the barrier layer of each semiconductor structure, and forming a gate in each groove, wherein the depth of each groove is unequal and smaller than the thickness of the barrier layer, and N is a positive integer greater than 2. The semiconductor device and the manufacturing method thereof provided by the application improve the linearity of the device by forming barrier layers with different thicknesses in the device.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
A third generation semiconductor material represented by gallium nitride (GaN) has excellent characteristics such as a wide bandgap, high electron mobility, and high breakdown voltage, and thus a high electron mobility field effect transistor (HEMT) based on the gallium nitride material is widely used in the fields of radar, microwave communication, and high voltage power devices. With the rapid development of modern wireless communication, various non-constant envelope modulation modes and multi-carrier technologies are widely applied, and the signals have the characteristics of wide bandwidth, high peak-to-average power ratio (PAR) and the like, so that the linearity of a field effect transistor becomes a very important index in a radio frequency power amplification circuit for the signals. If the linearity of the pipe is poor, this can result in spectral spread outside the signal bandwidth, interfering with adjacent channels, and degrading Adjacent Channel Leakage Ratio (ACLR) performance. Even within the signal bandwidth, the linearity fluctuation of the power amplifier tube leads to increased distortion, thereby degrading the Error Vector Magnitude (EVM) performance of the receiver and increasing the Bit Error Rate (BER). The gallium nitride based HEMT device is mainly used in the application occasions of high power, high frequency and large bandwidth, so the linearity of the HEMT device is of great importance to the performance of the whole radio frequency front end. When the dynamic range of an input signal is expanded, the static operating point of the gallium nitride HEMT device is influenced, so that the amplitude and phase transmission characteristics of the device are changed, distortion is generated on an output signal, and the problem of linearity is generated. How to improve the linearity performance of the HEMT device is a technical difficulty of the gallium nitride radio frequency device. Most of the applications adopt methods such as power back-off, negative feedback, feed-forward, digital pre-distortion (DPD) and the like to match with the nonlinearity of the tube from the perspective of a system, but the linearity performance of the tube still needs to be improved from the perspective of a device to fundamentally solve the problem.
Disclosure of Invention
The application provides a semiconductor device manufacturing method, which comprises the following steps:
providing a wafer comprising N semiconductor structures, wherein each semiconductor structure comprises a bottom, a buffer layer positioned on the substrate, a barrier layer positioned on the buffer layer, and a source electrode and a drain electrode positioned on the barrier layer;
forming a first gate on a gate region between a source and a drain on the first semiconductor structure;
etching the barrier layers of the gate regions of the other semiconductor structures except the first semiconductor structure, forming grooves in the barrier layer of each semiconductor structure, and forming a gate in each groove, wherein the depth of each groove is unequal and smaller than the thickness of the barrier layer, and N is a positive integer greater than 2.
In one embodiment, the barrier layer is a metal nitride with N-type doping composed of Ga element, N element and another group iii element.
In one embodiment, the composition of the other group iii element tapers from the bottom to the top of the barrier layer.
In one embodiment, the further group iii element is Al or In or a combination of Al and In.
In one embodiment, the depth of the groove increases sequentially from the second semiconductor structure to the nth semiconductor structure.
In one embodiment, the step of forming a recess in the barrier layer of each of the semiconductor structures comprises:
coating a first photoresist layer on the second semiconductor structure, defining a second grid electrode region on the first photoresist layer, etching the second grid electrode region, and etching off part of the barrier layer of the second semiconductor structure to form a first groove;
removing the first photoresist layer, coating a second photoresist layer on the third semiconductor structure, defining a third gate region on the second photoresist layer, etching the third gate region, and etching off part of the barrier layer of the third semiconductor structure to form a second groove;
and removing the N-2 photoresist layer, coating an N-1 photoresist layer on the Nth semiconductor structure, defining an Nth grid electrode region on the N-1 photoresist layer, etching the Nth grid electrode region, etching off part of the barrier layer of the Nth semiconductor structure, and forming an N-1 groove.
Correspondingly, the present application also proposes a semiconductor device comprising:
a wafer comprising N semiconductor structures, the semiconductor structures comprising a bottom, a buffer layer on the substrate, a barrier layer on the buffer layer, and a source and a drain on the barrier layer;
and forming a first gate on a gate region between the source and the drain on the first semiconductor structure;
and a groove in the barrier layer formed in the gate region of the semiconductor structure other than the first semiconductor structure;
and a gate electrode positioned in each groove, wherein the depth of each groove is unequal and is less than the thickness of the barrier layer, and N is a positive integer greater than 2.
The semiconductor device and the manufacturing method thereof provided by the application improve the linearity of the device by forming barrier layers with different thicknesses in the device.
Drawings
Fig. 1 is a flow chart of a method of manufacturing a semiconductor device according to the present application;
fig. 2-6 are schematic diagrams illustrating fabrication of a semiconductor device according to one embodiment.
Fig. 7 shows transconductance curves corresponding to three types of field effect transistors and a transconductance curve of a semiconductor device formed by combining the transconductance curves.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the present invention, in "a layer formed over another layer," it may mean that a layer is formed over another layer, but it is not necessary that the layer is in direct physical or electrical contact with another layer (for example, one or more other layers may be present between two layers). However, in some embodiments, "formed on" may mean that a layer is in direct physical contact with at least a portion of a top surface of another layer.
The present embodiment proposes a method for manufacturing a semiconductor device, as shown in fig. 1, including:
s10: providing a wafer comprising N semiconductor structures, wherein each semiconductor structure comprises a bottom, a buffer layer positioned on the substrate, a barrier layer positioned on the buffer layer, and a source electrode and a drain electrode positioned on the barrier layer;
s20: forming a first gate on a gate region between a source and a drain on the first semiconductor structure;
s30: etching the barrier layers of the gate regions of the other semiconductor structures except the first semiconductor structure, forming grooves in the barrier layer of each semiconductor structure, and forming a gate in each groove, wherein the depth of each groove is unequal and smaller than the thickness of the barrier layer, and N is a positive integer greater than 2.
In one embodiment, the wafer includes 4 semiconductor structures, namely a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3 and a fourth semiconductor structure 4, as shown in fig. 2. Each of the semiconductor structures includes a substrate 10, a buffer layer 20 on the substrate, a barrier layer 30 on the buffer layer, and a source 40 and a drain 50 on the barrier layer 30. The substrate 10 material includes but is not limited to sapphire, silicon carbide, silicon, diamond, gallium nitride, aluminum nitride, and the like. The buffer layer 20 and the barrier layer 30 are stacked together to form a heterojunction, and a surface of the buffer layer 20 near one end of the barrier layer 30 forms a two-dimensional electron gas (2DEG), and the 2DEG has a high electron density and a high electron mobility. A typical heterojunction is AlGaN/GaN, i.e. the buffer layer 20 is GaN and the barrier layer 30 is AlGaN. The buffer layer 20 may be nitride such as InN, AlN, AlGaN, InGaN, or the like, and the barrier layer 30 may be alloy material such as InGaN, AlGaInN, or the like. The substrate 10 has a thickness of 50 to 1000 micrometers, the barrier layer 30 has a thickness of 3 to 100 nanometers, and the buffer layer 20 has a thickness of 50 to 10000 nanometers. The source electrode 40 and the drain electrode 50 may be an alloy of any of titanium, aluminum, nickel, and gold.
Referring to fig. 3, a first gate 21 may be formed on the first semiconductor structure 1 by a method such as physical vapor deposition, and the first gate 21 is located in a gate region between a source 40 and a drain 50 of the first semiconductor structure 1. The first gate electrode 21 may be a metal stack of ni/au or pt/au. The first gate 21 and the first semiconductor structure 1 form a first field effect transistor.
Referring to fig. 4, a first photoresist layer may be coated on the wafer, the first photoresist layer covers the entire semiconductor structure, and then a second gate region is formed on the first photoresist layer through exposure and development, the second gate region is located between the source 40 and the drain 50 of the second semiconductor structure 2. The second gate region may be dry etched by plasma, and a portion of the barrier layer at a corresponding position is etched away, so that a first groove 31 is formed on the barrier layer 30. A second gate 22 may then be formed in the first recess 13 by the same method as the first gate. The second gate 22 and the second semiconductor structure 2 form a second field effect transistor.
Referring to fig. 5, a second photoresist layer may be coated on the third semiconductor structure 3. The remaining first photoresist layer needs to be removed first between applications of the second photoresist layer. A second gate region is then formed on the second photoresist layer by exposure to light and development, the second gate region being located between the source 40 and the drain 50 of the third semiconductor structure 3. The second gate region may be dry etched by plasma, and a portion of the barrier layer at a corresponding position is etched away, so that a second groove 32 is formed on the barrier layer 30. The third gate 23 may then be formed in the second recess 32 by the same method as the first gate. The third gate 23 and the third semiconductor structure 3 form a third field effect transistor.
Referring to fig. 6, a third photoresist layer may be coated on the fourth semiconductor structure 4. The remaining second photoresist layer needs to be removed first between applications of the third photoresist layer. A third gate region is then formed on the third photoresist layer by exposure to light and development, the third gate region being located between the source 40 and the drain 50 of the fourth semiconductor structure 4. The third gate region may be dry etched by plasma, and a portion of the barrier layer at a corresponding position is etched away, so that a third groove 33 is formed on the barrier layer 30. The fourth gate 24 may then be formed in the third recess 33 by the same method as the first gate. The fourth gate 24 and the fourth semiconductor structure 4 form a fourth field effect transistor.
The depths of the first, second and third grooves 31, 32, 33 are different, for example, the depth of the first groove 311 is 8nm, the depth of the second groove 32 is 12nm, and the depth of the third groove 33 is 15 nm. Note that the depth of each of the first, second, and third grooves 31, 32, and 33 cannot exceed the thickness of the barrier layer 30. In the present embodiment, the depth of the recess increases from the second semiconductor structure 2 to the fourth semiconductor structure 4, and those skilled in the art can immediately understand that other variation trends of the recess are also within the scope of the present application.
In this embodiment, the lengths of the first gate 21, the second gate 22, the third gate 23, and the fourth gate 24 along the longitudinal direction may not be equal to each other, or the lengths of two or three of the first gate and the second gate may be equal to each other, for example, the length of the first gate 13 is 200um, the length of the second gate 23 is 100um, the length of the third gate 33 is 300um, and the length of the fourth gate 43 is 200 um.
The thickness of a barrier layer of an existing HEMT device is usually not more than 50nm, and the requirement on etching precision is high. In order to solve this problem, the inventors of the present application have found through long-term experimental studies that, when forming the barrier layer, the composition of the introduced Al element is gradually reduced to gradually reduce the Al element in AlGaN, for example, the composition at the bottom end is Al0.25Ga0.75N, the component gradually transited to the top is Al0.17Ga0.83N, the thickness of the barrier layer can be increased to about 100nm, and the electrical properties of the structure, such as carrier concentration and mobility, are consistent with the epitaxial structure of the barrier layer with uniform composition. After the method is used for expanding the thickness of the barrier layer, the difficulty in accurately controlling the etching depth in the subsequent device process is correspondingly reduced.
In order to improve the linearity of the semiconductor device, the inventor of the application finds that the linearity of the device can be effectively improved by connecting the combination devices formed by MIS field effect transistors with different barrier layer thicknesses in parallel through long-term experiments. An important measure of linearity of the rf front-end module is intermodulation distortion (IM), and particularly interference generated by intermodulation distortion of order 3 (IMD3) falls directly near the main frequency band and cannot be filtered out, resulting in poor noise performance. The magnitude of IMD3 distortion power is mainly determined by the second derivative of the transconductance parameter of the FET, and the larger the value of the second derivative of the transconductance, the higher the IMD3 distortion power.
FIG. 7 shows transconductance data for a composite tube formed by field effect transistors having 0nm, 5nm, and 10nm thick barrier layers etched respectively, with the ordinate representing the second derivative (S/V) of unity transconductance2Mm) with the abscissa representing the gate voltage (V)The transconductance data for each of the three fets is also shown in the same figure. In the combined tube, the grid widths of the three field effect tubes are determined according to the ratio of 0.72:0.20: 0.08. As can be seen from the data shown in fig. 7, the transconductance data of each of the three fets fluctuates greatly between (0 and-3), and in order to reduce intermodulation distortion, the dynamic range of the input signal (gate voltage) must be limited so that the second derivative of the transconductance is at a smaller value in this range; when the three tubes form a combined tube according to the grid width ratio, the obvious transconductance data fluctuation is small, the dynamic range of the device is enlarged, and the linearity is improved.
Correspondingly, the present application also provides a semiconductor device, which has a structure as shown in fig. 6, and includes: and 4 semiconductor structures, namely a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3 and a fourth semiconductor structure 4. Each of the semiconductor structures includes a substrate 10, a buffer layer 20 on the substrate, a barrier layer 30 on the buffer layer, and a source 40 and a drain 50 on the barrier layer. The substrate 10 material includes but is not limited to sapphire, silicon carbide, silicon, diamond, gallium nitride, aluminum nitride, and the like. The buffer layer 20 and the barrier layer 30 are stacked together to form a heterojunction, and a surface of the buffer layer 20 near one end of the barrier layer 30 forms a two-dimensional electron gas (2DEG), and the 2DEG has a high electron density and a high electron mobility. A typical heterojunction is AlGaN/GaN, i.e. the buffer layer 20 is GaN and the barrier layer 30 is AlGaN. The buffer layer 20 may be nitride such as InN, AlN, AlGaN, InGaN, or the like, and the barrier layer 30 may be alloy material such as InGaN, AlGaInN, or the like. The substrate 10 has a thickness of 50 to 1000 micrometers, the barrier layer 30 has a thickness of 3 to 100 nanometers, and the buffer layer 20 has a thickness of 50 to 10000 nanometers. The source electrode 40 and the drain electrode 50 may be an alloy of any of titanium, aluminum, nickel, and gold.
A first gate 21 is formed on the first semiconductor structure 1, and the first gate 21 is located in a gate region between a source 40 and a drain 50 of the first semiconductor structure 1. The first gate electrode 21 may be a metal stack of ni/au or pt/au. The barrier layer 30 between the source electrode 40 and the drain electrode 50 of the second semiconductor structure 2 is formed with a first recess 31, and the recess 31 is formed with a second gate electrode 22. The barrier layer 30 between the source 40 and the drain 50 of the third semiconductor structure 3 is formed with a second recess 32, and the recess 32 is formed with a third gate 23. The barrier layer 30 between the source 40 and the drain 50 of the fourth semiconductor structure 4 is formed with a third recess 33, and the recess 33 is formed with a fourth gate 24.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising:
providing a wafer comprising N semiconductor structures, wherein each semiconductor structure comprises a substrate, a buffer layer positioned on the substrate, a barrier layer positioned on the buffer layer, and a source electrode and a drain electrode positioned on the barrier layer;
forming a first gate on a gate region between a source and a drain on the first semiconductor structure;
etching the barrier layers of the gate regions of the other semiconductor structures except the first semiconductor structure, forming grooves in the barrier layer of each semiconductor structure, and forming a gate in each groove, wherein the depth of each groove is unequal and smaller than the thickness of the barrier layer, and N is a positive integer greater than 2.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the barrier layer is a metal nitride having N-type doping, which is composed of Ga element, N element, and another group iiia element.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the composition of the other group iiia element is gradually decreased from the bottom to the top of the barrier layer.
4. The manufacturing method of a semiconductor device according to claim 2, wherein the other group iiia element is Al or In or a combination of Al and In.
5. The manufacturing method of a semiconductor device according to claim 1, wherein the depth of the recess increases in order from the second semiconductor structure to the nth semiconductor structure.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a recess in the barrier layer of each of the semiconductor structures comprises:
coating a first photoresist layer on the second semiconductor structure, defining a second grid electrode region on the first photoresist layer, etching the second grid electrode region, and etching off part of the barrier layer of the second semiconductor structure to form a first groove;
removing the first photoresist layer, coating a second photoresist layer on the third semiconductor structure, defining a third gate region on the second photoresist layer, etching the third gate region, and etching off part of the barrier layer of the third semiconductor structure to form a second groove;
and removing the N-2 photoresist layer, coating an N-1 photoresist layer on the Nth semiconductor structure, defining an Nth grid electrode region on the N-1 photoresist layer, etching the Nth grid electrode region, etching off part of the barrier layer of the Nth semiconductor structure, and forming an N-1 groove.
7. A semiconductor device, comprising:
a wafer comprising N semiconductor structures, the semiconductor structures comprising a substrate, a buffer layer on the substrate, a barrier layer on the buffer layer, and source and drain electrodes on the barrier layer;
and forming a first gate on the gate region between the source and the drain on the first semiconductor structure;
and a groove in the barrier layer formed in the gate region of the semiconductor structure other than the first semiconductor structure;
and the grid electrode is positioned in each groove, the depth of each groove is unequal and is smaller than the thickness of the barrier layer, and N is a positive integer larger than 2.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065635A (en) * 1992-06-18 1994-01-14 Murata Mfg Co Ltd Manufacturing method of two-dimensional electron gas semiconductor device
JPH10270463A (en) * 1997-03-27 1998-10-09 Nec Corp Field effect transistor
CN103794643A (en) * 2014-01-22 2014-05-14 西安电子科技大学 High voltage device based on trench gate and manufacturing method thereof
CN109461774A (en) * 2018-11-01 2019-03-12 电子科技大学 A kind of HEMT device of the block containing high dielectric coefficient medium
CN109524462A (en) * 2018-12-29 2019-03-26 苏州汉骅半导体有限公司 A kind of fin field effect pipe

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065635A (en) * 1992-06-18 1994-01-14 Murata Mfg Co Ltd Manufacturing method of two-dimensional electron gas semiconductor device
JPH10270463A (en) * 1997-03-27 1998-10-09 Nec Corp Field effect transistor
CN103794643A (en) * 2014-01-22 2014-05-14 西安电子科技大学 High voltage device based on trench gate and manufacturing method thereof
CN109461774A (en) * 2018-11-01 2019-03-12 电子科技大学 A kind of HEMT device of the block containing high dielectric coefficient medium
CN109524462A (en) * 2018-12-29 2019-03-26 苏州汉骅半导体有限公司 A kind of fin field effect pipe

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