CN109727862B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109727862B CN109727862B CN201811631049.1A CN201811631049A CN109727862B CN 109727862 B CN109727862 B CN 109727862B CN 201811631049 A CN201811631049 A CN 201811631049A CN 109727862 B CN109727862 B CN 109727862B
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Abstract
The application provides a semiconductor device manufacturing method, which comprises the following steps: providing a wafer, wherein the wafer comprises N semiconductor structures, and the semiconductor structures comprise a semiconductor layer and a source electrode and a drain electrode which are positioned on the semiconductor layer; forming a first gate between a source and a drain on the first semiconductor structure; forming a first dielectric layer on the wafer, and forming a second grid electrode on the first dielectric layer between the source electrode and the drain electrode of the second semiconductor structure; forming a second dielectric layer on the wafer, and forming a third grid electrode on the second dielectric layer between the source electrode and the drain electrode of the third semiconductor structure; and forming an Nth dielectric layer on the wafer, and forming an N +1 th grid electrode on the Nth dielectric layer between the source electrode and the drain electrode of the N +1 th semiconductor structure, wherein N is a positive integer greater than 1. According to the semiconductor device and the manufacturing method thereof, the dielectric layers with different thicknesses are formed in the device, so that the linearity of the device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
A third generation semiconductor material represented by gallium nitride (GaN) has excellent characteristics such as a wide bandgap, high electron mobility, and high breakdown voltage, and thus a high electron mobility field effect transistor (HEMT) based on the gallium nitride material is widely used in the fields of radar, microwave communication, and high voltage power devices. With the rapid development of modern wireless communication, various non-constant envelope modulation modes and multi-carrier technologies are widely applied, and the signals have the characteristics of wide bandwidth, high peak-to-average power ratio (PAR) and the like, so that the linearity of a field effect transistor becomes a very important index in a radio frequency power amplification circuit for the signals. If the linearity of the pipe is poor, this can result in spectral spread outside the signal bandwidth, interfering with adjacent channels, and degrading Adjacent Channel Leakage Ratio (ACLR) performance. Even within the signal bandwidth, the linearity fluctuation of the power amplifier tube leads to increased distortion, thereby degrading the Error Vector Magnitude (EVM) performance of the receiver and increasing the Bit Error Rate (BER). The gallium nitride based HEMT device is mainly used in the application occasions of high power, high frequency and large bandwidth, so the linearity of the HEMT device is of great importance to the performance of the whole radio frequency front end. When the dynamic range of an input signal is expanded, the static operating point of the gallium nitride HEMT device is influenced, so that the amplitude and phase transmission characteristics of the device are changed, distortion is generated on an output signal, and the problem of linearity is generated. How to improve the linearity performance of the HEMT device is a technical difficulty of the gallium nitride radio frequency device. Most of the applications adopt methods such as power back-off, negative feedback, feed-forward, digital pre-distortion (DPD) and the like to match with the nonlinearity of the tube from the perspective of a system, but the linearity performance of the tube still needs to be improved from the perspective of a device to fundamentally solve the problem.
Disclosure of Invention
The application provides a semiconductor device manufacturing method, which comprises the following steps:
providing a wafer, wherein the wafer comprises N +1 semiconductor structures, and each semiconductor structure comprises a semiconductor layer and a source electrode and a drain electrode which are positioned on the semiconductor layer;
forming a first gate between a source and a drain on the first semiconductor structure;
forming a first dielectric layer on the wafer, and forming a second grid electrode on the first dielectric layer between the source electrode and the drain electrode of the second semiconductor structure;
forming a second dielectric layer on the wafer, and forming a third grid electrode on the second dielectric layer between the source electrode and the drain electrode of the third semiconductor structure;
and forming an Nth dielectric layer on the wafer, and forming an N +1 th grid electrode on the Nth dielectric layer between the source electrode and the drain electrode of the N +1 th semiconductor structure, wherein N is a positive integer greater than 1.
In one embodiment, the thickness of the Nth dielectric layer is 1nm-10 nm.
In one embodiment, the thickness of each dielectric layer is equal.
In one embodiment, the semiconductor layer includes a substrate, a buffer layer on the substrate, and a barrier layer on the buffer layer.
In one embodiment, the buffer layer material is GaN, InN, AlN, AlGaN, or InGaN.
In one embodiment, the barrier layer material is a ternary or quaternary nitride compound semiconductor alloy.
Correspondingly, the present application also proposes a semiconductor device comprising:
the wafer comprises N +1 semiconductor structures, and each semiconductor structure comprises a semiconductor layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are positioned on the semiconductor layer;
and a first gate located between the source and the drain on the first semiconductor structure;
the second grid electrode is positioned on the first dielectric layer and is positioned between the source electrode and the drain electrode on the second semiconductor structure;
a third gate on the second dielectric layer and between the source and the drain of the third semiconductor structure
And the like, and an N +1 th grid electrode which is positioned on the Nth dielectric layer and is positioned between the source electrode and the drain electrode on the (N + 1) th semiconductor structure, wherein N is a positive integer greater than 1.
According to the semiconductor device and the manufacturing method thereof, the dielectric layers with different thicknesses are formed in the device, so that the linearity of the device is improved.
Drawings
FIG. 1 is a flow chart of a method for fabricating a semiconductor device according to one embodiment;
fig. 2-6 are schematic diagrams illustrating fabrication of a semiconductor device according to one embodiment.
Fig. 7 shows transconductance curves corresponding to three types of field effect transistors and a transconductance curve of a semiconductor device formed by combining the transconductance curves.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the present invention, in "a layer formed over another layer," it may mean that a layer is formed over another layer, but it is not necessary that the layer is in direct physical or electrical contact with another layer (for example, one or more other layers may be present between two layers). However, in some embodiments, "formed on" may mean that a layer is in direct physical contact with at least a portion of a top surface of another layer.
The present application provides a method for manufacturing a semiconductor device, as shown in fig. 1, including:
s10: providing a wafer, wherein the wafer comprises N +1 semiconductor structures, and the semiconductor structures comprise a semiconductor layer and a source electrode and a drain electrode which are positioned on the semiconductor layer;
s20: forming a first gate between a source and a drain on the first semiconductor structure;
s30: forming a first dielectric layer on the wafer, and forming a second grid electrode on the first dielectric layer between the source electrode and the drain electrode of the second semiconductor structure;
s40: forming a second dielectric layer on the wafer, and forming a third grid electrode on the second dielectric layer between the source electrode and the drain electrode of the third semiconductor structure;
s50: and forming an Nth dielectric layer on the wafer, and forming an N +1 th grid electrode on the Nth dielectric layer between the source electrode and the drain electrode of the N +1 th semiconductor structure, wherein N is a positive integer greater than or equal to 1.
In one embodiment, the wafer includes 4 semiconductor structures, namely a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3 and a fourth semiconductor structure 4, as shown in fig. 2. The first semiconductor structure 1 includes a first semiconductor layer 10, and a first source electrode 11 and a first drain electrode 12 on the first semiconductor layer 10, and the first semiconductor layer 10 may be an epitaxial layer including a substrate, a buffer layer, and a barrier layer. The second semiconductor structure 2 includes a second semiconductor layer 20 and a second source electrode 21 and a second drain electrode 22 on the second semiconductor layer 20, and the second semiconductor layer 20 may be an epitaxial layer including a substrate, a buffer layer, and a barrier layer. The third semiconductor structure 3 includes a third semiconductor layer 30 and a third source electrode 31 and a third drain electrode 32 on the third semiconductor layer 30, and the third semiconductor layer 30 may be an epitaxial layer including a substrate, a buffer layer, and a barrier layer. The fourth semiconductor structure 4 includes a fourth semiconductor layer 40 and a fourth source electrode 41 and a fourth drain electrode 42 on the fourth semiconductor layer 40, and the fourth semiconductor layer 40 may be an epitaxial layer including a substrate, a buffer layer, and a barrier layer.
Referring to fig. 3, a first gate 13 may be formed on the first semiconductor structure 1 by a method such as physical vapor deposition, wherein the first gate 13 is located between the first source 11 and the first drain 12. The first gate 13 and the first semiconductor structure 1 form a first field effect transistor.
Referring to fig. 4, the wafer may be placed in an apparatus such as Atomic Layer Deposition (ALD), ultra-high vacuum chemical vapor deposition (UHCVD), Molecular Beam Epitaxy (MBE), and a first dielectric layer 5 is grown on the wafer by a deposition method, wherein the first dielectric layer 5 is formed to cover the entire semiconductor structure. The first dielectric layer 5 may be made of silicon nitride (Si2N3), aluminum oxide (Al2O3), zirconium oxide (ZrO2), silicon dioxide (SiO2), or the like. After the first dielectric layer 5 is formed, a second gate 23 may be formed on the first dielectric layer 5 by the same method as that for forming the first gate 13, and the second gate 23 is located between the second source 21 and the second drain 22. The second gate 23, the second semiconductor structure 2 and the first dielectric layer 5 between the second source 21 and the second drain 22 form a second field effect transistor.
Referring to fig. 5, a second dielectric layer 6 may be formed on the surface of the wafer by the same method as the first dielectric layer 5, and the second dielectric layer 6 covers the first dielectric layer 5 and the second gate 23. The material of the second dielectric layer 6 is the same as that of the previous dielectric layer. After the second dielectric layer 6 is formed, a third gate 33 may be formed on the second dielectric layer 6 by the same method as that for forming the first gate 13, where the third gate 33 is located between the third source 31 and the third drain 32. The third gate 33, the second semiconductor structure 3, and the second dielectric layer 6 and the first dielectric layer 5 between the third source 31 and the third drain 32 constitute a third field effect transistor.
Referring to fig. 6, a third dielectric layer 7 may be formed on the surface of the wafer by the same method as the first dielectric layer 5, and the third dielectric layer 7 covers the second dielectric layer 6 and the third gate 33. The material of the third dielectric layer 7 is the same as that of the previous dielectric layer. After the third dielectric layer 7 is formed, a fourth gate 43 may be formed on the third dielectric layer 7 by the same method as that for forming the first gate 13, and the fourth gate 43 is located between the fourth source 41 and the fourth drain 42. The third gate 43, the fourth semiconductor structure 4, and the third dielectric layer 7, the second dielectric layer 6 and the first dielectric layer 5 between the fourth source 41 and the fourth drain 42 constitute a fourth field effect transistor.
In this embodiment, the thicknesses of the first dielectric layer 5, the second dielectric layer 6, and the third dielectric layer 7 are 1nm to 10nm, which may all be 5nm, or may be 3nm for the first dielectric layer, 5nm for the second dielectric layer, and 7nm for the third dielectric layer, or 8nm for the first dielectric layer, 6nm for the second dielectric layer, and 6nm for the third dielectric layer.
In this embodiment, the lengths of the first gate 13, the second gate 23, the third gate 22, and the fourth gate 43 along the longitudinal direction may not be equal to each other, or the lengths of two or three of the first gate 13, the second gate 23, the third gate 33, and the fourth gate 43 may be equal to each other, for example, the length of the first gate 13 is 200um, the length of the second gate 23 is 100um, the length of the third gate 33 is 300um, and the length of the fourth gate 43 is 200 um.
In order to improve the linearity of the semiconductor device, the inventor of the application finds that the linearity of the device can be effectively improved by connecting the combination device formed by MIS field effect transistors with different dielectric layer thicknesses in parallel through long-term experiments. An important measure of linearity of the rf front-end module is intermodulation distortion (IM), and particularly interference generated by intermodulation distortion of order 3 (IMD3) falls directly near the main frequency band and cannot be filtered out, resulting in poor noise performance. The magnitude of IMD3 distortion power is mainly determined by the second derivative of the transconductance parameter of the FET, and the larger the value of the second derivative of the transconductance, the higher the IMD3 distortion power.
FIG. 7 shows transconductance data for a composite transistor formed with 0nm, 5nm and 10nm silicon nitride dielectric layer field effect transistors, with the ordinate representing the second derivative (S/V) of unity transconductance2Mm), the abscissa represents the gate voltage (V), and the transconductance data for each of the three fets are also shownIn the same figure. In the combined tube, the grid widths of the three field effect tubes are determined according to the ratio of 0.13:0.28: 0.59. As can be seen from the data shown in fig. 7, the transconductance data of each of the three fets fluctuates greatly between (-1,2), and in order to reduce intermodulation distortion, the dynamic range of the input signal (gate voltage) must be limited so that the second derivative of the transconductance is at a smaller value in this range; when the three tubes form a combined tube according to the grid width ratio, the obvious transconductance data fluctuation is small, the dynamic range of the device is enlarged, and the linearity is improved.
In this embodiment, the method for manufacturing a semiconductor device proposed in the present application is described by taking 4 semiconductor structures as an example, and it can be understood by those skilled in the art that the number of the semiconductor structures may be other, and the method proposed in the present application is applicable to the case where N is greater than 1.
Accordingly, the present application also proposes a semiconductor device, as shown in fig. 6, including: the wafer comprises 4 semiconductor structures, namely a first semiconductor structure 1, a second semiconductor structure 2, a third semiconductor structure 3 and a fourth semiconductor structure 4. The first semiconductor structure 1 includes a first semiconductor layer 10 and a first source electrode 11 and a first drain electrode 12 on the first semiconductor layer 10. The second semiconductor structure 2 includes a second semiconductor layer 20 and a second source electrode 21 and a second drain electrode 22 on the second semiconductor layer 20. The third semiconductor structure 3 includes a third semiconductor layer 30 and a third source electrode 31 and a third drain electrode 32 on the third semiconductor layer 30. The fourth semiconductor structure 4 includes a fourth semiconductor layer 40 and a fourth source electrode 41 and a fourth drain electrode 42 on the fourth semiconductor layer 40. The first semiconductor layer 10, the second semiconductor layer 20, the third semiconductor layer 30, and the fourth semiconductor layer 40 may be epitaxial layers including a substrate, a buffer layer, and a barrier layer, which are sequentially stacked. The substrate material includes, but is not limited to, sapphire, silicon carbide, silicon, diamond, gallium nitride, and aluminum nitride. The buffer layer and the barrier layer are stacked together to form a heterojunction, the surface of the buffer layer close to one end of the barrier layer forms a two-dimensional electron gas (2DEG), and the 2DEG has high electron density and high electron mobility. A typical heterojunction is AlGaN/GaN, i.e. the buffer layer is GaN and the barrier layer is AlGaN. The buffer layer can also be nitride such as GaN, AlN, AlGaN, InGaN and the like, and the barrier layer can also be one or the superposition of a plurality of ternary or quaternary nitride compound semiconductor alloy materials such as InAlN, AlN, ScAlN and the like. The thickness of the substrate is 50um-1000um, the thickness of the barrier layer is 3nm-100nm, and the thickness of the buffer layer is 50nm-10000 nm.
Three medium layers, namely a first medium layer 5, a second medium layer 6 and a third medium layer 7, are sequentially stacked on the wafer. The first dielectric layer 5 is located on the wafer, the second dielectric layer 6 is located on the first dielectric layer 5, and the third dielectric layer 7 is located on the second dielectric layer 6. The material of the first dielectric layer 5, the second dielectric layer 6 and the third dielectric layer 7 can be silicon nitride or silicon dioxide. The thicknesses of the first dielectric layer 5, the second dielectric layer 6 and the third dielectric layer 7 are 1nm-10nm, and can be 5nm, or 3nm for the first dielectric layer, 5nm for the second dielectric layer and 7nm for the third dielectric layer, or 8nm for the first dielectric layer, 6nm for the second dielectric layer and 6nm for the third dielectric layer.
The first semiconductor structure has a first gate 13 thereon, and the first gate 13 is located between the first source 11 and the first drain 12. The first dielectric layer 5 is provided with a second gate 23, and the second gate 23 is located between the second source 21 and the second drain 22. The second dielectric layer 6 is provided with a third gate 33, and the third gate 33 is located between the third source 31 and the third drain 32. The third dielectric layer 7 is provided with a fourth gate 43, and the fourth gate 43 is located between the fourth source 41 and the fourth drain 42. The first source electrode, the second source electrode, the third source electrode and the fourth source electrode can be made of any alloy of titanium, aluminum, nickel and gold. The first drain electrode, the second drain electrode, the third drain electrode and the fourth drain electrode may be an alloy of any of titanium, aluminum, nickel and gold. The first gate, the second gate, the third gate and the fourth gate may be a metal stack of nickel/gold or platinum/gold.
The lengths of the first gate 13, the second gate 23, the third gate 22, and the fourth gate 43 along the longitudinal direction may not be equal to each other, or the lengths of two or three of the first gate 13 and the second gate 23 may be equal to each other, for example, the length of the first gate 13 is 200um, the length of the second gate 23 is 100um, the length of the third gate 33 is 300um, and the length of the fourth gate 43 is 200 um.
In this embodiment, the semiconductor device proposed in this application is described by taking 4 semiconductor structures as an example, and it can be understood by those skilled in the art that the number of the semiconductor structures may be other, and the structure proposed in this application is applicable to all cases where N is greater than 1.
According to the semiconductor device and the manufacturing method thereof, various field effect transistors can be formed on one wafer by controlling the thickness of the dielectric layer, and the linearity of the semiconductor device can be effectively improved due to the fact that different field effect transistors are different in thickness of the dielectric layer.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method of manufacturing a semiconductor device, comprising:
providing a wafer, wherein the wafer comprises N +1 semiconductor structures, and the semiconductor structures comprise a semiconductor layer and a source electrode and a drain electrode which are positioned on the semiconductor layer;
forming a first gate between a source and a drain on the first semiconductor structure;
forming a first dielectric layer on the wafer, and forming a second grid electrode on the first dielectric layer between the source electrode and the drain electrode of the second semiconductor structure;
forming a second dielectric layer on the wafer, and forming a third grid electrode on the second dielectric layer between the source electrode and the drain electrode of the third semiconductor structure;
and forming an Nth dielectric layer on the wafer, and forming an N +1 th grid electrode on the Nth dielectric layer between the source electrode and the drain electrode of the N +1 th semiconductor structure, wherein N is a positive integer greater than 1.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the Nth dielectric layer is 1nm to 10 nm.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of each dielectric layer may be equal or different.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer comprises a substrate, a buffer layer on the substrate, and a barrier layer on the buffer layer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the buffer layer material is GaN, InN, AlN, AlGaN, or InGaN.
6. The manufacturing method of a semiconductor device according to claim 4, wherein the barrier layer material is a ternary or quaternary nitride compound semiconductor alloy.
7. The method of claim 1, wherein the source, gate and drain of the N +1 semiconductor structures are connected together to form a composite fet.
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Address after: 215000 west side of b0-1f, Zhongyuan industrial building, No. 259, Changyang street, Suzhou Industrial Park, Suzhou area, China (Jiangsu) pilot Free Trade Zone, Suzhou City, Jiangsu Province Patentee after: Suzhou Han Hua Semiconductor Co.,Ltd. Address before: Room 303, building 11, Northwest District, Suzhou nano City, 99 Jinjihu Avenue, Suzhou Industrial Park, 215000, Jiangsu Province Patentee before: Suzhou Han Hua Semiconductor Co.,Ltd. |