CN109545852B - Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof - Google Patents

Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof Download PDF

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CN109545852B
CN109545852B CN201910060484.1A CN201910060484A CN109545852B CN 109545852 B CN109545852 B CN 109545852B CN 201910060484 A CN201910060484 A CN 201910060484A CN 109545852 B CN109545852 B CN 109545852B
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CN109545852A (en
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张雅超
马晓华
任泽阳
张进成
郝跃
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Jiangxi Wannian Crystal Semiconductor Co ltd
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Xidian University
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention relates to a nonpolar InAlN/GaN high electron mobility transistor and a preparation method thereof, wherein the preparation method comprises the following steps: s1, selecting a nonpolar GaN material as a substrate; s2, growing GaN on the substrate to form a nonpolar channel layer; s3, growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer; and S4, manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor. According to the preparation method of the nonpolar InAlN/GaN high-electron-mobility transistor, the nonpolar channel layer and the nonpolar barrier layer are formed under certain process conditions, the nonpolar channel layer and the nonpolar barrier layer form a nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that generation of high-density polarization charges in the channel is inhibited, and an enhancement effect is achieved.

Description

Nonpolar InAlN/GaN high electron mobility transistor and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a nonpolar InAlN/GaN high-electron-mobility transistor and a preparation method thereof.
Background
Because the channel of the GaN-based heterostructure has high-mobility two-dimensional electron gas, GaN becomes the most ideal material for preparing high-performance electronic devices. Since the first proposal by k.han et al of the concept of GaN-based heterostructures, heterostructures represented by AlGaN/GaN, InAlN/GaN, AlN/GaN, etc. have achieved significant research results in the fabrication of high electron mobility transistors. Up to now, the cut-off frequency of a High Electron Mobility Transistor (HEMT) based on a conventional AlGaN/GaN heterostructure has broken through 200GHz, and the maximum oscillation frequency has broken through 300 GHz.
Transistor devices based on conventional polar c-plane III-nitride heterostructures are depletion mode devices, i.e., the devices exhibit an on-state at zero bias, requiring an applied bias voltage to reach an off-state. This property not only causes the device to lose power in the non-operating state, but also causes the device to have a safety hazard in power electronic applications. In addition, in a digital circuit system, the realization of various logic functions cannot be completed only by means of depletion devices. Therefore, the fabrication of high performance enhancement mode (normally-off) devices is a hot spot and focus of current GaN-based electronic device research.
At present, technologies for realizing enhancement devices mainly include a p-GaN cap layer structure preparation technology, a recessed gate structure preparation technology, a fluorine ion implantation technology, and the like, but the conventional technologies have serious adverse effects while realizing enhancement.
The p-GaN cap layer preparation technology comprises the following steps: the working principle of the p-GaN cap layer technology is similar to that of a pn junction, and p-type GaN and an n-type AlGaN barrier layer can generate a pn junction electric field to generate depletion effect on two-dimensional electron gas at an AlGaN/GaN heterojunction interface. However, in the p-GaN cap layer structure, the deposition of the cap layer can not only increase the parasitic capacitance of the device, but also weaken the gate control capability of the device; moreover, the growth of p-type GaN has high requirements on doping technology, the difficulty of GaN epitaxy process which is not overcome yet is present, and the process is difficult to control accurately;
the concave grid structure preparation technology comprises the following steps: the concave grid technology is to etch the AlGaN barrier layer, when the thickness is smaller than the critical value, the AlGaN/GaN heterojunction interface can not generate two-dimensional electron gas, at this time, no electron accumulation is under the grid, and the device is in the normally-off state. However, for the recessed gate structure, the too thin barrier layer can cause the depth of a channel potential well to be shallow, so that the confinement property of a carrier is reduced; moreover, the dry etching process can damage the material structure, and the stability and the repeatability of the process are poor, so that the process is not beneficial to large-scale production; in addition, the threshold voltage of the device with the concave gate structure can only reach a level slightly larger than 0V, and higher threshold voltage cannot be obtained.
Fluorine ion implantation technology: the principle of the fluorine ion implantation technology is that fluorine plasma treatment is carried out on an AlGaN barrier layer in a gate region through plasma equipment, partial fluorine ions enter the AlGaN barrier layer to form a negative electric center, and a potential field formed around the negative electric center generates a depletion effect on channel electrons so as to form an enhancement type device. However, the fluorine ion implantation process may cause an increase in trap states and defect damage in the barrier layer, affecting device performance, especially affecting the stability of the device under high temperature conditions; in addition, although the traditional process method can achieve the purpose of depleting current carriers in a channel, polarization charges at the interface of the heterostructure still exist; the prior art shows that when device processes such as gate dielectric deposition are carried out, negative drift of the threshold voltage of the device can be caused by polarization charges, and potential hazards exist in reliability.
In summary, there are many problems in the technology for realizing the enhancement type device at home and abroad, which mainly reflect on the aspects of poor process repeatability, damage to materials and devices caused by the process, influence on the stability of the device caused by the process, and the like, thereby influencing the performance and reliability of the enhancement type device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a nonpolar InAlN/GaN high electron mobility transistor and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a nonpolar InAlN/GaN high electron mobility transistor, which comprises the following steps:
s1, selecting a nonpolar GaN material as a substrate;
s2, growing GaN on the substrate to form a nonpolar channel layer;
s3, growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer;
s4, manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor.
In an embodiment of the present invention, step S1 is followed by:
s11, performing nitridation treatment on the substrate at the temperature of 828-1012 ℃;
s12, processing the substrate, wherein the processing process comprises the following steps: growing a GaN film on a substrate, performing etching treatment on the GaN film, growing the GaN film, and performing etching treatment on the GaN film for a preset cycle.
In one embodiment of the present invention, step S2 includes:
and growing GaN under the conditions that the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-10 Torr, the flow range of the Ga source is 9-11 sccm, and the flow range of the N source is 90-110 sccm to form the non-polar channel layer.
In one embodiment of the present invention, step S3 includes:
s31, growing AlN on the nonpolar channel layer to form an insertion layer;
and S32, growing InAlN on the insertion layer to form the nonpolar barrier layer.
In one embodiment of the present invention, step S32 includes:
InAlN is grown under the conditions that the temperature range of the base is 648-792 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow range of the Al source is 10-14 sccm, the flow range of the N source is 900-1100 sccm, and the flow range of the In source is 72-88 sccm, and the non-polar barrier layer is formed.
In one embodiment of the invention, the material of the non-polar barrier layer is In1-xAlxN, wherein x ranges from 80% to 85%.
In one embodiment of the present invention, step S4 includes:
s41, depositing a first metal material on the nonpolar barrier layer by using a metal evaporation method, and annealing the first metal material to enable the first metal material to sink to the nonpolar channel layer to form a source electrode and a drain electrode;
s42, etching the nonpolar barrier layer and the nonpolar channel layer to form an isolation groove;
and S43, depositing a second metal material on the nonpolar barrier layer by using a metal evaporation method to form a grid electrode.
In one embodiment of the present invention, after the source, the drain and the gate are fabricated on the non-polar barrier layer, the method further comprises:
s5, depositing SiN on the nonpolar barrier layer, the source electrode, the drain electrode and the grid electrode by using a plasma enhanced chemical vapor deposition method to form a protective layer;
and S6, photoetching an interconnection opening region on the protective layer, and manufacturing a metal interconnection layer in the interconnection opening region.
The invention also provides a nonpolar InAlN/GaN high electron mobility transistor which is prepared by the preparation method.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the preparation method of the nonpolar InAlN/GaN high electron mobility transistor, the nonpolar channel layer and the barrier layer are formed under certain process conditions, the nonpolar channel layer and the nonpolar barrier layer form a nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that generation of high-density polarization charges in the channel is inhibited, and an enhancement effect is achieved.
2. The preparation method only depends on the growth control of the in-situ material, avoids the damage of the processes such as etching, ion implantation and the like to the material device, greatly improves the repeatability and stability of the process, ensures the performance and reliability of the enhancement device and can realize the large-scale preparation of the enhancement device.
3. The invention selects the nonpolar GaN homogeneous material based on novel Hydride Vapor Phase Epitaxy (HVPE) as the substrate, not only can effectively relieve the difficulty of epitaxially growing the nonpolar material on the heterogeneous material, but also has important significance for improving the crystallization quality of the epitaxial material, the transport property of a heterostructure and the working performance of HEMTs.
4. The included angle theta between the grid direction and the c-axis direction of the nonpolar InAlN/GaN high electron mobility transistor is more than or equal to 0 degree and less than or equal to 90 degrees, and the influence mechanism of the grid direction on the device characteristics is discussed on the basis of preparing the nonpolar high electron mobility transistor by combining the anisotropy in the nonpolar material plane, so that the nonpolar InAlN/GaN high electron mobility transistor has important significance on the establishment of a nonpolar heterostructure and a related device system.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a c-axis direction and a gate direction of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another non-polar InAlN/GaN HEMT structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the c-axis direction and the gate direction of another nonpolar InAlN/GaN high electron mobility transistor provided by the embodiment of the invention;
FIG. 6 is a schematic diagram of another non-polar InAlN/GaN HEMT structure according to an embodiment of the present invention;
fig. 7 is a schematic view of the c-axis direction and the gate direction of another nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention, including the following steps:
s1, selecting a nonpolar GaN material as the substrate 101;
s2, growing GaN on the substrate to form a nonpolar channel layer;
s3, growing InAlN on the nonpolar channel layer to form a nonpolar barrier layer;
s4, manufacturing a source electrode and a drain electrode in the nonpolar channel layer and the nonpolar barrier layer, and manufacturing a grid electrode on the nonpolar barrier layer to obtain the nonpolar InAlN/GaN high electron mobility transistor.
Specifically, step S1 is followed by:
s11, performing nitridation treatment on the substrate at the temperature range of 828-1012 ℃; preferably, the treatment temperature is 920 ℃;
s12, processing the substrate, wherein the processing process comprises the following steps: growing a GaN film on a substrate, performing etching treatment on the GaN film, growing the GaN film and performing etching treatment on the GaN film for a preset cycle; preferably, the cycle period is 15 times.
Specifically, step S2 includes:
growing GaN under the conditions that the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-11 Torr, the flow range of the Ga source is 9-11 sccm, and the flow range of the N source is 90-110 sccm to form the non-polar channel layer;
preferably, the growth temperature is 100 deg.C, the reaction chamber pressure is 10Torr, the Ga source flow is 10sccm, and the N source flow is 100 sccm.
Specifically, step S3 includes:
s31, growing AlN on the nonpolar channel layer to form an insertion layer;
and S32, growing InAlN on the insertion layer to form a nonpolar barrier layer.
Specifically, step S32 includes:
growing InAlN under the conditions that the temperature range of the base is 648-792 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow range of the Al source is 10-14 sccm, the flow range of the N source is 900-1100 sccm, and the flow range of the In source is 72-88 sccm to form the nonpolar barrier layer;
preferably, the growth temperature is 720 deg.C, the reaction chamber pressure is 200Torr, the flow rate of the Al source is 12sccm, the flow rate of the N source is 1000sccm, and the flow rate of the In source is 80 sccm.
Specifically, the nonpolar barrier layer is made of In1-xAlxN, wherein x ranges from 80% to 85%.
Specifically, step S4 includes:
s41, depositing a first metal material on the nonpolar barrier layer, and annealing the first metal material to enable the first metal material to sink to the nonpolar channel layer to form a source electrode and a drain electrode;
s42, etching the insertion layer, the nonpolar barrier layer and the nonpolar channel layer to form an isolation groove;
and S43, depositing a second metal material on the nonpolar barrier layer by using a metal evaporation method to form a grid electrode.
Specifically, after the source electrode, the drain electrode and the gate electrode are fabricated on the non-polar barrier layer, the method further comprises the following steps:
s5, depositing SiN on the nonpolar barrier layer, the source electrode, the drain electrode and the grid electrode by using a plasma enhanced chemical vapor deposition method to form a protective layer;
and S6, photoetching an interconnection opening region on the protective layer, and manufacturing a metal interconnection layer in the interconnection opening region.
According to the preparation method of the nonpolar InAlN/GaN high-electron-mobility transistor, the nonpolar channel layer and the nonpolar barrier layer are formed under certain process conditions, the nonpolar channel layer and the nonpolar barrier layer form a nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that generation of high-density polarization charges in the channel is inhibited, and an enhancement effect is achieved.
The preparation method provided by the embodiment of the invention only depends on growth control of the in-situ material, avoids damage of processes such as etching and ion implantation to a material device, greatly improves the process repeatability and stability, ensures the performance and reliability of an enhancement device, and can realize large-scale preparation of the enhancement device.
Example two
Referring to fig. 2, fig. 2 is a schematic structural diagram of a nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention, which is prepared by using a purchased semi-insulating nonpolar a-plane homogeneous GaN material as a substrate 101, wherein the semi-insulating nonpolar a-plane homogeneous GaN material is grown by using a Hydride Vapor Phase Epitaxy (HVPE) method.
The embodiment of the invention selects the nonpolar GaN homogeneous material based on the novel hydride vapor phase epitaxy as the substrate, not only can effectively relieve the difficulty of epitaxially growing the nonpolar material on the heterogeneous material, but also has important significance for improving the crystallization quality of the epitaxial material, the transport property of a heterostructure and the working performance of HEMTs.
Due to the fact that anisotropy exists in the nonpolar InAlN/GaN heterostructure surface, the grid direction can cause remarkable influence on device characteristics, and therefore three nonpolar InAlN/GaN high electron mobility transistors are prepared according to different device grid directions, wherein the first grid direction is parallel to the c-axis direction, the included angle between the second grid direction and the c-axis direction is 45 degrees, and the third grid direction is perpendicular to the c-axis direction.
In this embodiment, the gate direction of the nonpolar InAlN/GaN high electron mobility transistor is parallel to the c-axis direction, and the specific steps are as follows:
s1, processing the substrate 101, wherein the substrate 101 is made of a homogeneous nonpolar GaN material, and the specific steps are as follows:
s11, performing high-temperature nitridation treatment on the substrate 101, wherein the treatment temperature is 920 ℃;
placing a substrate 101 above a graphite base to ensure that the substrate normally floats, and then placing the graphite base into a reaction chamber to ensure that the base can normally rotate and revolve; opening reactionThe chamber vacuum pump vacuumizes the reaction chamber to make the vacuum degree of the reaction chamber lower than 1X 10-2Torr; introducing mixed gas of high-purity ammonia gas and hydrogen gas into a reaction chamber, and simultaneously continuing to work a vacuum pump of the reaction chamber to keep the reaction chamber in a high-purity ammonia gas atmosphere of 40 Torr; the substrate 101 is high-temperature nitrided under conditions in which the temperature of the stone base is raised to 920 ℃ within 7 minutes by heating the stone base by a radio frequency source and maintained at this temperature for 5 minutes.
Furthermore, the process of high-temperature nitridation treatment of the substrate can eliminate the adverse factors of dangling bonds attached to the surface of the substrate and the like, and provides a good substrate for subsequent reaction.
Furthermore, a nonpolar GaN homogeneous material based on novel Hydride Vapor Phase Epitaxy (HVPE) is selected as the substrate, so that the difficulty of epitaxially growing the nonpolar material on the heterogeneous material can be effectively relieved, and the method has important significance for improving the crystallization quality of the epitaxial material, the transport property of a heterostructure and the working performance of HEMTs.
S12, processing the substrate 101, the processing procedure is: growing a GaN film on a substrate, carrying out annealing etching treatment on the GaN film, and circulating for a preset period;
in the present embodiment, growing GaN-etching GaN film-growing GaN-etching GaN film … …, the process of such a cycle is referred to as a thermal decomposition-regrowth technique.
The method comprises the following specific steps:
firstly, taking trimethyl gallium as a Ga source, taking hydrogen as carrier gas to carry the trimethyl gallium, taking ammonia as an N source, and growing GaN under the condition that the growth rate is 7nm/min, wherein the growth time is 0.5min, so as to form a GaN film; then closing the flow valves of the N source and the Ga source, and continuing for 1 minute to anneal the material in a hydrogen atmosphere, wherein the annealing temperature is 910 ℃, the annealing temperature is the optimal growth temperature of the GaN, and the annealing process at high temperature is the process of etching the GaN film; thus, the cycle is alternated for 15 cycles to complete the processing of the substrate 101.
The thermal decomposition-regrowth technology can inhibit the combination of impurities on the surface of the substrate, the annealing treatment can lead the GaN film on the surface to be largely decomposed and take away the impurities on the surface of the self-supporting substrate, and the GaN reaction atoms are deposited in a superlattice-like mode and can quickly fill up the fluctuation of the material surface caused by hydrogen etching.
S2, growing GaN on the substrate 101 to form the non-polar channel layer 102, the specific steps are as follows:
controlling the temperature of the graphite base to gradually rise to 1000 ℃, introducing a Ga source and an N source into the reaction chamber, and keeping the pressure in the reaction chamber in dynamic balance of 10Torr, wherein trimethyl gallium is used as the Ga source, and the flow rate of the trimethyl gallium is 10 sccm; introducing trimethyl gallium into the carrier gas by hydrogen with the flow rate of 800 sccm; taking ammonia gas as an N source, wherein the flow rate of the ammonia gas is 100 sccm; under this condition, the growth time of GaN was 40 minutes, and the thickness of the non-polar channel layer 102 correspondingly formed was 200 nm.
The requirements for forming the nonpolar structure are as follows: higher growth temperature, lower reaction chamber pressure, and lower flow ratio of group V to group III sources; in this embodiment, the growth temperature of the nonpolar channel layer 102 is 1000 ℃, the pressure of the reaction chamber is 10Torr, and the flow ratio of the N source to the Ga source is 10, all of which conform to the growth conditions of the nonpolar GaN layer, under which the channel layer formed is nonpolar.
Furthermore, the flow rates of the Ga source and the N source which are reaction sources are maintained in a lower range, so that the crystallization quality of the material of the formed nonpolar channel layer is higher, and the flow rate of electrons in the nonpolar channel layer is ensured.
S3, growing InAlN on the nonpolar channel layer 102 to form a nonpolar barrier layer 103; the method comprises the following specific steps:
s31, growing AlN on the nonpolar channel layer 102 to form an insertion layer 1021;
keeping the temperature of the graphite base at 1000 ℃ and the pressure of the reaction chamber at 10Torr, and introducing an Al source and an N source into the reaction chamber, wherein trimethylaluminum is used as the Al source, and the flow rate of the trimethylaluminum is 5 sccm; introducing trimethylaluminum by using hydrogen as carrier gas, wherein the hydrogen flow is 200 sccm; taking ammonia gas as an N source, wherein the flow rate of the ammonia gas is 100 sccm; under this condition, the growth time of GaN was 0.5 minute, and the thickness of the correspondingly formed insertion layer 1021 was 2 nm.
S32, growing InAlN on the insertion layer 1021 to form a nonpolar barrier layer 103;
controlling the temperature of the graphite base to gradually reduce the temperature to 720 ℃, introducing an Al source, an In source and an N source into the reaction chamber, and keeping the pressure In the reaction chamber In a dynamic balance of 200Torr, wherein trimethylaluminum is used as the Al source, and the flow rate of the trimethylaluminum is 12 sccm; taking trimethyl indium as an In source, wherein the flow rate of the trimethyl indium is 80 sccm; introducing trimethylaluminum by taking hydrogen as carrier gas, wherein the hydrogen flow is 800 sccm; carrying in trimethyl indium by taking nitrogen as carrier gas; taking ammonia gas as an N source, wherein the flow rate of the ammonia gas is 1000 sccm; under the condition, the InAlN growth time is 5 minutes, the thickness of the correspondingly formed nonpolar barrier layer 103 is 12nm, and the Al component in the nonpolar barrier layer 103 is 82%.
Further, In this example, the growth temperature was 720 ℃, the pressure In the reaction chamber was 200Torr, the flow ratio of the N source to the Al source was 83, and the flow ratio of the N source to the In source was 12.5, which met the growth conditions of the nonpolar structure, and the barrier layer formed under these conditions was nonpolar.
Further, the flow rate of the In source is higher than that of the Al source, because the bonding energy between the indium atoms and the nitrogen atoms is low, and therefore, the indium-rich environment In the reaction chamber should be maintained when the nonpolar InAlN is grown.
Furthermore, 82% of Al component in the nonpolar barrier layer 103 can realize smectic lattice matching between the barrier layer and the channel layer, and under the condition of the component, the heterostructure keeps a larger energy band offset between the barrier layer and the channel layer on the basis of ensuring that the concentration of intrinsic two-dimensional electron gas in the channel is lower, ensures that a deep potential well is still formed at the channel, and improves the confinement property of a current carrier in the channel.
Further, an ultrathin insertion layer 1021 grows between the nonpolar channel layer 102 and the nonpolar barrier layer 103, because the insertion layer can form an effective barrier between the nonpolar barrier layer and the nonpolar channel layer, and prevent the wave function of the two-dimensional electron gas from diffusing into the nonpolar barrier layer, thereby preventing the alloy disorder scattering in the ternary barrier material from adversely affecting the transport of the two-dimensional electron gas; moreover, the growth conditions of the barrier layer and the channel layer are different, the condition conversion process can cause the influences of uneven airflow, unstable temperature and the like in the reaction chamber, the insertion layer can play a transition role in the conversion of the growth conditions, and the adverse influence of the growth condition mutation on the heterojunction characteristics is effectively eliminated; in addition, the insertion layer can play a role in smoothing the appearance of an interface to a great extent, inhibiting the roughness scattering of the interface and improving the performance of the device.
Furthermore, the inserted layer is made of AlN, the forbidden bandwidth of AlN is large, the heterojunction energy band structure can be modulated by using the advantage of large forbidden bandwidth of AlN, the band step height between the barrier layer and the channel layer is obviously improved, the depth of a potential well is increased, and the domain limitation of two-dimensional electron gas in the channel is improved.
S4, forming a source 104 and a drain 105 in the non-polar channel layer 102 and the non-polar barrier layer 103, and forming a gate 106 on the non-polar barrier layer 103, the steps are as follows:
s41, depositing a metal material on the nonpolar barrier layer 103, and annealing the metal material to sink the metal material to the nonpolar channel layer 102, thereby forming a source electrode 104 and a drain electrode 105;
first, a source electrode region and a drain electrode region are etched on the nonpolar barrier layer 103; then, ohmic metal is deposited on the nonpolar barrier layer 103 in the source electrode area and the drain electrode area and on the photoresist outside the source electrode area and the drain electrode area, wherein the ohmic metal is a metal stack structure composed of four layers of metal, the four layers of metal are sequentially Ti, Al, Ni and Au from bottom to top, and the thicknesses of the four layers of metal are respectively Ti, Al, Ni and Au
Figure BDA0001953981230000131
Then, stripping the ohmic metal on the photoresist outside the source electrode area and the drain electrode area; finally, the sample after the ohmic metal evaporation and peeling is put into a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal on the nonpolar barrier layer 103 in the source electrode region and the drain electrode region sinks to the nonpolar channel layer 102, thereby forming ohmic contact between the ohmic metal and the heterojunction channel and forming the source electrode 104 and the drain electrode 105. Wherein, inThe process conditions of the annealing treatment in the rapid thermal annealing furnace are as follows: annealing atmosphere is N2The annealing temperature was 850 ℃ and the annealing time was 30 s.
Further, a connection line between center points of the surfaces of the source electrode 104 and the drain electrode 105 is parallel to a c-axis direction on the non-polar barrier layer 103, and the c-axis direction is along a horizontal direction of the non-polar barrier layer 103 (i.e., from left to right), please refer to fig. 3, and fig. 3 is a schematic diagram of the c-axis direction and the gate direction of the non-polar InAlN/GaN high electron mobility transistor according to the embodiment of the present invention.
S42, etching the non-polar barrier layer 103, the insertion layer 1021 and the non-polar channel layer 102 to form an isolation trench 1051;
photoetching an electric isolation area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, then washing the sample with ultrapure water and drying the sample with nitrogen, and baking the sample on a hot plate at 110 ℃ for 2 min; then, sequentially etching the nonpolar barrier layer 103, the insertion layer 1021 and the nonpolar GaN channel layer in the electrical isolation region by using an Inductively Coupled Plasma (ICP) process to realize mesa isolation of the active region, wherein the total etching depth is 214 nm; finally, the sample is sequentially placed into an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation region, and then the sample is rinsed with ultrapure water and dried with nitrogen gas to form an isolation trench 1051.
Note that, when the insertion layer 1021 is grown between the nonpolar barrier layer 103 and the nonpolar channel layer 102, the nonpolar barrier layer 103, the insertion layer 1021, and the nonpolar channel layer 102 are etched, thereby forming the isolation trench 1051; when there is no intervening layer 1021 between the nonpolar barrier layer 103 and the nonpolar channel layer 102, the nonpolar barrier layer 103 and the nonpolar channel layer 102 are etched, thereby forming an isolation trench 1051.
S43, depositing a metal material on the non-polar barrier layer 103 by a metal evaporation method to form a gate 106, wherein the direction of the gate 106 is along the center-point connecting line of the surfaces of the source 104 and the drain 105, i.e. the direction of the gate electrode is parallel to the c-axis direction, as shown in fig. 3, wherein the connecting line of the center point a of the source 104 and the center point B of the drain 105 is parallel to the c-axis direction, and the gate 106 is located on the connecting line of a and B, so the gate 108 is parallel to the c-axis;
photoetching a gate electrode area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, controlling the direction of a grid bar (the gate electrode area is generally rectangular, and the direction of a long edge in the rectangle is the direction of the grid bar) to be parallel to the c-axis direction of the surface of the epitaxial wafer, and washing a sample with ultrapure water and drying the sample with nitrogen; then, a schottky metal is evaporated on the nonpolar barrier layer 103 in the gate electrode region and on the photoresist outside the gate electrode region as a gate electrode, wherein the schottky metal is a metal stack structure composed of two layers of metals, which are Ni and Au in sequence from bottom to top, and the thicknesses of Ni and Au are respectively
Figure BDA0001953981230000141
And finally, putting the sample subjected to gate metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove the Schottky metal and the photoresist outside the gate electrode, then putting the sample into an NMP solution for ultrasonic removal of the stripping glue, washing the sample with isopropanol and ultrapure water, and drying with nitrogen to form the gate 106.
Furthermore, the direction of the gate is determined by the relative orientation of the source and the drain, so that when the source and the drain are manufactured, the included angle between the connecting line of the drain and the source and the direction of the c axis is different, and because the gate is positioned between the drain and the source, the included angle between the direction of the gate and the direction of the c axis is different.
S5, depositing SiN on the non-polar barrier layer 105, the source electrode 104, the drain electrode 105 and the gate electrode 106 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a protective layer 107; the method comprises the following specific steps:
cleaning the surface of the sample with the manufactured grid 106, and growing a 200nm SiN protective layer by using a PECVD process, wherein the growth process conditions are as follows: by NH3And SiH4As the reaction gas, the substrate temperature was 300 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 30W.
S6, etching an interconnect opening region on the protection layer 107, and forming a metal interconnect layer 108 on the interconnect opening region, including the following steps:
manufacturing metal interconnection open hole regions of the source electrode 104, the drain electrode 105 and the grid electrode 107 on the protective layer 107 by adopting the processes of gluing, drying glue, exposing, developing, stripping and the like, and carrying out ultra-pure water washing and nitrogen blow-drying on a sample; then, etching the protection layer 107 in the metal interconnection open pore region to form a metal interconnection open pore structure; then, depositing interconnection metal on the protective layer 107 in the metal interconnection open pore structure and outside the metal interconnection open pore structure by using an electron beam evaporation process, wherein the interconnection metal is a metal stack structure consisting of two layers of metal and sequentially comprises Ti and Au from bottom to top; finally, putting a sample subjected to interconnection metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove interconnection metal and photoresist outside an interconnection region, then putting the sample into an N-methyl-2-pyrrolidone (commonly called NMP) solution for ultrasonic removal of stripping glue, washing the sample with isopropanol and ultrapure water, and drying with nitrogen to form a metal interconnection layer 108, and leading out a source electrode 104, a drain electrode 105 and a grid electrode 107 from the metal interconnection layer 108; finally obtaining the nonpolar InAlN/GaN high electron mobility transistor with the grid direction parallel to the c axis.
The preparation method provided by the embodiment of the invention only depends on growth control of the in-situ material, avoids damage of processes such as etching and ion implantation to a material device, greatly improves the process repeatability and stability, ensures the performance and reliability of an enhancement device, and can realize large-scale preparation of the enhancement device.
EXAMPLE III
On the basis of the first and second embodiments, an included angle between a gate direction and a c-axis direction of the nonpolar InAlN/GaN high electron mobility transistor in the present embodiment is 45 °, please refer to fig. 4 and 5, fig. 4 is a schematic diagram of a structure of another nonpolar InAlN/GaN high electron mobility transistor provided in the embodiment of the present invention, and fig. 5 is a schematic diagram of a c-axis direction and a gate direction of another nonpolar InAlN/GaN high electron mobility transistor provided in the embodiment of the present invention.
The method comprises the following specific steps:
see example II for steps S1-S3;
s41, depositing a metal material on the nonpolar barrier layer 203 by using a metal evaporation method to form a source electrode 204 and a drain electrode 205;
first, a source electrode region and a drain electrode region are etched on the nonpolar barrier layer 203; then, ohmic metal is deposited on the nonpolar barrier layer 203 in the source electrode area and the drain electrode area and on the photoresist outside the source electrode area and the drain electrode area, wherein the ohmic metal is a metal stack structure consisting of four layers of metal, the four layers of metal are sequentially Ti, Al, Ni and Au from bottom to top, and the thicknesses of the four layers of metal are respectively Ti, Al, Ni and Au
Figure BDA0001953981230000161
Then, stripping the ohmic metal on the photoresist outside the source electrode area and the drain electrode area; finally, putting the sample subjected to ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment so as to enable ohmic metal on the nonpolar barrier layer 203 in the source electrode region and the drain electrode region to sink to the nonpolar channel layer 202, thereby forming ohmic contact between the ohmic metal and the heterojunction channel and forming a source electrode 204 and a drain electrode 205; wherein the annealing treatment process conditions in the rapid thermal annealing furnace are as follows: annealing atmosphere is N2The annealing temperature was 850 ℃ and the annealing time was 30 s.
Further, the angle between the center connecting line of the source 204 and drain 205 surfaces and the c-axis direction on the non-polar barrier layer 203 is 45 °, as shown in fig. 5.
S42, etching the non-polar barrier layer 203, the insertion layer 2021 and the non-polar channel layer 202 to form an isolation trench 2051, as shown in fig. 4;
photoetching an electric isolation area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, then washing the sample with ultrapure water and drying the sample with nitrogen, and baking the sample on a hot plate at 110 ℃ for 2 min; then, the non-polar barrier layer 203, the insertion layer 2021 and the non-polar GaN channel layer in the electrical isolation region are sequentially etched by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of the active region, wherein the total etching depth is 214 nm; finally, the sample is sequentially placed in an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation region, and the sample is rinsed with ultrapure water and dried with nitrogen to form an isolation trench 2051.
S43, depositing a metal material on the non-polar barrier layer 203 by a metal evaporation method to form a gate 206, wherein the direction of the gate 206 is along the connection line of the center points of the surfaces of the source 204 and the drain 205, i.e. the angle between the gate electrode direction and the c-axis direction is 45 °, as shown in fig. 5, the angle between the connection line of the center point a of the source 204 and the center point B of the drain 205 and the c-axis direction is 45 °, and the gate 206 is located on the connection line of a and B, so the included angle between the gate 208 and the c-axis is 45 °;
photoetching a gate electrode area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, controlling an included angle between the direction of a grid bar and the direction of a c axis of the surface of an epitaxial wafer to be 45 degrees, and carrying out ultrapure water washing and nitrogen blow-drying on a sample; then, a schottky metal is evaporated on the nonpolar barrier layer 203 in the gate electrode region and on the photoresist outside the gate electrode region as a gate electrode, wherein the schottky metal is a metal stack structure composed of two layers of metals, Ni and Au are sequentially arranged from bottom to top, and the thicknesses of Ni and Au are respectively
Figure BDA0001953981230000181
And finally, putting the sample subjected to gate metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove the Schottky metal and the photoresist outside the gate electrode, then putting the sample into an NMP solution for ultrasonic removal of the stripping glue, washing the sample with isopropanol and ultrapure water, and drying with nitrogen to form the gate 206.
Furthermore, the direction of the gate is determined by the relative orientation of the source and the drain, so that when the source and the drain are manufactured, the included angle between the connecting line of the drain and the source and the direction of the c axis is different, and because the gate is positioned between the drain and the source, the included angle between the direction of the gate and the direction of the c axis is different.
See example II for steps S5-S6. Finally, the nonpolar InAlN/GaN high electron mobility transistor with the gate direction and the c-axis direction forming an angle of 45 degrees is obtained, please refer to FIG. 4.
Example four
On the basis of the first and second embodiments, the gate direction of the non-polar InAlN/GaN high electron mobility transistor in the present embodiment is perpendicular to the c-axis direction, please refer to fig. 6 and 7, fig. 6 is a schematic structural view of another non-polar InAlN/GaN high electron mobility transistor provided in the present embodiment; fig. 7 is a schematic view of the c-axis direction and the gate direction of another nonpolar InAlN/GaN high electron mobility transistor according to an embodiment of the present invention.
The method comprises the following specific steps:
see example II for steps S1-S3;
s41, depositing a metal material on the non-polar barrier layer 303 by a metal evaporation method to form a source electrode 304 and a drain electrode 305;
first, a source electrode region and a drain electrode region are etched on the nonpolar barrier layer 303; then, ohmic metal is deposited on the nonpolar barrier layer 303 in the source electrode area and the drain electrode area and on the photoresist outside the source electrode area and the drain electrode area, wherein the ohmic metal is a metal stack structure consisting of four layers of metal, the four layers of metal are sequentially Ti, Al, Ni and Au from bottom to top, and the thicknesses of the four layers of metal are respectively Ti, Al, Ni and Au
Figure BDA0001953981230000191
Then, stripping the ohmic metal on the photoresist outside the source electrode area and the drain electrode area; finally, the sample subjected to ohmic metal evaporation and peeling is placed in a rapid thermal annealing furnace to be annealed, so that the ohmic metal on the nonpolar barrier layer 303 in the source electrode region and the drain electrode region sinks to the nonpolar channel layer 302, thereby forming ohmic contact between the ohmic metal and the heterojunction channel, and forming a source electrode 304 and a drain electrode 305. Wherein the annealing treatment process conditions in the rapid thermal annealing furnace are as follows: annealing atmosphere is N2The annealing temperature was 850 ℃ and the annealing time was 30 s.
Further, the center connecting line between the source 304 and the drain 305 is perpendicular to the c-axis direction of the non-polar barrier layer 303, as shown in fig. 7.
S42, etching the nonpolar barrier layer 303, the insertion layer 3021 and the nonpolar channel layer 302 to form an isolation trench 3051;
photoetching an electric isolation area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, then washing the sample with ultrapure water and drying the sample with nitrogen, and baking the sample on a hot plate at 110 ℃ for 2 min; then, the non-polar barrier layer 303, the insertion layer 3021 and the non-polar GaN channel layer in the electrical isolation region are sequentially etched by using an ICP process to realize mesa isolation of the active region, with a total etching depth of 214 nm; and finally, sequentially putting the sample into an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electric isolation region, then washing the sample with ultrapure water and drying with nitrogen to form the isolation trench 3051.
S43, depositing a metal material on the non-polar barrier layer 303 by a metal evaporation method to form a gate 306, wherein the direction of the gate 306 is along the center-point connecting line of the surfaces of the source 304 and the drain 305, i.e. the direction of the gate electrode is perpendicular to the c-axis direction, as shown in fig. 7, wherein the connecting line of the center point a of the source 304 and the center point B of the drain 305 is perpendicular to the c-axis direction, and the gate 306 is located on the connecting line of a and B, so the gate 308 is perpendicular to the c-axis;
photoetching a gate electrode area on the nonpolar InAlN barrier layer by adopting the processes of gluing, drying glue, exposing, developing and stripping, controlling the direction of a grid bar to be vertical to the c-axis direction of the surface of the epitaxial wafer, and washing a sample by ultrapure water and drying the sample by nitrogen; then, a schottky metal is evaporated on the nonpolar barrier layer 303 in the gate electrode region and on the photoresist outside the gate electrode region to serve as a gate, wherein the schottky metal is a metal stack structure composed of two layers of metals, Ni and Au are sequentially arranged from bottom to top, and the thicknesses of Ni and Au are respectively equal to that of Ni and Au
Figure BDA0001953981230000201
Finally, putting the sample subjected to gate metal evaporation into acetone for ultrasonic treatment, wherein the ultrasonic time is set to 10min to remove the Schottky metal and the photoresist outside the gate electrode, and then removing the Schottky metal and the photoresist outside the gate electrodeAnd putting the sample into an NMP solution to remove the stripping glue by ultrasonic, washing the sample by using isopropanol and ultrapure water, and drying by using nitrogen to form the grid 306.
Furthermore, the direction of the gate is determined by the relative orientation of the source and the drain, so that when the source and the drain are manufactured, the included angle between the connecting line of the drain and the source and the direction of the c axis is different, and because the gate is positioned between the drain and the source, the included angle between the direction of the gate and the direction of the c axis is different.
In steps S5 to S6, please refer to example two, and finally obtain the nonpolar InAlN/GaN high electron mobility transistor with the gate direction perpendicular to the c-axis direction, see fig. 6.
EXAMPLE five
Referring to fig. 2, the non-polar InAlN/GaN high electron mobility transistor with the gate direction parallel to the c-axis in fig. 2 includes:
a substrate 101; a non-polar channel layer 102 on the substrate 101; an insertion layer 1021 on the non-polar channel layer 102; a nonpolar barrier layer 103 on the insertion layer 1021; a source 104 within the non-polar channel layer 102 and the non-polar barrier layer 103; a drain 105 located within the non-polar channel layer 102 and the non-polar barrier layer 103; a gate 106 on the non-polar barrier layer 103, the gate 106 oriented parallel to the c-axis; a protective layer 107 covering the nonpolar barrier layer 103, the source electrode 104, the drain electrode 105, and the gate electrode 106; and a metal interconnection layer 108 on the source electrode 104, the drain electrode 105 and the gate electrode 106.
In the nonpolar InAlN/GaN high-electron-mobility transistor, the nonpolar channel layer and the nonpolar barrier layer form a nonpolar heterostructure, and the nonpolar heterostructure can modulate spontaneous polarization and piezoelectric polarization, so that the generation of high-density polarization charges in the channel is inhibited, and an enhancement effect is realized.
The transport rate of the current carrier in the nonpolar InAlN/GaN high electron mobility transistor along the c-axis direction is higher than that of the current carrier in the polar InAlN/GaN high electron mobility transistor, the device performance is better, and the enhancement effect is better.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A preparation method of a nonpolar InAlN/GaN high electron mobility transistor is characterized by comprising the following steps:
s1, selecting a nonpolar GaN material as a substrate (101); nitriding the substrate (101) at a temperature ranging from 828 to 1012 ℃; -treating said substrate (101) by means of a thermal decomposition-regrowth technique, in the following steps: growing a GaN film on a substrate (101), performing etching treatment on the GaN film, and circulating a preset period to grow the GaN film and perform etching treatment on the GaN film;
s2, growing GaN on the substrate (101) to form a non-polar channel layer (102); the conditions for forming the non-polar channel layer (102) are: the temperature range of the base is 900-1100 ℃, the pressure range of the reaction chamber is 9-10 Torr, the flow range of the Ga source is 9-11 sccm, and the flow range of the N source is 90-110 sccm;
s3, growing InAlN on the nonpolar channel layer (102) to form a nonpolar barrier layer (103); the conditions for forming the nonpolar barrier layer (103) are: the temperature range of the base is 648-792 ℃, the pressure range of the reaction chamber is 180-220 Torr, the flow range of the Al source is 10-14 sccm, the flow range of the N source is 900-1100 sccm, and the flow range of the In source is 72-88 sccm;
s4, manufacturing a source electrode (104) and a drain electrode (105) in the nonpolar channel layer (102) and the nonpolar barrier layer (103), and manufacturing a grid electrode (106) on the nonpolar barrier layer (103) to obtain the nonpolar InAlN/GaN high electron mobility transistor.
2. The method of claim 1, wherein step S3 includes:
s31, growing AlN on the nonpolar channel layer (102) to form an insertion layer (1021);
s32, InAlN is grown on the insertion layer (1021), and the nonpolar barrier layer (103) is formed.
3. The method of claim 1, wherein the nonpolar InAlN/GaN high electron mobility transistor is formed from a nonpolar barrier layer (103) of In1-xAlxN, wherein x ranges from 80% to 85%.
4. The method of claim 1, wherein step S4 includes:
s41, depositing a first metal material on the nonpolar barrier layer (103) by using a metal evaporation method, and annealing the first metal material to enable the first metal material to sink to the nonpolar channel layer (102) so as to form a source electrode (104) and a drain electrode (105);
s42, etching the nonpolar barrier layer (103) and the nonpolar channel layer (102) to form an isolation trench (1051);
and S43, depositing a second metal material on the nonpolar barrier layer (103) by using a metal evaporation method to form a grid electrode (106).
5. The method of claim 1, wherein fabricating a source (104) and a drain (105) within the non-polar channel layer (102) and the non-polar barrier layer (103), and further comprising, after fabricating a gate (106) on the non-polar barrier layer (103):
s5, depositing SiN on the nonpolar barrier layer (103), the source electrode (104), the drain electrode (105) and the grid electrode (106) by utilizing a plasma enhanced chemical vapor deposition method to form a protective layer (107);
s6, photoetching an interconnection opening area on the protective layer (107), and manufacturing a metal interconnection layer (108) in the interconnection opening area.
6. A non-polar InAlN/GaN high electron mobility transistor made by the method of any of claims 1-5.
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