CN111106169A - Transistor device and preparation method thereof - Google Patents
Transistor device and preparation method thereof Download PDFInfo
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- CN111106169A CN111106169A CN201911185651.1A CN201911185651A CN111106169A CN 111106169 A CN111106169 A CN 111106169A CN 201911185651 A CN201911185651 A CN 201911185651A CN 111106169 A CN111106169 A CN 111106169A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The embodiment of the application provides a transistor device and a preparation method thereof. And a gate groove penetrating through the gate dielectric layer is prepared on the gate dielectric layer, wherein the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps. Therefore, the slope-shaped grid groove with multiple steps can avoid sudden change of the electric field at the grid groove, slow down the change amplitude of the electric field, improve the spike effect of the electric field and further improve the reliability of the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a micro transistor device and a preparation method thereof.
Background
The third generation semiconductor material GaN has large forbidden bandwidth (3.4eV) and high electron saturation velocity (2 × 10)7cm/s) and high breakdown electric field (1X 10)10～3×1010V/cm), higher thermal conductivity, corrosion resistance, radiation resistance and the like become current research hotspots, and the method has wide application prospect. In particular, High Electron Mobility Transistors (HEMTs) having an AlGaN/GaN heterojunction structure have the advantages of High frequency, High power density, High operating temperature, and the like, have shown great advantages in High-temperature devices and High-power microwave devices, and have attracted much research in pursuing High frequency, High voltage, High power, and the like of the devices.
The stability and reliability of the device are decisive factors for determining whether the device can be put into practical use on a large scale. At present, although GaN-based HEMT power device products are sold, the stability and reliability research of the GaN-based HEMT devices is still in the initial stage, and the research is a current international research hotspot, and a complete and scientific test and evaluation system is not established. When the AlGaN/GaN HEMT device works, the AlGaN/GaN HEMT device can be repeatedly impacted by a strong electric field and a large current, and the performance of the device can be influenced by a higher junction temperature and a working environment during high-temperature application. The degradation mechanism of the GaN-based HEMT device under electrical stress and high temperature is a very important issue.
It is currently found that there is a current collapse phenomenon in AlGaN/GaN HEMT devices, which is currently the most prominent problem affecting the stability and practicality of GaN-based HEMT devices. Such a current collapse phenomenon may cause a decrease in output current of the device, an increase in on-resistance, and a decrease in output power, thereby causing deterioration in performance of the device. Although much research is currently being conducted on similar electrical degradation phenomena, numerous degradation mechanisms have been proposed. However, the degradation phenomenon of the electrical characteristics of the device has multiple manifestations, and so far, there is no complete theory to explain all the degradation phenomena simultaneously. The gate electrode process has become the most complex and most core process for manufacturing the high-performance GaN-based HEMT, and the process quality directly influences the performance of the device in the aspects of power, gain, efficiency, stability, reliability and the like. Analysis and statistics of the electrical characteristic degradation cause of the device find that the degradation factor of the gate electrode accounts for the largest proportion, typically, the gate leakage is increased, the substrate at the edge of the gate groove is degraded, and gate metal is diffused to the substrate.
Disclosure of Invention
In order to overcome at least the above disadvantages in the prior art, embodiments of the present application provide a transistor device and a method for manufacturing the same.
In a first aspect, an embodiment of the present invention provides a transistor device, including:
a substrate;
manufacturing an epitaxial layer based on the substrate;
manufacturing a formed gate dielectric layer on one side of the epitaxial layer far away from the substrate;
the gate dielectric layer is provided with a gate groove penetrating through the gate dielectric layer, the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps.
In an alternative embodiment, the transistor device further comprises:
the gate electrode is filled in the gate groove and is in contact with the epitaxial layer;
and the source electrode and the drain electrode penetrate through the gate dielectric layer and are in contact with the epitaxial layer, and the source electrode and the drain electrode are respectively positioned on two sides of the gate electrode.
In an alternative embodiment, the gate recess has a sidewall that is sloped at an angle of 25 degrees to 75 degrees.
In an alternative embodiment, the gate dielectric layer is a single dielectric layer comprising a dielectric material of the same density.
In an alternative embodiment, the gate electrode comprises:
gate metal filled in the gate groove;
a passivation dielectric layer formed on the gate dielectric layer except the gate metal;
and the grid field plate is formed on the grid metal and the passivation dielectric layer and is electrically connected with the grid metal.
In an optional embodiment, interconnection metals are respectively formed on the gate electrode, the source electrode and the drain electrode to lead out the gate electrode, the source electrode and the drain electrode.
In an optional embodiment, the width of the opening of the gate groove away from the epitaxial layer is 0.1um to 1.0 um.
In a second aspect, an embodiment of the present application provides a method for manufacturing a transistor device, where the method includes:
providing a substrate;
forming an epitaxial layer based on the substrate manufacture;
forming a gate dielectric layer on one side of the epitaxial layer far away from the substrate;
and preparing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer, wherein the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps.
In an alternative embodiment, the method further comprises:
preparing a source electrode and a drain electrode which penetrate through the gate dielectric layer and are in contact with the epitaxial layer on the basis of the gate dielectric layer;
and filling the gate groove to prepare a gate electrode, wherein the gate electrode is in contact with the epitaxial layer and is positioned between the source electrode and the drain electrode.
In an optional embodiment, the step of preparing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer includes:
forming a photoresist layer on the surface of the gate dielectric layer through a photoetching process, and exposing and developing the photoresist layer to form a photoresist layer groove penetrating through the photoresist layer;
partially etching the gate dielectric layer based on the region of the gate dielectric layer corresponding to the glue layer groove;
ashing the photoresist layer by using a plasma treatment process to widen the groove of the photoresist layer;
etching the area corresponding to the widened glue layer groove on the basis of the gate dielectric layer to form a gate groove with a step-shaped side wall, stopping processing if the gate groove penetrates through the gate dielectric layer, repeatedly performing ashing processing on the photoresist layer by using a plasma processing technology to widen the glue layer groove if the gate groove does not penetrate through the gate dielectric layer, and etching the area corresponding to the widened glue layer groove on the basis of the gate dielectric layer until the formed gate groove penetrates through the gate dielectric layer.
In an optional embodiment, the width of the opening of the gate groove far away from the epitaxial layer is adjusted by controlling the intensity and the treatment duration of the plasma treatment process, wherein the width of the opening is 0.1um to 1.0 um.
In an optional embodiment, the step of preparing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer includes:
and etching the gate dielectric layer under the condition of an atmosphere containing oxygen to form a gate groove penetrating through the gate dielectric layer, and adjusting the inclination angle of the side wall of the gate groove by controlling the content of the oxygen, wherein the inclination angle of the side wall of the gate groove is 25-75 degrees.
In an alternative embodiment, the step of filling in the gate groove to prepare a gate electrode includes:
filling gate metal in the gate groove;
manufacturing and forming a passivation dielectric layer in the region of the gate dielectric layer except the gate metal;
and manufacturing and forming a gate field plate on the gate metal and the passivation dielectric layer to form a gate electrode, wherein the gate field plate is electrically connected with the gate metal.
Compared with the prior art, the method has the following beneficial effects:
the transistor device and the manufacturing method thereof provided by the embodiment of the application comprise an epitaxial layer manufactured on a substrate and a gate dielectric layer manufactured on the epitaxial layer. And a gate groove penetrating through the gate dielectric layer is prepared on the gate dielectric layer, wherein the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps. Therefore, the slope-shaped grid groove with multiple steps can avoid sudden change of the electric field at the grid groove, slow down the change amplitude of the electric field, improve the spike effect of the electric field and further improve the reliability of the device.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of a transistor device provided in an embodiment of the present application;
fig. 2 is another block diagram of a transistor device provided in an embodiment of the present application;
fig. 3 is another block diagram of a transistor device provided in an embodiment of the present application;
fig. 4 is a flow chart of a method for fabricating a transistor device according to an embodiment of the present disclosure;
fig. 5-10 are structural diagrams of devices formed at various steps in a method for fabricating a transistor device according to an embodiment of the present application;
fig. 11 is a schematic diagram of an electric field spike at the edge of a gate recess for a prior art transistor device;
fig. 12 is a schematic diagram of an electric field spike at an edge of a gate recess of a crystal optical device according to an embodiment of the present application.
Icon: 10-a substrate; 20-an epitaxial layer; 30-a gate dielectric layer; 31-a gate recess; 41-a gate electrode; 42-a source electrode; 43-a drain electrode; 50-a photoresist layer; 51-glue line groove.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, embodiments of the present application provide a transistor device including a substrate 10, where the substrate 10 may be a SiC substrate 10, a Si substrate 10, a sapphire substrate 10, a GaN substrate 10, or any other substrate 10 suitable for epitaxial growth of GaN material known to those skilled in the art, and the present application is not limited thereto.
The transistor device further comprises an epitaxial layer 20 formed on the substrate 10, wherein the epitaxial layer 20 can be any one of GaN, Si, GaAs, SiGe and SiC. A gate dielectric layer 30 is formed on the side of the epitaxial layer 20 away from the substrate 10, and the gate dielectric layer 30 may be made of SiN or SiO2、AlN、Al2O3And the like. In this embodiment, the Plasma Enhanced Chemical Vapor Deposition (PECVD), the Low Pressure Chemical Vapor Deposition (LPCVD), the inductively coupled Enhanced cvd (LPCVD), and the Plasma Enhanced cvd (LPCVD) can be usedA gate dielectric layer 30 is deposited on the epitaxial layer 20 by any one of plasma deposition (ICP-PECVD) methods.
In this embodiment, the gate dielectric layer 30 may be a single dielectric layer containing a dielectric material with the same compactness, so that the process for forming the gate dielectric layer 30 by deposition may be simplified. The problem of complex process in the prior art that a plurality of dielectric layers are formed by using different density materials to prepare the gate groove 31 is solved.
A gate groove 31 penetrating through the gate dielectric layer 30 is formed on the gate dielectric layer, wherein the width of the opening of the gate groove 31 far away from the epitaxial layer 20 is greater than the width of the opening near the epitaxial layer 20. Thus, the sidewalls of the gate recess 31 have a certain inclination angle. In this embodiment, the width of the opening of the gate recess 31 away from the epitaxial layer 20 may be 0.1um to 1.0 um. The width of the opening of the gate recess 31 away from the epitaxial layer 20 can be adjusted accordingly by controlling parameters in the fabrication process.
If the inclination angle of the sidewall of the gate recess 31 is too large, the coverage of the subsequent gate metal is not favorable, and the peak electric field at the edge of the gate recess 31 is still significant when the device works, which affects the reliability of the device. If the tilt angle is too small, the parasitic capacitance is large, and the device performance is also affected.
Based on the above research, in the present embodiment, the inclination angle of the sidewall of the gate groove 31 may be between 25 degrees and 75 degrees.
In addition, in the present embodiment, the inner sidewall of the gate groove 31 is stepped to include at least two steps. For example, the grating groove 31 may include two steps as shown in fig. 1, and may also include three grating grooves 31 as shown in fig. 2. Thus, the gate recess 31 extends from the opening near the epitaxial layer 20 to the upper portion slowly through the sidewall having a slope and including at least two steps.
Through the design of the above-mentioned structure to grid recess 31, compare current vertical sidewall and only the grid recess 31 structure of one change step, the change of electric field in grid recess 31 department can be decomposed into many times to play the purpose of alleviating the range of change of electric field, avoid appearing the sudden change at grid recess 31 edge, and cause the electric field spike effect, and then influence the problem of device performance.
Referring to fig. 3, in the present embodiment, the transistor device further includes a gate electrode 41 filled in the gate recess 31 and contacting the epitaxial layer 20. Gate electrode 41 forms a schottky contact with epitaxial layer 20 and can be used to control device channel current. The transistor device further comprises a source electrode 42 and a drain electrode 43 penetrating the gate dielectric layer 30 and contacting the epitaxial layer 20, the source electrode 42 and the drain electrode 43 being located on both sides of the gate electrode 41, respectively. The source electrode 42 and the drain electrode 43 form ohmic contacts with the epitaxial layer 20, respectively.
In this embodiment, the gate electrode 41 includes a gate metal filled in the gate groove 31, a passivation dielectric layer formed on the gate dielectric layer 30 except for the gate metal, and a gate field plate electrically connected to the gate metal and formed on the gate metal and the passivation dielectric layer.
The gate field plate structure can greatly improve the breakdown voltage of the device, inhibit current collapse to a certain extent, and improve the power density and power added efficiency of the device, thereby improving the linearity and microwave power characteristics of the device.
In this embodiment, interconnection metals are formed on the gate electrode 41, the source electrode 42 and the drain electrode 43, respectively, so as to lead out the gate electrode 41, the source electrode 42 and the drain electrode 43 for facilitating the subsequent power-on.
According to the transistor device provided by the embodiment of the application, the gate groove 31 is formed in the single dielectric layer containing the dielectric materials with the same density, the gate groove 31 is in a step shape with a certain gradient and the side wall of the step shape comprises at least two steps, and the gate electric field distribution of the device during working is optimized through the structure of the gate groove 31 with multiple steps, so that the electric field spike effect at the bottom edge of the gate groove 31 is improved, and the reliability of the device is improved.
Referring to fig. 4, embodiments of the present application further provide a method for manufacturing a transistor device, which can be used for manufacturing the transistor device, and the detailed process of the method will be described below.
In step S110, please refer to fig. 5, a substrate 10 is provided. The substrate 10 may be a SiC substrate 10, a Si substrate 10, a sapphire substrate 10, a GaN substrate 10, or the like.
Step S120, forming an epitaxial layer 20 on the basis of the substrate 10. The epitaxial layer 20 may be any of GaN, AlGaN, Si, GaAs, SiGe, SiC.
Step S130, forming a gate dielectric layer 30 on the side of the epitaxial layer 20 away from the substrate 10.
The gate dielectric layer 30 may be deposited on the epitaxial layer 20 by any one of PECVD, LPCVD, and ICP-PECVD.
In this embodiment, SiH may be included4、NH4、N2And depositing the gate dielectric layer 30 under the atmospheric condition of the equal gas. For example, SiH can be at 2sccm to 50sccm by PECVD42sccm-50sccm NH40sccm to 1000sccm of N2And depositing the SiN gate dielectric layer 30 under the conditions of power of 10w-600w and gas pressure of 100mTorr-2000mTorr under the same gas. The SiN gate dielectric layer 30 may be formed to a thickness of 200A-2000A with a refractive index of 1.9-2.1.
Step S140, please refer to fig. 6 to fig. 10 in combination, a gate recess 31 penetrating through the gate dielectric layer 30 is formed on the gate dielectric layer 30, wherein a width of an opening of the gate recess 31 away from the epitaxial layer 20 is greater than a width of an opening close to the epitaxial layer 20, and an inner sidewall of the gate recess 31 is stepped and includes at least two steps.
In this embodiment, the gate recess 31 may be formed on the gate dielectric layer 30 by photolithography, development and etching. Alternatively, referring to fig. 6, a photoresist layer 50 may be formed on the surface of the gate dielectric layer 30 through a photolithography process, and the photoresist layer 50 is exposed and developed to form a photoresist layer groove 51 penetrating through the photoresist layer 50. I.e., a portion of the gate dielectric layer 30 is exposed through the glue line recess 51. The width of the glue layer groove 51 can be set according to the required width of the gate groove 31.
Referring to fig. 7, the gate dielectric layer 30 is partially etched based on the region of the gate dielectric layer 30 corresponding to the glue line groove 51. That is, when the gate dielectric layer 30 is etched for the first time, the etching thickness of the gate dielectric layer 30 may be a part of the total thickness of the gate dielectric layer 30, and does not penetrate through the gate dielectric layer 30.
In order to form the multi-step gate recess 31 in the gate dielectric layer 30, the photoresist layer 50 may be subjected to an ashing process using a plasma treatment process to widen the above-mentioned photoresist layer recess 51, as shown in fig. 8. Namely, on the basis of the above, a part of the gate dielectric layer 30 is exposed.
Etching is performed on the basis of the area of the gate dielectric layer 30 corresponding to the widened glue layer groove 51 to form a gate groove 31 with a stepped inner side wall, as shown in fig. 9. It should be understood that, when the gate dielectric layer 30 is etched this time, the groove formed by the last etching and the newly exposed partial region are etched at the same time, the groove formed by the last etching is further deepened, and the newly exposed partial region is also etched by a certain depth, so that the groove formed by the last etching and the newly exposed partial region are stepped after being etched.
In this embodiment, the process parameters may be set according to actual requirements, so as to control the number of steps formed and the inclination of the sidewalls formed.
If the formed gate groove 31 penetrates through the gate dielectric layer 30, stopping the processing, and if the formed gate groove 31 does not penetrate through the gate dielectric layer 30, repeatedly performing ashing processing on the photoresist layer 50 by using a plasma processing process to widen the glue layer groove 51, and etching the glue layer groove 51 corresponding to the widened glue layer based on the gate dielectric layer 30 until the formed gate groove 31 penetrates through the gate dielectric layer 30. For example, as shown in fig. 10, a gate recess 31 is formed through the gate dielectric layer 30 including three steps.
In practice, it should be noted that the photoresist layer 50 is subjected to ashing treatment, and the total thickness of the photoresist layer 50 should be less than the thickness of the photoresist layer 50 to avoid exposing the entire surface of the gate dielectric layer 30.
When the gate dielectric layer 30 is etched, the gate dielectric layer 30 may be etched under an atmosphere containing oxygen to form the gate groove 31 penetrating through the gate dielectric layer 30, and in the process, an inclination angle of a sidewall of the gate groove 31 may be adjusted by controlling the content of oxygen, wherein in this embodiment, the inclination angle of the sidewall of the formed gate groove 31 is 25 degrees to 75 degrees.
When the photoresist layer 50 is subjected to ashing treatment by plasma treatment process to remove a portion of the photoresist, the width of the upper opening of the gate groove 31 can be adjusted by controlling the intensity and treatment duration of the plasma treatment process, wherein in the present embodiment, the width of the upper opening of the gate groove 31 can be 0.1um to 1.0 um.
In this embodiment, the inclination angle of the gate groove 31 can be adjusted by the content of oxygen during the etching process, and the width of the gate groove 31 can be adjusted by controlling the plasma processing intensity and the processing duration, so that the inclination angle and the width of the gate groove 31 can be flexibly adjusted, and the corresponding adjustment can be performed according to actual requirements.
The process of forming the gate recess 31 will be described below by taking the formation of the gate recess 31 including three steps as an example. It should be noted that the parameters in the process are only examples, and specific values may be set according to actual situations, and this embodiment is not particularly limited.
First, a photoresist layer 50 is coated on the gate dielectric layer 30, and is exposed and developed to form a photoresist layer groove 51, exposing a portion of the gate dielectric layer 30.
CF at 5sccm to 100sccm by Inductively Coupled Plasma etching (ICP)4CHF of 5sccm to 100sccm35sccm-100sccm of O25sccm to 100sccm of N2And etching the gate dielectric layer 30 to form a groove structure under the conditions of power of 20w-500w and gas pressure of 100mTorr-1000mTorr under the gas, wherein the etching depth can be 200A.
The photoresist layer 50 is subjected to ashing treatment using oxygen plasma treatment to remove a certain amount of photoresist, thereby widening the formed photoresist layer groove 51. The amount of photoresist removed can be determined by the step length required by the process. O can be introduced by ICP at 5sccm to 100sccm20sccm to 100sccm of N2Under the gas condition, under the conditions of power of 20w-500w and gas pressure of 100mTorr-1000mTorr, the oxygen plasma is used for processing the ashing photoresist layer 50, and the etching amount of the photoresist can be 200A.
Using 5sccm to 100sccm CF by ICP4CHF of 5sccm to 100sccm3、5sccm-100sccmO2、5sccm-100sccmN2Under the condition of equal gas, the gate dielectric layer 30 is etched under the conditions of power of 20w-500w and gas pressure of 100mTorr-1000mTorr to form a gate groove 31 comprising two steps, and the etching depth of the gate dielectric layer 30 can be 200A.
Then, an oxygen plasma treatment is performed to remove a certain amount of the photoresist layer 50, and 5sccm-100sccmO is used by ICP2、0sccm-100sccm N2Under the condition of equal gas and the power of 20w-500w and the gas pressure of 100mTorr-1000mTorr, oxygen plasma treatment is carried out to remove part of the photoresist, and the glue layer groove 51 is further widened.
Using 5sccm to 100sccm CF by ICP4、5sccm-100sccm CHF3、5sccm-100sccm O2、5sccm-100sccm N2Under the condition of equal gas, under the conditions of power of 20w-500w and gas pressure of 100mTorr-1000mTorr, etching is carried out on the gate dielectric layer 30 corresponding to the widened glue layer groove 51 to form a gate groove 31 comprising three steps, and the gate groove 31 penetrates through the whole gate dielectric layer 30.
After the gate recess 31 including the multi-step is formed through the above process, the residual photoresist after etching may be removed by using an organic solvent, such as N-methyl pyrrolidone, at 70 ℃ under 1000PSI pressure, so as to form the device with the three-step gate recess 31 structure as shown in fig. 2.
Referring to fig. 3 again, the preparation method provided in this embodiment further includes manufacturing a gate electrode 41, a source electrode 42, and a drain electrode 43, and the source electrode 42 and the drain electrode 43 penetrating through the gate dielectric layer 30 and contacting the epitaxial layer 20 are prepared based on the gate dielectric layer 30, and the gate electrode 41 is filled in the gate recess 31, wherein the gate electrode 41 contacts the epitaxial layer 20 and is located between the source electrode 42 and the drain electrode 43.
In this embodiment, the isolation may be performed by an ion implantation process in a region outside the active region on the surface of the gate dielectric layer 30, wherein the active region includes a gate region, a source region and a drain region. The gate dielectric layer 30 is etched to cut off to the epitaxial layer 20 based on the source and drain regions. In the through-holes formed by etching, metal Ti/Al/Ni/Au is evaporated on the basis of the surface of the epitaxial layer 20, and ohmic contacts are formed under high temperature conditions to fabricate and form the source electrode 42 and the drain electrode 43.
When the gate electrode 41 is fabricated, the gate groove 31 may be filled with gate metal, a passivation dielectric layer is fabricated on a region of the gate dielectric layer 30 except for the gate metal, and a gate field plate is fabricated on the gate metal and the passivation dielectric layer to form the gate electrode 41. Wherein the gate field plate is electrically connected to the gate metal.
The breakdown voltage of the device can be greatly improved through the grid field plate structure, the current collapse can be restrained to a certain degree, the power density and the power additional efficiency of the device are improved, and therefore the linearity and the microwave power characteristic of the device are improved.
On the basis, interconnection metals can be respectively manufactured and formed on the gate electrode 41, the source electrode 42 and the drain electrode 43, so that the gate electrode 41, the source electrode 42 and the drain electrode 43 can be led out, and the power supply can be conveniently switched on subsequently.
In the transistor device manufactured by the manufacturing method provided by the embodiment, the gate groove 31 is a step shape having a certain inclination and comprising a plurality of steps, and compared with the gate groove 31 having a single step and a vertical sidewall adopted in the prior art, the abrupt change phenomenon of an electric field at the edge of the gate groove 31 can be effectively alleviated, and the spike effect of the electric field can be alleviated. Fig. 11 and 12 respectively show an electric field spike effect schematic diagram of the edge of the gate groove 31 structure of the device with the gate groove 31 structure in the prior art, and the edge condition of the gate groove 31 of the device formed by the embodiment. It can be seen that the device formed by the present embodiment effectively alleviates the electric field spike effect at the edge of the gate recess 31.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
In summary, the transistor device and the method for manufacturing the same provided by the embodiment of the present application include an epitaxial layer 20 formed on a substrate 10, and a gate dielectric layer 30 formed on the epitaxial layer 20. A gate groove 31 penetrating through the gate dielectric layer 30 is prepared, wherein the width of the opening of the gate groove 31 far away from the epitaxial layer 20 is larger than the width of the opening near the epitaxial layer 20, and the inner side wall of the gate groove 31 is in a step shape including at least two steps. Therefore, the slope-shaped gate groove 31 with multiple steps can avoid sudden change of the electric field at the gate groove 31, slow down the variation range of the electric field, improve the spike effect of the electric field and further improve the reliability of the device.
The above description is only for various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and all such changes or substitutions are included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A transistor device, comprising:
a substrate;
manufacturing an epitaxial layer based on the substrate;
manufacturing a formed gate dielectric layer on one side of the epitaxial layer far away from the substrate;
the gate dielectric layer is provided with a gate groove penetrating through the gate dielectric layer, the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps.
2. The transistor device of claim 1, further comprising:
the gate electrode is filled in the gate groove and is in contact with the epitaxial layer;
and the source electrode and the drain electrode penetrate through the gate dielectric layer and are in contact with the epitaxial layer, and the source electrode and the drain electrode are respectively positioned on two sides of the gate electrode.
3. The transistor device of claim 1, wherein the gate recess has a sidewall that is sloped at an angle of 25 degrees to 75 degrees.
4. The transistor device of claim 1, wherein the gate dielectric layer is a single dielectric layer comprising a dielectric material of the same densification.
5. The transistor device of claim 2, wherein the gate electrode comprises:
gate metal filled in the gate groove;
a passivation dielectric layer formed on the gate dielectric layer except the gate metal;
and the grid field plate is formed on the grid metal and the passivation dielectric layer and is electrically connected with the grid metal.
6. The transistor device of claim 1, wherein the width of the opening of the gate recess away from the epitaxial layer is 0.1um-1.0 um.
7. A method of fabricating a transistor device, the method comprising:
providing a substrate;
forming an epitaxial layer based on the substrate manufacture;
forming a gate dielectric layer on one side of the epitaxial layer far away from the substrate;
and preparing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer, wherein the width of the opening of the gate groove far away from the epitaxial layer is larger than that of the opening close to the epitaxial layer, and the inner side wall of the gate groove is in a step shape comprising at least two steps.
8. The transistor device fabrication method of claim 7, further comprising:
preparing a source electrode and a drain electrode which penetrate through the gate dielectric layer and are in contact with the epitaxial layer on the basis of the gate dielectric layer;
and filling the gate groove to prepare a gate electrode, wherein the gate electrode is in contact with the epitaxial layer and is positioned between the source electrode and the drain electrode.
9. The method for manufacturing a transistor device according to claim 7, wherein the step of manufacturing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer comprises:
forming a photoresist layer on the surface of the gate dielectric layer through a photoetching process, and exposing and developing the photoresist layer to form a photoresist layer groove penetrating through the photoresist layer;
partially etching the gate dielectric layer based on the region of the gate dielectric layer corresponding to the glue layer groove;
ashing the photoresist layer by using a plasma treatment process to widen the groove of the photoresist layer;
etching the area corresponding to the widened glue layer groove on the basis of the gate dielectric layer to form a gate groove with a step-shaped side wall, stopping processing if the gate groove penetrates through the gate dielectric layer, repeatedly performing ashing processing on the photoresist layer by using a plasma processing technology to widen the glue layer groove if the gate groove does not penetrate through the gate dielectric layer, and etching the area corresponding to the widened glue layer groove on the basis of the gate dielectric layer until the formed gate groove penetrates through the gate dielectric layer.
10. The method of claim 9, wherein the width of the opening of the gate trench away from the epitaxial layer is adjusted by controlling the intensity and duration of the plasma treatment process, wherein the width of the opening is between 0.1um and 1.0 um.
11. The method for manufacturing a transistor device according to claim 7, wherein the step of manufacturing a gate groove penetrating through the gate dielectric layer on the gate dielectric layer comprises:
and etching the gate dielectric layer under the condition of an atmosphere containing oxygen to form a gate groove penetrating through the gate dielectric layer, and adjusting the inclination angle of the side wall of the gate groove by controlling the content of the oxygen, wherein the inclination angle of the side wall of the gate groove is 25-75 degrees.
12. The method for manufacturing a transistor device according to claim 8, wherein the step of filling in the gate recess to manufacture a gate electrode comprises:
filling gate metal in the gate groove;
manufacturing and forming a passivation dielectric layer in the region of the gate dielectric layer except the gate metal;
and manufacturing and forming a gate field plate on the gate metal and the passivation dielectric layer to form a gate electrode, wherein the gate field plate is electrically connected with the gate metal.
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