TWI818709B - Phase change memory structure and manufacturing method thereof - Google Patents

Abstract

A phase change memory structure including a substrate, a first dielectric layer, and phase change memory cells is provided. The first dielectric layer is disposed on the substrate. Each of the phase change memory cells includes a first electrode, a heater layer, a phase change layer, and a second electrode. The first electrode is disposed in the first dielectric layer. The heater layer is disposed on the first electrode. The phase change layer is disposed on the heater layer. The second electrode is disposed on the phase change layer. There is an air gap between two adjacent phase change memory cells. The air gap is located between two adjacent heater layers and between two adjacent phase change layers.

Description

Phase change memory structure and manufacturing method thereof

The present invention relates to a memory structure and a manufacturing method thereof, and in particular to a phase change memory (PCM) structure and a manufacturing method thereof.

Phase change memory is a non-volatile memory. Phase change memory is a memory element that utilizes the conductivity difference displayed by phase change materials when they transition between crystalline and amorphous phases to store data. For example, phase change materials have relatively high resistance in the amorphous phase state, and phase change materials have relatively low resistance in the crystalline phase state. In addition, phase change memory operates by heating. However, when heating phase change materials, if heat energy is easily dissipated, greater operating power (such as RESET power) is required to operate the selected phase change memory cells, and the dissipated heat energy will Causes thermal disturbance to adjacent phase change memory cells. Therefore, how to reduce the operating power (eg, reset power) of the phase change memory and prevent thermal interference between adjacent phase change memory cells is the goal of ongoing efforts.

The present invention provides a phase change memory structure that can effectively reduce operating power (eg, reset power) and prevent thermal interference between phase change memory cells.

The present invention proposes a phase change memory structure, which includes a substrate, a first dielectric layer and a plurality of phase change memory cells. A first dielectric layer is disposed on the substrate. Each phase change memory cell includes a first electrode, a heater layer, a phase change layer and a second electrode. The first electrode is disposed in the first dielectric layer. The heating layer is disposed on the first electrode. The phase change layer is provided on the heating layer. The second electrode is provided on the phase change layer. There is an air gap between two adjacent phase change memory cells. The air gap is located between two adjacent heating layers and between two adjacent phase change layers.

According to an embodiment of the present invention, in the above phase change memory structure, the air gap may be further located between two adjacent second electrodes.

According to an embodiment of the invention, in the above phase change memory structure, the side walls of the second electrode, the side walls of the phase change layer and the side walls of the heating layer may be aligned with each other.

According to an embodiment of the present invention, the phase change memory structure may further include a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the air gap and the phase change layer, between the air gap and the heating layer, and between the air gap and the first dielectric layer. The third dielectric layer is disposed above the air gap and connected to the second dielectric layer.

According to an embodiment of the invention, in the above phase change memory structure, the second dielectric layer can be conformally disposed on the sidewalls of the phase change layer, the sidewalls of the heating layer and the top surface of the first dielectric layer. .

According to an embodiment of the invention, in the above phase change memory structure, the second dielectric layer and the third dielectric layer may surround the air gap.

According to an embodiment of the present invention, in the above phase change memory structure, the third dielectric layer can be further disposed on the second electrode.

The invention proposes a method for manufacturing a phase change memory structure, which includes the following steps. Provide a base. A first dielectric layer is formed on the substrate. Multiple phase change memory cells are formed. Each phase change memory cell includes a first electrode, a heating layer, a phase change layer and a second electrode. The first electrode is disposed in the first dielectric layer. The heating layer is disposed on the first electrode. The phase change layer is provided on the heating layer. The second electrode is provided on the phase change layer. An air gap is formed between two adjacent phase change memory cells. The air gap is located between two adjacent heating layers and between two adjacent phase change layers.

According to an embodiment of the present invention, in the above method for manufacturing a phase change memory structure, openings may be provided on both sides of the phase change memory cell. The method of forming the air gap may include the following steps. A second dielectric layer is conformally formed on the first dielectric layer, the heating layer, the phase change layer and the second electrode. A third dielectric layer filling the opening is formed on the second dielectric layer. Using the second dielectric layer as a termination layer, a planarization process is performed on the third dielectric layer. A fourth dielectric layer is formed on the second dielectric layer and the third dielectric layer. The third dielectric layer is removed to form an air gap.

According to an embodiment of the present invention, the method for manufacturing the phase change memory structure may further include the following steps. After performing a planarization process on the third dielectric layer, a portion of the third dielectric layer is removed to reduce the height of the third dielectric layer. During the process of removing a portion of the third dielectric layer, a portion of the second dielectric layer located on the second electrode is also removed.

Based on the above, in the phase change memory structure and its manufacturing method proposed by the present invention, there is an air gap between two adjacent phase change memory cells, and the air gap is between two adjacent heating layers and the phase change memory cell. between two adjacent phase change layers. Since the air gap has poor thermal conductivity, when operating a selected phase change memory cell, the air gap between two adjacent heating layers and between two adjacent phase change layers can be used to prevent heat energy from dissipating. , thus effectively reducing operating power (such as reset power) and preventing thermal interference between phase change memory cells.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Examples are listed below and described in detail with reference to the drawings. However, the provided examples are not intended to limit the scope of the present invention. To facilitate understanding, the same components will be identified with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to original size. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A to 1J are cross-sectional views of the manufacturing process of a phase change memory structure and a manufacturing method thereof according to some embodiments of the present invention.

Referring to Figure 1A, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate (eg, silicon substrate), a compound semiconductor substrate (eg, gallium arsenide substrate), or a semiconductor-on-insulator (SOI) substrate, but the present invention does not This is the limit. In some embodiments, the substrate 100 may have required components such as semiconductor components (such as active components and/or passive components) (not shown), and their description is omitted here.

Next, a dielectric layer 102 is formed on the substrate 100 . The dielectric layer 102 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 102 is, for example, silicon oxide. In some embodiments, the dielectric layer 102 is formed by a chemical vapor deposition method (eg, plasma-enhanced chemical vapor deposition (PECVD)). In some embodiments, the dielectric layer 102 may have required components such as interconnect structures (not shown), and their description is omitted here.

Electrodes 104 may then be formed in dielectric layer 102 . In some embodiments, the material of the electrode 104 is, for example, copper or aluminum. In some embodiments, the electrode 104 may be formed by a damascene process.

Referring to FIG. 1B , a heating material layer 106 , a phase change material layer 108 and an electrode material layer 110 can be formed sequentially on the dielectric layer 102 and the electrode 104 . In some embodiments, the material of the heating material layer 106 is, for example, a conductive material such as tungsten. In some embodiments, the heating material layer 106 is formed by a physical vapor deposition method or a chemical vapor deposition method, for example. In some embodiments, the material of the phase change material layer 108 is, for example, a phase change material such as germanium antimony tellurium alloy (Ge-Sb-Te alloy). In some embodiments, the phase change material layer 108 is formed by, for example, physical vapor deposition. In some embodiments, the material of the electrode material layer 110 is, for example, a conductive material such as aluminum. In some embodiments, the electrode material layer 110 is formed by, for example, physical vapor deposition.

Referring to FIG. 1C, the electrode material layer 110, the phase change material layer 108 and the heating material layer 106 can be patterned to form the electrode 110a, the phase change layer 108a and the heating layer 106a. In some embodiments, the electrode material layer 110, the phase change material layer 108, and the heating material layer 106 can be patterned through a photolithography process and an etching process. In other embodiments, the electrode material layer 110 , the phase change material layer 108 and the heating material layer 106 can be patterned by using a patterned hard mask layer (not shown) as a mask.

In addition, through the above method, multiple phase change memory cells 112 can be formed. Each phase change memory cell 112 includes an electrode 104, a heating layer 106a, a phase change layer 108a and an electrode 110a. Electrodes 104 are disposed in dielectric layer 102 . The heating layer 106a is provided on the electrode 104. The material of the heating layer 106a is, for example, a conductive material such as tungsten. The phase change layer 108a is provided on the heating layer 106a. The material of the phase change layer 108a is, for example, a phase change material such as germanium antimony tellurium alloy. The electrode 110a is provided on the phase change layer 108a. The material of the electrode 110a is, for example, a conductive material such as aluminum. In addition, there may be openings OP on both sides of the phase change memory cell 112 . In some embodiments, the opening OP may be located between two adjacent electrodes 110a, between two adjacent phase change layers 108a, and between two adjacent heating layers 106a.

Referring to FIG. 1D, the dielectric layer 114 can be conformally formed on the dielectric layer 102, the heating layer 106a, the phase change layer 108a and the electrode 110a. In some embodiments, the material of the dielectric layer 114 is, for example, silicon nitride. In some embodiments, the dielectric layer 114 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1E , a dielectric layer 116 filling the opening OP may be formed on the dielectric layer 114 . In some embodiments, the material of the dielectric layer 116 is, for example, silicon oxide. In some embodiments, the dielectric layer 116 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1F , the dielectric layer 114 can be used as a termination layer to perform a planarization process on the dielectric layer 116 . In some embodiments, after the dielectric layer 116 is subjected to a planarization process, a portion of the dielectric layer 114 may be exposed. In some embodiments, the planarization process is, for example, a chemical mechanical polishing process. For example, the dielectric layer 114 can be used as a polishing stop layer, and a chemical mechanical polishing process can be performed on the dielectric layer 116 to planarize the dielectric layer 116 .

Referring to FIG. 1G , after performing a planarization process on the dielectric layer 116 , part of the dielectric layer 116 can be removed to reduce the height of the dielectric layer 116 . In some embodiments, the height of the top surface S1 of the dielectric layer 116 may be lower than the height of the top surface S2 of the electrode 110a. In some embodiments, the height of the top surface S1 of the dielectric layer 116 may be equal to or higher than the height of the bottom surface S3 of the electrode 110a. In some embodiments, the height of the top surface S1 of the dielectric layer 116 may be lower than the height of the top surface S2 of the electrode 110a, and the height of the top surface S1 of the dielectric layer 116 may be equal to or higher than the height of the bottom surface S3 of the electrode 110a. high. In some embodiments, part of the dielectric layer 116 is removed by, for example, dry etching.

In addition, during the process of removing part of the dielectric layer 116, part of the dielectric layer 114 on the electrode 110a may be removed at the same time. In some embodiments, during the process of removing part of the dielectric layer 116, part of the dielectric layer 114 on the top surface S2 of the electrode 110a may be removed at the same time, and further, part of the sidewalls of the electrode 110a may be removed at the same time. part of the dielectric layer 114 on.

Referring to FIG. 1H , dielectric layer 118 may be formed on dielectric layer 114 and dielectric layer 116 . In some embodiments, the dielectric layer 118 may be further formed on the electrode 110a. In some embodiments, dielectric layer 118 may be conformally formed over dielectric layer 114, dielectric layer 116, and electrode 110a. In some embodiments, the material of the dielectric layer 118 is, for example, silicon nitride. In some embodiments, the dielectric layer 118 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 1I, the dielectric layer 116 can be removed to form the air gap AG. Thereby, an air gap AG can be formed between two adjacent phase change memory cells 112 . In this embodiment, the air gap AG is located between two adjacent heating layers 106a and between two adjacent phase change layers 108a. In some embodiments, air gaps AG may be formed on both sides of the phase change memory cell 112 . In addition, the formation position of the air gap AG can be adjusted by adjusting the height of the dielectric layer 116 in FIG. 1G . For example, in other embodiments, the air gap AG may be located between two adjacent electrodes 110a.

In some embodiments, the method of removing dielectric layer 116 may include the following steps. First, a hole (not shown) may be formed in the dielectric layer 118 at the edge of the phase change memory cell region, and the hole exposes part of the dielectric layer 116 . In some embodiments, the dielectric layer 116 may be patterned through a photolithography process and an etching process to form holes. Then, a wet etching process can be performed on the dielectric layer 116 to remove the dielectric layer 116 . In the above wet etching process, the etchant can pass through the holes to etch the dielectric layer 116 , thereby removing the dielectric layer 116 . In some embodiments, the etching rate of the dielectric layer 116 by the wet etching process may be much greater than the etching rate of the dielectric layer 114 by the wet etching process and the etching rate of the dielectric layer 118 by the wet etching process.

Referring to FIG. 1J , dielectric layer 120 may be formed on dielectric layer 118 . The material of the dielectric layer 120 is, for example, silicon oxide. In some embodiments, the dielectric layer 120 is formed by a chemical vapor deposition method (eg, plasma enhanced chemical vapor deposition (PECVD)).

Next, plugs 122 may be formed in dielectric layer 120 . The plug 122 can pass through the dielectric layer 118 and be electrically connected to the electrode 110a. In some embodiments, plug 122 may be a via plug. In some embodiments, the plug 122 is made of a conductive material such as tungsten. In some embodiments, plug 122 may be formed by a damascene process.

Hereinafter, the phase change memory structure 10 of the above embodiment will be described with reference to FIG. 1J. In addition, although the method for forming the phase change memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 1J , the phase change memory structure 10 includes a substrate 100 , a dielectric layer 102 and a plurality of phase change memory cells 112 . In some embodiments, the plurality of phase change memory cells 112 can be separated from each other. Dielectric layer 102 is disposed on substrate 100 . Each phase change memory cell 112 includes an electrode 104, a heating layer 106a, a phase change layer 108a and an electrode 110a. Electrodes 104 are disposed in dielectric layer 102 . The heating layer 106a is provided on the electrode 104. In this embodiment, the width of the heating layer 106a may be equal to the width of the electrode 104, but the invention is not limited thereto. In other embodiments, the width of heating layer 106a may be greater or less than the width of electrode 104. The phase change layer 108a is provided on the heating layer 106a. The electrode 110a is provided on the phase change layer 108a. In some embodiments, the sidewalls of the electrode 110a, the phase change layer 108a, and the heating layer 106a may be aligned with each other. There is an air gap AG between two adjacent phase change memory cells 112 . The air gap AG is located between two adjacent heating layers 106a and between two adjacent phase change layers 108a.

The phase change memory structure 10 may further include a dielectric layer 114 and a dielectric layer 118 . The dielectric layer 114 is disposed between the air gap AG and the phase change layer 108a, between the air gap AG and the heating layer 106a, and between the air gap AG and the dielectric layer 102. The dielectric layer 114 may be conformally disposed on the sidewalls of the phase change layer 108a, the sidewalls of the heating layer 106a, and the top surface of the dielectric layer 102. The dielectric layer 118 is disposed above the air gap AG and connected to the dielectric layer 114 . In some embodiments, the dielectric layer 118 may be further disposed on the electrode 110a. In some embodiments, dielectric layer 114 and dielectric layer 118 may surround air gap AG.

The phase change memory structure 10 may further include a dielectric layer 120 and a plug 122 . Dielectric layer 120 is disposed on dielectric layer 118 . The plug 122 is disposed in the dielectric layer 120 and is electrically connected to the electrode 110a. In some embodiments, plug 122 can pass through dielectric layer 118 and be electrically connected to electrode 110a.

In addition, the details of each component in the capacitor structure 10 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again.

Based on the above embodiments, it can be seen that in the phase change memory structure 10 and its manufacturing method, there is an air gap AG between two adjacent phase change memory cells 112, and the air gap AG is located between two adjacent heating layers 106a. between two adjacent phase change layers 108a. Since the air gap AG has poor thermal conductivity, when operating the selected phase change memory cell 112, the air gap between two adjacent heating layers 106a and between two adjacent phase change layers 108a can be used. AG is used to prevent heat energy from dissipating, thereby effectively reducing operating power (eg, reset power) and preventing thermal interference between phase change memory cells 112 .

2A to 2C are cross-sectional views of the manufacturing process of phase change memory structures and manufacturing methods according to other embodiments of the present invention.

Please refer to FIG. 2A to provide a structure as shown in FIG. 1F. In addition, the structure of FIG. 1F and its manufacturing method have been described in detail in the above embodiments and will not be described again. As shown in FIG. 2A , the height of the top surface S1 of the dielectric layer 116 may be higher than the height of the top surface S2 of the electrode 110a.

Next, dielectric layer 118 may be formed on dielectric layer 114 and dielectric layer 116 . In some embodiments, the material of the dielectric layer 118 is, for example, silicon nitride. In some embodiments, the dielectric layer 118 is formed by a chemical vapor deposition method, for example.

Referring to FIG. 2B , the dielectric layer 116 can be removed to form the air gap AG. Thereby, an air gap AG can be formed between two adjacent phase change memory cells 112 . The air gap AG is located between two adjacent heating layers 106a and between two adjacent phase change layers 108a. In this embodiment, the air gap AG may be further located between two adjacent electrodes 110a.

In some embodiments, the method of removing dielectric layer 116 may include the following steps. First, a hole (not shown) may be formed in the dielectric layer 118 at the edge of the phase change memory cell region, and the hole exposes part of the dielectric layer 116 . In some embodiments, the dielectric layer 116 may be patterned through a photolithography process and an etching process to form holes. Then, a wet etching process can be performed on the dielectric layer 116 to remove the dielectric layer 116 . In the above wet etching process, the etchant can pass through the holes to etch the dielectric layer 116 , thereby removing the dielectric layer 116 . In some embodiments, the etching rate of the dielectric layer 116 by the wet etching process may be much greater than the etching rate of the dielectric layer 114 by the wet etching process and the etching rate of the dielectric layer 118 by the wet etching process.

Referring to FIG. 2C , dielectric layer 120 may be formed on dielectric layer 118 . The material of the dielectric layer 120 is, for example, silicon oxide. In some embodiments, the dielectric layer 120 is formed by a chemical vapor deposition method (eg, plasma enhanced chemical vapor deposition method).

Next, plugs 122 may be formed in dielectric layer 120 . The plug 122 can pass through the dielectric layer 118 and the dielectric layer 114 to be electrically connected to the electrode 110a. In some embodiments, plug 122 may be a through-hole plug. In some embodiments, the plug 122 is made of a conductive material such as tungsten. In some embodiments, plug 122 may be formed by a damascene process.

The phase change memory structure 20 of the above embodiment will be described below with reference to FIG. 2C. In addition, although the method for forming the phase change memory structure 20 is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIG. 2C , the phase change memory structure 20 includes a substrate 100 , a dielectric layer 102 and a plurality of phase change memory cells 112 . In some embodiments, the plurality of phase change memory cells 112 can be separated from each other. Dielectric layer 102 is disposed on substrate 100 . Each phase change memory cell 112 includes an electrode 104, a heating layer 106a, a phase change layer 108a and an electrode 110a. Electrodes 104 are disposed in dielectric layer 102 . The heating layer 106a is provided on the electrode 104. In this embodiment, the width of the heating layer 106a may be equal to the width of the electrode 104, but the invention is not limited thereto. In other embodiments, the width of heating layer 106a may be greater or less than the width of electrode 104. The phase change layer 108a is provided on the heating layer 106a. The electrode 110a is provided on the phase change layer 108a. In some embodiments, the sidewalls of the electrode 110a, the phase change layer 108a, and the heating layer 106a may be aligned with each other. There is an air gap AG between two adjacent phase change memory cells 112 . The air gap AG is located between two adjacent heating layers 106a and between two adjacent phase change layers 108a. In this embodiment, the air gap AG may be further located between two adjacent electrodes 110a.

The phase change memory structure 20 may further include a dielectric layer 114 and a dielectric layer 118 . The dielectric layer 114 is disposed between the air gap AG and the electrode 110a, between the air gap AG and the phase change layer 108a, between the air gap AG and the heating layer 106a, and between the air gap AG and the dielectric layer 102. The dielectric layer 114 may be conformally disposed on the sidewalls of the electrode 110a, the sidewalls of the phase change layer 108a, the sidewalls of the heating layer 106a, and the top surface of the dielectric layer 102. The dielectric layer 118 is disposed above the air gap AG and connected to the dielectric layer 114 . In some embodiments, dielectric layer 114 and dielectric layer 118 may surround air gap AG.

The phase change memory structure 20 may further include a dielectric layer 120 and a plug 122. Dielectric layer 120 is disposed on dielectric layer 118 . The plug 122 is disposed in the dielectric layer 120 and is electrically connected to the electrode 110a. In some embodiments, the plug 122 can pass through the dielectric layer 118 and the dielectric layer 114 to be electrically connected to the electrode 110a.

In addition, the details of each component in the capacitor structure 20 (such as materials and formation methods, etc.) have been described in detail in the above embodiments and will not be described again.

Based on the above embodiments, it can be seen that in the phase change memory structure 20 and its manufacturing method, there is an air gap AG between two adjacent phase change memory cells 112, and the air gap AG is located between two adjacent heating layers 106a. between two adjacent phase change layers 108a. Since the air gap AG has poor thermal conductivity, when operating the selected phase change memory cell 112, the air gap between two adjacent heating layers 106a and between two adjacent phase change layers 108a can be used. AG is used to prevent heat energy from dissipating, thereby effectively reducing operating power (eg, reset power) and preventing thermal interference between phase change memory cells 112 .

To sum up, in the phase change memory structure and the manufacturing method of the above embodiments, the air gap between two adjacent heating layers and between two adjacent phase change layers has poor thermal conductivity. , therefore when operating selected phase change memory cells, the air gap can be used to prevent heat energy from dissipating, thus effectively reducing operating power (such as reset power) and preventing thermal interference between phase change memory cells.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10, 20: Phase change memory structure

100:Base

102, 114, 116, 118, 120: Dielectric layer

104, 110a:Electrode

106: Heating material layer

106a: Heating layer

108: Phase change material layer

108a: Phase change layer

110: Electrode material layer

112:Phase change memory cell

122:Plug

AG: air gap

OP: Open your mouth

S1, S2: top surface

S3: Bottom

1A to 1J are cross-sectional views of the manufacturing process of a phase change memory structure and a manufacturing method thereof according to some embodiments of the present invention. 2A to 2C are cross-sectional views of the manufacturing process of phase change memory structures and manufacturing methods according to other embodiments of the present invention.

10: Phase change memory structure

100:Base

102,114,118,120: Dielectric layer

104,110a:Electrode

106a: Heating layer

108a: Phase change layer

112:Phase change memory cell

122:Plug

AG: air gap

Claims (10)

A phase change memory structure, including: a substrate; a first dielectric layer disposed on the substrate; and a plurality of phase change memory cells, wherein each of the phase change memory cells includes: a first electrode disposed on the In the first dielectric layer; a heating layer is provided on the first electrode, wherein the first electrode directly contacts the heating layer; a phase change layer is provided on the heating layer; and a second electrode, is provided on the phase change layer, wherein there is an air gap between two adjacent phase change memory cells, and the air gap is located between two adjacent heating layers and between two adjacent heating layers. between the phase change layers. The phase change memory structure of claim 1, wherein the air gap is located between two adjacent second electrodes. The phase change memory structure of claim 1, wherein the side walls of the second electrode, the side walls of the phase change layer and the side walls of the heating layer are aligned with each other. The phase change memory structure of claim 1, further comprising: a second dielectric layer disposed between the air gap and the phase change layer, between the air gap and the heating layer, and between the air gap and the heating layer. between the air gap and the first dielectric layer; and a third dielectric layer disposed above the air gap and connected to the second dielectric layer. The phase change memory structure of claim 4, wherein the second dielectric layer is conformally disposed on the sidewalls of the phase change layer, the sidewalls of the heating layer and the top of the first dielectric layer. On the surface. The phase change memory structure of claim 4, wherein the second dielectric layer and the third dielectric layer surround the air gap. The phase change memory structure of claim 4, wherein the third dielectric layer is further disposed on the two electrodes. A method of manufacturing a phase change memory structure, including: providing a substrate; forming a first dielectric layer on the substrate; forming a plurality of phase change memory cells, wherein each of the phase change memory cells includes: a first electrode, disposed in the first dielectric layer; a heating layer disposed on the first electrode, wherein the first electrode directly contacts the heating layer; a phase change layer disposed on the heating layer; and Two electrodes are arranged on the phase change layer; and an air gap is formed between two adjacent phase change memory cells, wherein the air gap is located between two adjacent heating layers and adjacent between the two phase change layers. The manufacturing method of a phase change memory structure according to claim 8, wherein there are openings on both sides of the phase change memory cell, and the forming method of the air gap includes: in the first dielectric layer, the The heating layer, the phase change layer and the second A second dielectric layer is conformally formed on the electrode; a third dielectric layer filling the opening is formed on the second dielectric layer; the second dielectric layer is used as a termination layer, and the third dielectric layer is formed on the second dielectric layer. Performing a planarization process on three dielectric layers; forming a fourth dielectric layer on the second dielectric layer and the third dielectric layer; and removing the third dielectric layer to form the air gap . The manufacturing method of a phase change memory structure as claimed in claim 9, further comprising: after performing the planarization process on the third dielectric layer, removing part of the third dielectric layer to reduce the The height of the third dielectric layer, wherein during the process of removing a portion of the third dielectric layer, a portion of the second dielectric layer located on the second electrode is also removed.

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