CN109727990A - A kind of three-dimensional storage and its manufacturing method - Google Patents
A kind of three-dimensional storage and its manufacturing method Download PDFInfo
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
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- 239000002699 waste material Substances 0.000 abstract 1
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Abstract
The invention discloses a kind of three-dimensional storage and its manufacturing methods.Above-mentioned manufacturing method includes: to provide the first wafer and the second wafer, and above-mentioned first wafer includes the first substrate and first medium layer, and the top of above-mentioned second wafer is the peripheral components of above-mentioned three-dimensional storage；The well region that the array element of above-mentioned three-dimensional storage is formed in above-mentioned first medium layer forms above-mentioned array element on above-mentioned first wafer top；Above-mentioned first wafer and above-mentioned second wafer are bonded, is the first bonding interface between above-mentioned array element and above-mentioned peripheral components；The first cutting above-mentioned first wafer of interface cut between above-mentioned first medium layer and above-mentioned first substrate, makes above-mentioned first wafer of above-mentioned first substrate desquamation.The present invention can overcome prior art processes process complicated, and the defect of waste silicon wafer.
Description
Technical field
The present invention relates to a kind of memory and its manufacturing method more particularly to a kind of three-dimensional storage and a kind of three-dimensionals
The manufacturing method of memory.
Background technique
With the continuing emphasis to highly integrated electronic device, to higher speed and lower Power operation and having
There are lasting demands for the semiconductor storage unit of the device density of increase.To reach this purpose, having been developed has more
The device of small size and multilayer device with the transistor unit arranged with horizontal and vertical array.Three-dimensional storage is industry
The emerging flash type of the one kind researched and developed, two dimension or planar flash memory are solved by vertical stacking multi-layer data storage unit
Bring limitation, has brilliant precision, supports to receive higher memory capacity in smaller space content, can create storage
Capacity is up to the storage equipment of several times than similar flash memory technology, and then effectively reduces cost and energy consumption, can meet numerous disappear comprehensively
Take class mobile device and requires the demand of most harsh enterprise's deployment.
Existing three-dimensional storage utilizes drain selection door, to control the conducting and shutdown in source channel on silicon substrate, into
And electric current is conducted by flash memory string to common source contact.
As shown in figures 1A-c, the manufacturing method of existing three-dimensional storage needs successively to carry out the organic semiconductor device back side
Technique and the technique for drawing back metal pad, above-mentioned manufacturing method have following defects that
1, it needs through hard mask deposition/photoengraving/dry or wet etch/chemically mechanical polishing (Chemical
Mechanical polishing, CMP) technique, with the organic semiconductor device back side, process flow is complex and costly high, and can introduce
Additional problem (such as: wafer defect)；
2, silicon wafer is wasted, and cannot be recycled after adhesion process.
Therefore, this field needs a kind of three-dimensional storage and its manufacturing method, to overcome of the existing technology above-mentioned lack
It falls into.
Summary of the invention
A brief summary of one or more aspects is given below to provide to the basic comprehension in terms of these.This general introduction is not
The extensive overview of all aspects contemplated, and be both not intended to identify critical or decisive element in all aspects also non-
Attempt to define the range in terms of any or all.Its unique purpose is to provide the one of one or more aspects in simplified form
A little concepts are with the sequence for more detailed description given later.
In order to overcome drawbacks described above of the existing technology, the present invention provides a kind of three-dimensional storages, and one kind three
Tie up the manufacturing method of memory.
The manufacturing method of above-mentioned three-dimensional storage provided by the invention, comprising:
First wafer and the second wafer be provided, above-mentioned first wafer includes the first substrate and first medium layer, and above-mentioned second
The top of wafer is the peripheral components of above-mentioned three-dimensional storage；
The well region that the array element of above-mentioned three-dimensional storage is formed in above-mentioned first medium layer, on above-mentioned first wafer
Portion forms above-mentioned array element；
Above-mentioned first wafer and above-mentioned second wafer are bonded, it is viscous for first between above-mentioned array element and above-mentioned peripheral components
Junction interface；
The first cutting above-mentioned first wafer of interface cut between above-mentioned first medium layer and above-mentioned first substrate, makes
State above-mentioned first wafer of the first substrate desquamation.
Preferably, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, the step of above-mentioned first wafer is provided
Suddenly it may further include:
Above-mentioned first substrate and third substrate are provided；
Above-mentioned first medium layer is formed in above-mentioned third substrate；
Above-mentioned first substrate and above-mentioned third substrate are bonded, is second between above-mentioned first substrate and above-mentioned first medium layer
Bonding interface；
It is the above-mentioned third lining of the second cutting interface cut with interface of the above-mentioned first medium layer in above-mentioned third substrate
Bottom makes above-mentioned first medium layer remove above-mentioned third substrate.
Preferably, it in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, is formed in above-mentioned third substrate
Above-mentioned first medium layer may further include:
The processing of note hydrogen is carried out in above-mentioned third substrate surface to form note hydrogen layer, and above-mentioned first medium layer is above-mentioned note hydrogen
Layer.
Preferably, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, the shape in above-mentioned first medium layer
At the array element of above-mentioned memory well region the step of can further include:
Ion implanting is executed to above-mentioned note hydrogen layer, to form above-mentioned well region；
High annealing, to solidify the PN junction in above-mentioned well region and the above-mentioned note hydrogen layer of degasification as hydrogen-rich layer.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, providing above-mentioned first substrate can be with
Further comprise:
Porous oxidation processing is carried out in above-mentioned first substrate to form porous silica layer.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, bond above-mentioned first substrate with it is upper
Stating third substrate may further include:
It is inverted above-mentioned third substrate, above-mentioned first medium layer is made to be bonded in the upper surface of above-mentioned first substrate.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, after cutting above-mentioned third substrate, also
May include:
Above-mentioned second cutting interface is processed by shot blasting.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, after cutting above-mentioned first wafer, also
May include:
Above-mentioned first medium layer surface is processed by shot blasting.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, above-mentioned polishing treatment can be change
Learn mechanical polishing.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, bond above-mentioned first wafer with it is upper
Stating the second wafer may further include:
It is inverted above-mentioned first wafer, above-mentioned array element is made to be bonded in the upper surface of above-mentioned peripheral components, that is removed is upper
It states the first substrate and is located at top.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, bond above-mentioned first wafer with it is upper
Stating the second wafer also may further include:
It is inverted above-mentioned second wafer, above-mentioned peripheral components is made to be bonded in the upper surface of above-mentioned array element；
The step of cutting above-mentioned first wafer can also include:
Above-mentioned first wafer and above-mentioned second wafer after being inverted bonding, above-mentioned first substrate removed are located at top.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, smart peeling can be passed through
The method of (smart cut) executes above-mentioned cutting.
According to another aspect of the present invention, the present invention also provides a kind of three-dimensional storage, above-mentioned three-dimensional storage can be with
It is using manufactured by any one of the above manufacturing method.
Detailed description of the invention
Figure 1A shows the structural schematic diagram before the existing three-dimensional storage organic semiconductor device back side.
Figure 1B shows the structural schematic diagram after the existing three-dimensional storage organic semiconductor device back side.
Fig. 1 C shows the structural schematic diagram after existing three-dimensional storage extraction back metal pad.
Fig. 2 shows the flow diagrams for the three-dimensional storage manufacturing method that one embodiment of the present of invention provides.
Fig. 3 shows the flow diagram of the first wafer of acquisition of one embodiment of the present of invention offer.
Fig. 4 shows the flow diagram of the formation well region of one embodiment of the present of invention offer.
Fig. 5 A shows the schematic diagram that first medium layer is formed in third substrate of one embodiment of the present of invention offer.
Fig. 5 B shows the structural representation of the third substrate with first medium layer of one embodiment of the present of invention offer
Figure.
The structure that Fig. 5 C shows the first substrate with porous silica layer of one embodiment of the present of invention offer is shown
It is intended to.
Fig. 5 D shows the schematic diagram of bonding the first substrate and third substrate of one embodiment of the present of invention offer.
Fig. 5 E shows the schematic diagram of the removing third substrate of one embodiment of the present of invention offer.
Fig. 5 F shows the structural schematic diagram of the first wafer of one embodiment of the present of invention offer.
Fig. 5 G shows the structural schematic diagram of the first wafer with array element of one embodiment of the present of invention offer.
Fig. 5 H shows the schematic diagram of bonding the first wafer and the second wafer of one embodiment of the present of invention offer.
Fig. 5 I shows the schematic diagram of the first substrate of removing of one embodiment of the present of invention offer.
Fig. 5 J shows the structural schematic diagram of the three-dimensional storage of one embodiment of the present of invention offer.
Fig. 6 shows the well region structural schematic diagram of the 3 D memory array unit of one embodiment of the present of invention offer.
Appended drawing reference:
1 silicon substrate；
2 array elements；
3 bonding interfaces；
4 CMOS wafers；
5 back metal pads；
10 first wafers；
11 first substrates；
12 first medium layers；
13 well regions；
131 dielectric oxidation silicon；
132 high pressure p-wells；
133 high pressure N traps；
134 deep N-wells；
135 epitaxial crystallization silicon substrates；
14 array elements；
15 third substrates；
16 porous silica layer；
20 second wafers；
21 peripheral components；
30 first bonding interfaces；
31 first cutting interfaces；
32 second bonding interfaces；
33 second cutting interfaces；
The step of manufacturing method of 201-206 three-dimensional storage；
2011-2016 obtains the step of the first wafer；
2021-2022 forms the step of well region.
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this specification
Revealed content is understood other advantages and efficacy of the present invention easily.Although description of the invention will combine preferred embodiment
It introduces together, but this feature for not representing the invention is only limitted to the embodiment.On the contrary, being invented in conjunction with embodiment
The purpose of introduction is to be possible to the other selections extended or transformation to cover based on claim of the invention.In order to mention
For that will include many concrete details in depth understanding of the invention, being described below.The present invention can also be thin without using these
Section is implemented.In addition, in order to avoid confusion or obscuring emphasis of the invention, some details will be omitted in the de-scription.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In addition, in the following description used in "upper", "lower", "left", "right", "top", "bottom", "horizontal", " hang down
It directly " should be understood orientation depicted in this section and relevant drawings.The term of this relativity explanation merely for convenience
With not representing device that it is described need to be manufactured or be operated with particular orientation, therefore should not be construed as to of the invention
Limitation.
As used herein term " ... top (over) ", " ... lower section (under) ", " ... between
(between) " and " ... upper (on) " refer to this layer relative to other layers of relative position.Similarly, for example, by sinking
One layer for accumulating or being placed on above or below another layer directly can contact or can have one or more with another layer
A middle layer.In addition, one layer being deposited or being placed between layer directly can contact with these layers or can have one
A or multiple middle layers.In contrast, the first layer in second layer "upper" is contacted with the second layer.Further it is provided that one layer of phase
For other layers of relative positions (assuming that film operation is deposited, modified and removed relative to starting substrates without considering base
The absolute orientation at bottom).
It is appreciated that, although term " first ", " second ", " third " etc. can be used herein to describe various assemblies, area
Domain, layer and/or part, these components, regions, layers, and/or portions should not be limited by these terms, and these terms are intended merely to
Distinguish different components, regions, layers, and/or portions.Therefore, first assembly discussed below, regions, layers, and/or portions can be
It is referred to as the second component, regions, layers, and/or portions in the case where without departing from some embodiments of the invention.
In order to overcome drawbacks described above of the existing technology, the present invention provides a kind of embodiment of three-dimensional storage, with
And a kind of embodiment of the manufacturing method of three-dimensional storage.
As shown in Fig. 2, may include step in the manufacturing method of three-dimensional storage provided in this embodiment:
201: the first wafer 10 and the second wafer 20 are provided.
Above-mentioned first wafer 10 (being illustrated in Fig. 5 F) includes: the first substrate 11 and first medium layer 12, above-mentioned first substrate
11 can be made of suitable material, including but not limited to, SiGe, germanium or silicon on insulator (SOI).
Above-mentioned second wafer 20 (being illustrated in Fig. 5 H) may include: the peripheral components set on above-mentioned second wafer, 20 top
21, above-mentioned peripheral components 21 include multiple transistors, and above-mentioned multiple transistors can be CMOS transistor.Those skilled in the art
It should be known that above-mentioned second wafer 20 can also include the peripheral interconnection layer for drawing peripheral components 21, above-mentioned peripheral components 21 and/
Or above-mentioned peripheral interconnection layer can be formed by technology semiconductor fabrication process that is existing or will having.
Above-mentioned periphery interconnection layer covering transistor is to carry out electric signal conduction, including one or more interlayer insulating films.On
Stating peripheral interconnection layer can further include one or more contacts in interlayer insulating film, and one or more interconnections are led
Body layer.Contact and interconnection conductors layer are made of an electrically conducting material, and can be one of tungsten, cobalt, copper, aluminium and metal silicide or more
The combination of kind, or other suitable materials.Interlayer insulating film is made of insulating material, can for silica, silicon nitride,
One of silicon oxynitride and doped silicon oxide or a variety of combinations, or other suitable materials.
As shown in figure 3, above-mentioned first wafer 10 can be provided by following methods:
2011: the first substrate 11 and third substrate 15 are provided.
2012: as shown in Figure 5A, carrying out note hydrogen processing on 15 surface of third substrate, be situated between with forming as shown in Figure 5 B first
Matter layer (note hydrogen layer) 12.
2013: as shown in Figure 5 C, carrying out porous oxidation processing, in the first substrate 11 to form porous silica layer 16.
Porous oxidation processing is a kind of porosity processing and two techniques of thermal oxide, forms the method for electric insulation layer on a silicon surface.
This method overcomes the methods of planar process, carrying out local oxide isolation and air insulated in technologic difficulty, its main feature is that being not required to
Want high temperature or prolonged heat treatment that can form thicker insulating layer.
It will be understood to those skilled in the art that being formed in the first substrate 11 more with infusing hydrogen layer 12 as first medium layer
Hole silicon oxide layer 16, only a kind of preferred embodiment provided in this embodiment, is mainly used for carrying out subsequent cutting operation, thus into
One step simplifies the process at the organic semiconductor device back side.In other embodiments, those skilled in the art can also use other materials
First medium layer, or in the first substrate 11 formed other materials separation layer, to obtain identical effect.
2014: as shown in Figure 5 D, being inverted third substrate 15, first medium layer 12 is made to be bonded in the upper table of the first substrate 11
Face, for the second bonding interface 32, to bond the first substrate 11 and third substrate 15 between the first substrate 11 and first medium layer 12.
2015: being the second cutting interface 33 with interface of the first medium layer 12 in third substrate 15 as shown in fig. 5e
Third substrate 15 is cut, first medium layer 12 is made to remove third substrate 15.Above-mentioned cutting can pass through smart peeling (smart
Cut method) executes.It is understood that smart peeling (smart cut) though be a kind of preferably embodiment, without
As limit, those skilled in the art can be by existing or other means having are realized that above-mentioned first medium layer is served as a contrast from third
The mode of bottom removing, details are not described herein.
2016: the second cutting interface 33 being processed by shot blasting, to obtain above-mentioned first wafer provided in this embodiment
10。
It will be understood to those skilled in the art that above-mentioned steps 2016 provide after cutting third substrate 15, to second
Cutting interface 33 is processed by shot blasting that only a kind of preferred embodiment provided in this embodiment, is mainly used for the second cutting of planarizing
Interface 33, preferably to carry out the well region 13 for being subsequently formed array element 2, and the first wafer 10 of bonding and the second wafer 20
Operation.Due to what is obtained using system by cutting, the uniformity at above-mentioned second cutting interface 33 is much higher than the prior art using hard
The uniformity at the interface that masked-deposition/photoengraving/dry or wet etch is cut into.Above-mentioned polishing treatment can be useization
Learn mechanical polishing (Chemical mechanical polishing, CMP) technique, the subtle buffering polishing treatment carried out
(Buffer CMP), and no longer need to carry out significantly polishing treatment.
In other embodiments, even if those skilled in the art will not make subsequent shape without above-mentioned polishing treatment
It can not be carried out at the operation of the well region 13 of array element 2, and bonding the first wafer 10 and the second wafer 20.
It will also be understood by those skilled in the art that providing the first wafer 10 provided by above-mentioned steps 2011-2016
Method, only a kind of preferred embodiment provided in this embodiment.The operation of third substrate 15 is inverted in step 2014, mainly for just
In the operation of subsequent cutting third substrate 15.In other embodiments, those skilled in the art can also use other methods
To provide same the first wafer 10 including the first substrate 11 and first medium layer 12.
As shown in Fig. 2, in the manufacturing method of above-mentioned three-dimensional storage provided in this embodiment, can with comprising steps of
202: as depicted in fig. 5g, the well region 13 of the array element 2 of above-mentioned three-dimensional storage is formed in first medium layer 12
(being illustrated in Fig. 6), and array element 14 is formed on 10 top of the first wafer.
Above-mentioned array element 14 is mainly used for the store function of above-mentioned three-dimensional storage, can specifically include vertical stacking
Multi-layer data storage unit, such as: multiple NAND strings.
Array element 14 and above-mentioned periphery interconnection interlayer are formed with array interconnection layer.In some embodiments, array interconnection
Layer may include one or more insulating layers.Above-mentioned array interconnection layer can further include one or more of insulating layer
Bit line contact, and one or more conductor layers.Above-mentioned conductor layer is made of an electrically conducting material, specifically can be by tungsten, cobalt, copper, aluminium
It constitutes, can also be made of other suitable materials with one of metal silicide or a variety of combinations.Above-mentioned insulating layer by
Insulating materials is made, specifically can be by one of silica, silicon nitride and high dielectric constant insulating material or a variety of combinations
It constitutes, can also be made of other suitable materials.
As shown in figure 4, above-mentioned well region 13 can be formed by the following method:
2021: ion implanting being executed to note hydrogen layer 12, to form well region 13；
2022: high annealing to solidify the PN junction curve in well region 13, and removes hydrogen (H) in high-temperature annealing process
Gas, above-mentioned note hydrogen layer 12 stabilize to hydrogen-rich layer.
As shown in fig. 6, above-mentioned well region 13 may include: the p-type formed on the epitaxial crystallization silicon substrate 135 of note hydrogen layer 12
Trap (P+), N-type trap (N+), high pressure p-well (HVPW) 132, high pressure N trap (HVNW) 133, deep N-well (DNW) 134, and be covered on
State the dielectric oxidation silicon 131 of 13 top of well region.
It will be understood to those skilled in the art that the method for above-mentioned formation well region 13 as shown in Figure 4, only the present embodiment
A kind of concrete scheme provided.In other embodiments, those skilled in the art can also use other methods, in note hydrogen layer
Identical well region is formed in 12.
It will also be understood by those skilled in the art that 13 structure of well region as shown in FIG. 6, only provided in this embodiment one
Kind concrete scheme.In other embodiments, those skilled in the art can also form the trap of other structures in note hydrogen layer 12
Area.
As shown in Fig. 2, in the manufacturing method of above-mentioned three-dimensional storage provided in this embodiment, can with comprising steps of
203: as illustrated in fig. 5h, for the first bonding interface 30, to bond first between array element 14 and peripheral components 21
Wafer 10 and the second wafer 20.
Above-mentioned peripheral components 21 can be set to the second wafer 20 top, be mainly used for control the second wafer 20 conducting with
Shutdown, and then electric current is conducted by flash memory string to common source contact.Above-mentioned peripheral components 21 may include being made of CMOS transistor
Logic control circuit.
First bonding interface 30 can be formed in the insulation of the insulating layer and above-mentioned array interconnection layer of above-mentioned peripheral interconnection layer
Between layer；It can also be formed between the conductor layer of above-mentioned peripheral interconnection layer and the conductor layer of above-mentioned array interconnection layer.Some
In embodiment, the insulating layer of above-mentioned periphery interconnection layer can be silicon nitride layer, and correspondingly, the insulating layer of above-mentioned array interconnection layer can
To be silicon oxide layer.In some embodiments, the insulating layer of above-mentioned peripheral interconnection layer is also possible to silicon oxide layer, correspondingly, on
The insulating layer for stating array interconnection layer is also possible to silicon nitride layer.
204: as shown in fig. 5i, it is inverted the first wafer 10, array element 14 is made to be bonded in the upper surface of peripheral components 21, and
The first substrate 11 is set to be located at top.
It will be understood to those skilled in the art that above-mentioned steps 204 are inverted the first wafer 10, it is only provided in this embodiment
A kind of concrete scheme is mainly used for corresponding to the operational requirements of the first wafer 10 of subsequent cutting.In other embodiments, this field
Technical staff can also first be inverted the second wafer 20, and peripheral components 21 is made to be bonded in the upper surface of array element 14；It is inverted again viscous
The first wafer 10 and the second wafer 20 after knot, to realize the purpose for making the first substrate 11 be located at top.
205: as shown in fig. 5i, the first cutting interface 31 between first medium layer 12 and above-mentioned first substrate 11 is cut
First wafer 10 makes the first substrate 11 remove the first wafer 10.Above-mentioned cutting can pass through the side of smart peeling (smart cut)
Method executes.It is understood that smart peeling (smart cut) though be a kind of preferably embodiment, and be not limited,
Those skilled in the art can realize above-mentioned first medium layer from third substrate desquamation by other means existing or will have
Mode, details are not described herein.
It will be understood to those skilled in the art that the smart-cut process that above-mentioned steps 205 provide is that the present embodiment mentions
A kind of preferred embodiment supplied is mainly used for saving the dry or wet etch step of the prior art, and chemically mechanical polishing
The step of (Chemical mechanical polishing, CMP), with easily cutting semiconductor wafer, thus further
Simplify the process flow at the above-mentioned organic semiconductor device back side, and improves the uniformity of wafer.
Therefore above-mentioned smart-cut process needs in step 204 more suitable for the top layer portion of cutting semiconductor wafer
First substrate 11 to be stripped is placed in top.And setting porous silica layer 16 come distinguish over note hydrogen layer 12 by way of,
The removing of the first substrate 11 can be more advantageous to.
In other embodiments, those skilled in the art can also cut the first wafer 10 using other methods, with
Remove the first substrate 11.Correspondingly, when using other methods to cut the first wafer 10, the first substrate 11 it is not absolutely required to
Positioned at top, also it is not absolutely required to form porous silica layer 16 in the first substrate 11.
206: the first cutting interface 31 of first medium layer 12 being processed by shot blasting, to obtain three as indicated at figure 5j
Tie up memory.
It will be understood to those skilled in the art that above-mentioned steps 206 provide after cutting the first wafer 10, cut to first
It cuts interface 31 to be processed by shot blasting, only a kind of preferred embodiment provided in this embodiment, is mainly used for planarizing above-mentioned first and cut
Cut interface 31.Due to what is obtained using system by cutting, the uniformity at above-mentioned second cutting interface 33 is adopted much higher than the prior art
With the uniformity at the interface that hard mask deposition/photoengraving/dry or wet etch is cut into.Above-mentioned polishing treatment can be to adopt
With chemically mechanical polishing (Chemical mechanical polishing, CMP) technique, the subtle buffering polishing carried out
It handles (Buffer CMP), and no longer needs to carry out significantly polishing treatment.In other embodiments, due to using this hair
The manufacturing method of the above-mentioned three-dimensional storage of bright offer, though those skilled in the art without above-mentioned polishing treatment, also not
It will affect the basis function storage of above-mentioned three-dimensional storage.
According to another aspect of the present invention, the present invention also provides a kind of embodiments of three-dimensional storage.
Above-mentioned three-dimensional storage provided in this embodiment can be using manufactured by any one of the above manufacturing method,
Its structure can be as indicated at figure 5j.
Although for simplify explain the above method is illustrated to and is described as a series of actions, it should be understood that and understand,
The order that these methods are not acted is limited, because according to one or more embodiments, some movements can occur in different order
And/or with from it is depicted and described herein or herein it is not shown and describe but it will be appreciated by those skilled in the art that other
Movement concomitantly occurs.
Offer is to make any person skilled in the art all and can make or use this public affairs to the previous description of the disclosure
It opens.The various modifications of the disclosure all will be apparent for a person skilled in the art, and as defined herein general
Suitable principle can be applied to other variants without departing from the spirit or scope of the disclosure.The disclosure is not intended to be limited as a result,
Due to example described herein and design, but should be awarded and principle disclosed herein and novel features phase one
The widest scope of cause.
Claims (13)
1. a kind of manufacturing method of three-dimensional storage characterized by comprising
The first wafer and the second wafer are provided, first wafer includes the first substrate and first medium layer, second wafer
Top be the three-dimensional storage peripheral components；
The well region that the array element of the three-dimensional storage is formed in the first medium layer, in first wafer top shape
At the array element；
First wafer and second wafer are bonded, is the first bonding circle between the array element and the peripheral components
Face；
First wafer described in the first cutting interface cut between the first medium layer and first substrate, makes described the
First wafer described in one substrate desquamation.
2. manufacturing method as described in claim 1, which is characterized in that the step of providing first wafer further comprises:
First substrate and third substrate are provided；
The first medium layer is formed in the third substrate；
First substrate and the third substrate are bonded, is the second bonding between first substrate and the first medium layer
Interface；
Third substrate described in interface cut is cut for second in the interface in the third substrate with the first medium layer, is made
The first medium layer removes the third substrate.
3. manufacturing method as claimed in claim 2, which is characterized in that form the first medium layer in the third substrate
Further comprise:
The processing of note hydrogen is carried out in the third substrate surface to form note hydrogen layer, and the first medium layer is the note hydrogen layer.
4. manufacturing method as claimed in claim 3, which is characterized in that form the memory in the first medium layer
The step of well region of array element, further comprises:
Ion implanting is executed to the note hydrogen layer, to form the well region；
High annealing, to solidify note hydrogen layer described in the PN junction in the well region and degasification as hydrogen-rich layer.
5. manufacturing method as claimed in claim 2, which is characterized in that providing first substrate further comprises:
Porous oxidation processing is carried out in first substrate to form porous silica layer.
6. manufacturing method as claimed in claim 2, which is characterized in that bond first substrate and the third substrate into one
Step includes:
It is inverted the third substrate, the first medium layer is made to be bonded in first upper surface of substrate.
7. manufacturing method as claimed in claim 2, which is characterized in that after cutting the third substrate, further includes:
Second cutting interface is processed by shot blasting.
8. manufacturing method as described in claim 1, which is characterized in that after cutting first wafer, further includes:
The first medium layer surface is processed by shot blasting.
9. manufacturing method as claimed in claim 7 or 8, which is characterized in that the polishing treatment is chemically mechanical polishing.
10. manufacturing method as described in claim 1, which is characterized in that bonding first wafer and second wafer into
One step includes:
It is inverted first wafer, the array element is made to be bonded in the upper surface of the peripheral components, described removed
One substrate is located at top.
11. manufacturing method as described in claim 1, which is characterized in that bonding first wafer and second wafer into
One step includes:
It is inverted second wafer, the peripheral components is made to be bonded in the upper surface of the array element；
The step of cutting first wafer further include:
First wafer and second wafer after being inverted bonding, first substrate removed are located at top.
12. manufacturing method as claimed in claim 1 or 2, which is characterized in that execute the cutting by smart-cut process.
13. a kind of use the three-dimensional storage as manufactured by manufacturing method of any of claims 1-12.
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