CN109727848A - A kind of manufacturing method of three-dimensional storage - Google Patents
A kind of manufacturing method of three-dimensional storage Download PDFInfo
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- CN109727848A CN109727848A CN201811634603.1A CN201811634603A CN109727848A CN 109727848 A CN109727848 A CN 109727848A CN 201811634603 A CN201811634603 A CN 201811634603A CN 109727848 A CN109727848 A CN 109727848A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
The invention discloses a kind of manufacturing methods of three-dimensional storage.The manufacturing method of above-mentioned three-dimensional storage, comprising: the first wafer is provided, the array layer of three-dimensional storage is formed on the first wafer；Second wafer is provided, the peripheral components layer of three-dimensional storage is formed on the second wafer；Adhesive layer is provided, the first interconnection layer of interconnection array layer back segment metal is formed in adhesive layer；The first wafer, the second wafer and adhesive layer are bonded so that adhesive layer connects array layer and peripheral components layer in the short transverse of three-dimensional storage；Wherein the first bonding surface of adhesive layer and array layer bond, and the second bonding surface and peripheral components layer of adhesive layer bond, and array layer is electrically connected with peripheral components layer by adhesive layer.The present invention is able to solve the defect that the prior art manufacturing cycle is long and the degree of modularity is low.
Description
Technical field
The present invention relates to a kind of manufacturing method of memory more particularly to a kind of manufacturing methods of three-dimensional storage.
Background technique
With the continuing emphasis to highly integrated electronic device, to higher speed and lower Power operation and having
There are lasting demands for the semiconductor storage unit of the device density of increase.To reach this purpose, having been developed has more
The device of small size and multilayer device with the transistor unit arranged with horizontal and vertical array.Three-dimensional storage is industry
The emerging flash type of the one kind researched and developed, two dimension or planar flash memory are solved by vertical stacking multi-layer data storage unit
Bring limitation, has brilliant precision, supports to receive higher memory capacity in smaller space content, can create storage
Capacity is up to the storage equipment of several times than similar flash memory technology, and then effectively reduces cost and energy consumption, can meet numerous disappear comprehensively
Take class mobile device and requires the demand of most harsh enterprise's deployment.
As illustrated in figs, the manufacturing method of existing three-dimensional storage specifically includes that
(1) it is formed in first wafer and has bit line/wordline contact array layer；
(2) CMOS peripheral components are formed in second wafer；
(3) array wafer and CMOS wafer are mixed and is bonded together.
The manufacturing method of existing three-dimensional storage has following defects that
1, cycle time is long: the processing time for forming array wafer is much longer more than the processing time for forming CMOS wafer,
Cause the total cycle time for manufacturing three-dimensional storage too long.
2, the degree of modularity is low: height interactive interference between array wafer formation process and CMOS wafer formation process, difficult
To carry out modularized production.
Therefore, this field needs a kind of three-dimensional storage and its manufacturing method, to overcome of the existing technology above-mentioned lack
It falls into.
Summary of the invention
A brief summary of one or more aspects is given below to provide to the basic comprehension in terms of these.This general introduction is not
The extensive overview of all aspects contemplated, and be both not intended to identify critical or decisive element in all aspects also non-
Attempt to define the range in terms of any or all.Its unique purpose is to provide the one of one or more aspects in simplified form
A little concepts are with the sequence for more detailed description given later.
In order to solve drawbacks described above of the existing technology, the present invention provides a kind of three-dimensional storages, and one kind three
The manufacturing method for tieing up memory, so as to shorten the manufacturing cycle of three-dimensional storage, and is mentioned by way of hoisting module degree
Rise its adaptability.
Above-mentioned three-dimensional storage provided by the invention, comprising: array layer, peripheral components layer and adhesive layer；
The first interconnection layer of interconnection array layer back segment metal is formed in above-mentioned adhesive layer, above-mentioned adhesive layer is in above-mentioned three-dimensional
Above-mentioned array layer and above-mentioned peripheral components layer are connected in the short transverse of memory；Wherein the first bonding surface of above-mentioned adhesive layer
Bonded with above-mentioned array layer, the second bonding surface of above-mentioned adhesive layer and above-mentioned peripheral components layer bond, above-mentioned array layer with it is upper
Peripheral components layer is stated to be electrically connected by above-mentioned adhesive layer.
Preferably, in above-mentioned three-dimensional storage provided by the invention, above-mentioned first interconnection layer may include: above-mentioned array
The bit line and bit line contact of layer, upper bit line contact is electrically connected above-mentioned bit line and above-mentioned array layer, upper bit line contact are exposed to
Above-mentioned first bonding surface.
Preferably, in above-mentioned three-dimensional storage provided by the invention, above-mentioned array layer may include: grade layer stack,
On channel hole along above-mentioned short transverse through above-mentioned grade layer stack, the channel layer in above-mentioned channel hole, and contact
The drain electrode of channel layer is stated, above-mentioned drain electrode is electrically connected with upper bit line contact.
Optionally, in above-mentioned three-dimensional storage provided by the invention, above-mentioned first interconnection layer also may include: common source touching
Point and wordline contact, above-mentioned common source contact are electrically connected the common source line in above-mentioned array layer, and above-mentioned wordline contact is electrically connected above-mentioned battle array
Word line contact structure in column layer, above-mentioned common source contact and above-mentioned wordline contact are exposed to above-mentioned first bonding surface.
Preferably, in above-mentioned three-dimensional storage provided by the invention, above-mentioned array layer may include grade layer stack, grid
Gap, common source line and word line contact structure；
Above-mentioned grade layer stack is run through along above-mentioned short transverse in above-mentioned grid gap, and above-mentioned common source line is formed in above-mentioned grid gap
In；
Above-mentioned word line contact structure is along above-mentioned short transverse part through above-mentioned grade layer stack to draw above-mentioned grading layer
Grid layer in storehouse.
It optionally, can also include the first metal in above-mentioned adhesive layer in above-mentioned three-dimensional storage provided by the invention
Through-hole, above-mentioned first metal throuth hole is electrically connected above-mentioned first interconnection layer and above-mentioned peripheral components layer, above-mentioned first metal throuth hole are sudden and violent
It is exposed to above-mentioned second bonding surface.
Preferably, in above-mentioned three-dimensional storage provided by the invention, above-mentioned peripheral components layer may include: peripheral components
It may include: the second metal throuth hole in above-mentioned second interconnection layer with the second interconnection layer for interconnecting above-mentioned peripheral components back segment metal,
Above-mentioned second metal throuth hole is electrically connected with above-mentioned first metal throuth hole.
According to another aspect of the present invention, the present invention also provides a kind of manufacturing methods of three-dimensional storage.
The manufacturing method of above-mentioned three-dimensional storage provided by the invention, comprising:
First wafer is provided, the array layer of above-mentioned three-dimensional storage is formed on above-mentioned first wafer；
Second wafer is provided, the peripheral components layer of above-mentioned three-dimensional storage is formed on above-mentioned second wafer；
Adhesive layer is provided, the first interconnection layer of interconnection array layer back segment metal is formed in above-mentioned adhesive layer；
Above-mentioned first wafer, above-mentioned second wafer and above-mentioned adhesive layer are bonded so that above-mentioned adhesive layer is in above-mentioned three-dimensional storage
Above-mentioned array layer and above-mentioned peripheral components layer are connected in the short transverse of device；Wherein the first bonding surface of above-mentioned adhesive layer with it is upper
Array layer bonding is stated, the second bonding surface of above-mentioned adhesive layer and above-mentioned peripheral components layer bond, above-mentioned array layer and above-mentioned outer
Peripheral device layer is electrically connected by above-mentioned adhesive layer.
Preferably, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, providing above-mentioned adhesive layer can be into
One step includes:
Third substrate is provided；
The first metal throuth hole and above-mentioned first in above-mentioned adhesive layer is sequentially formed mutually in the upper surface of above-mentioned third substrate
Even layer, the surface of above-mentioned first interconnection layer are above-mentioned first bonding surface；
Being bonded above-mentioned first wafer, above-mentioned second wafer and above-mentioned adhesive layer may further include:
The above-mentioned array layer of above-mentioned first wafer is bonded to above-mentioned first bonding surface；
Above-mentioned third substrate is removed with above-mentioned second bonding surface of the above-mentioned adhesive layer of exposure, above-mentioned first metal throuth hole is sudden and violent
It is exposed to above-mentioned second bonding surface；
The above-mentioned peripheral components layer of above-mentioned second wafer is bonded to above-mentioned second gluing of surfaces.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, providing above-mentioned adhesive layer can also be with
Further comprise:
Third substrate is provided；
Above-mentioned first interconnection layer and the first metal in above-mentioned adhesive layer are sequentially formed in the upper surface of above-mentioned third substrate
Through-hole, above-mentioned first metal throuth hole are exposed to above-mentioned second bonding surface；
Being bonded above-mentioned first wafer, above-mentioned second wafer and above-mentioned adhesive layer may further include:
The above-mentioned peripheral components layer of above-mentioned second wafer is bonded to above-mentioned second bonding surface；
Above-mentioned third substrate is removed with above-mentioned first bonding surface of the above-mentioned adhesive layer of exposure, above-mentioned first bonding surface is
The surface of above-mentioned first interconnection layer；
The above-mentioned array layer of above-mentioned first wafer is bonded to above-mentioned first bonding surface.
Preferably, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, above-mentioned offer third substrate can be with
Further comprise:
First medium layer is formed on above-mentioned third substrate top, above-mentioned adhesive layer is formed in the upper table of above-mentioned first medium layer
Face；
The above-mentioned above-mentioned third substrate of removing may further include:
It is the cutting above-mentioned third substrate of interface cut with interface of the above-mentioned first medium layer in above-mentioned third substrate, goes
Except above-mentioned first medium layer, with the first bonding surface or the second bonding surface of the above-mentioned adhesive layer of exposure.
Preferably, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, in above-mentioned third substrate top shape
It may further include at first medium layer:
The processing of note hydrogen is carried out on the surface of above-mentioned third substrate to form note hydrogen layer, and above-mentioned first medium layer is above-mentioned note hydrogen
Layer.
Optionally, in the manufacturing method of above-mentioned three-dimensional storage provided by the invention, in above-mentioned third substrate top shape
It also may further include at first medium layer:
Porous oxidation is carried out on the surface of above-mentioned third substrate to handle to form porous silica layer, above-mentioned first medium layer
For above-mentioned porous silica layer.
Based on above description, above-mentioned three-dimensional storage provided by the invention and its manufacturing method can be by above-mentioned adhesive layers
It is separated with above-mentioned array wafer and above-mentioned CMOS wafer, its advantages essentially consist in:
(1) by being respectively formed adhesive layer and array layer, the processing time to form array wafer can effectively be shortened, from
And shorten the manufacturing time of entire three-dimensional storage.
(2) by being respectively formed adhesive layer and array layer, array wafer formation process can be effectively reduced and CMOS is brilliant
Interactive interference degree between circle formation process, to promote adaptability.If the work of above-mentioned array wafer or above-mentioned CMOS wafer
Skill or structure change, then only need correspondingly to change adhesive layer structure, technique or knot without changing another wafer
Structure.
Detailed description of the invention
After the detailed description for reading embodiment of the disclosure in conjunction with the following drawings, it better understood when of the invention
Features described above and advantage.In the accompanying drawings, each component is not necessarily drawn to scale, and has similar correlation properties or feature
Component may have same or similar appended drawing reference.
Figure 1A shows the structural schematic diagram of existing 3 D memory array wafer.
Figure 1B shows the structural schematic diagram of existing three-dimensional storage CMOS wafer.
Fig. 2A shows the structural schematic diagram of the first wafer of one embodiment of the present of invention offer.
Fig. 2 B shows the structural schematic diagram of the second wafer of one embodiment of the present of invention offer.
The top in third substrate that Fig. 2 C shows one embodiment of the present of invention offer carries out the signal of note hydrogen processing
Figure.
Fig. 2 D shows the structural representation of the third substrate with first medium layer of one embodiment of the present of invention offer
Figure.
Fig. 2 E shows the structural schematic diagram of the third substrate with adhesive layer of one embodiment of the present of invention offer.
The array layer by the first wafer that Fig. 2 F shows one embodiment of the present of invention offer is bonded to the first bonding table
The schematic diagram in face.
Fig. 2 G shows the schematic diagram of the removing third substrate of one embodiment of the present of invention offer.
Fig. 2 H shows the schematic diagram of the removal first medium layer of one embodiment of the present of invention offer.
Fig. 2 I shows the structural schematic diagram of the three-dimensional storage of one embodiment of the present of invention offer.
Fig. 3 shows the structural schematic diagram of the third substrate with adhesive layer of one embodiment of the present of invention offer.
Fig. 4 shows the flow diagram of the manufacturing method of the three-dimensional storage of one embodiment of the present of invention offer.
Fig. 5 shows the flow diagram of the offer adhesive layer of one embodiment of the present of invention offer.
Fig. 6 shows the process of the first wafer of bonding of one embodiment of the present of invention offer, the second wafer and adhesive layer
Schematic diagram.
Appended drawing reference:
1 array layer；
2 bit lines/wordline contact；
3 CMOS transistors；
10 first wafers；
11 array layers；
12 word line contact structures；
13 grid gaps；
20 second wafers；
21 peripheral components layers；
22 CMOS transistors；
23 second interconnection layers；
24 second metal throuth holes；
31 adhesive layers；
32 first interconnection layers；
33 third substrates；
34 first metal throuth holes；
35 first medium layers；
36 adhesive layers；
41 first bonding surfaces；
42 second bonding surfaces；
43 cutting interfaces；
201-204 manufactures the step of three-dimensional storage；
2031-2032 provides the step of adhesive layer；
2041-2043 is bonded the step of the first wafer, the second wafer and adhesive layer.
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this specification
Revealed content is understood other advantages and efficacy of the present invention easily.Although description of the invention will combine preferred embodiment
It introduces together, but this feature for not representing the invention is only limitted to the embodiment.On the contrary, being invented in conjunction with embodiment
The purpose of introduction is to be possible to the other selections extended or transformation to cover based on claim of the invention.In order to mention
For that will include many concrete details in depth understanding of the invention, being described below.The present invention can also be thin without using these
Section is implemented.In addition, in order to avoid confusion or obscuring emphasis of the invention, some details will be omitted in the de-scription.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
In addition, in the following description used in "upper", "lower", "left", "right", "top", "bottom", "horizontal", " hang down
It directly " should be understood orientation depicted in this section and relevant drawings.The term of this relativity explanation merely for convenience
With not representing device that it is described need to be manufactured or be operated with particular orientation, therefore should not be construed as to of the invention
Limitation.
It is appreciated that, although term " first ", " second ", " third " etc. can be used herein to describe various assemblies, area
Domain, layer and/or part, these components, regions, layers, and/or portions should not be limited by these terms, and these terms are intended merely to
Distinguish different components, regions, layers, and/or portions.Therefore, first assembly discussed below, regions, layers, and/or portions can be
It is referred to as the second component, regions, layers, and/or portions in the case where without departing from some embodiments of the invention.
In order to solve drawbacks described above of the existing technology, the present invention provides a kind of embodiment of three-dimensional storage, with
And a kind of embodiment of the manufacturing method of three-dimensional storage, so as to shorten the manufacturing cycle of three-dimensional storage, and pass through Lifting Modules
The mode of block degree promotes its adaptability.
As shown in figure 4, the manufacturing method of three-dimensional storage provided in this embodiment, may include:
201: the first wafer 10 as shown in Figure 2 A being provided, the array of above-mentioned three-dimensional storage is formed on the first wafer 10
Layer 11.
Array layer 11 is mainly used for the store function of above-mentioned three-dimensional storage, can specifically include: grade layer stack, common source
Line, wordline, the channel hole along above-mentioned short transverse through above-mentioned grade layer stack, the channel layer in above-mentioned channel hole, with
And the drain electrode of the above-mentioned channel layer of contact, above-mentioned drain electrode are electrically connected with upper bit line contact.
In some embodiments, array layer 11 may include one or more insulating layers.Above-mentioned array layer 11 can also be into
One step includes one or more bit line contacts in insulating layer, and one or more conductor layers.Above-mentioned conductor layer is by conduction material
Material is made, and can specifically be made of one of tungsten, cobalt, copper, aluminium and metal silicide or a variety of combinations, can also be by other
Suitable material is constituted.Above-mentioned insulating layer is made of insulating material, specifically can be exhausted by silica, silicon nitride and high dielectric constant
One of edge material or a variety of combinations are constituted, and can also be made of other suitable materials.
Optionally, in another embodiment, above-mentioned array layer 11 also may include: grade layer stack, grid gap 13, common source
Line and word line contact structure 12.Above-mentioned grade layer stack is run through along above-mentioned short transverse in grid gap 13, and above-mentioned common source line is formed in
In grid gap 13, so that the common source line in substrate be picked out.Word line contact structure 12 is along above-mentioned short transverse part through above-mentioned
Grade layer stack, to draw the grid layer in above-mentioned grade layer stack.
It will be understood to those skilled in the art that array layer 11 can pass through semiconductor fabrication process shape that is existing or will having
At above-mentioned semiconductor fabrication process should be that those skilled in the art knows that details are not described herein.
202: the second wafer 20 as shown in Figure 2 B being provided, the periphery of above-mentioned three-dimensional storage is formed on the second wafer 20
Device layer 21.
Peripheral components layer 21 may include: the second interconnection layer of 22 back segment metal of peripheral components 22 and interconnection periphery device
23.Above-mentioned peripheral components layer 21 can be formed by semiconductor fabrication process that is existing or will having, above-mentioned semiconductor fabrication process
It should be that those skilled in the art knows that details are not described herein.
Peripheral components 22 may include the logic control circuit of multiple transistors and its composition, and above-mentioned multiple transistors can be with
For CMOS transistor, it is mainly used for controlling the conducting and shutdown of the second wafer 20, and then electric current is conducted by flash memory string to common source
Contact.
Second interconnection layer 23 can be formed by semiconductor fabrication process that is existing or will having, above-mentioned semiconductor fabrication process
It should be that those skilled in the art knows that details are not described herein.It may include: that the second metal is logical in second interconnection layer 23
Hole 24, above-mentioned second metal throuth hole 24 are electrically connected with the first metal throuth hole 34, thus by the CMOS crystal in peripheral components layer 21
Pipe 22 is communicated to bit line, wordline and/or the common source line of array layer 11.
Above-mentioned second interconnection layer 23 covers CMOS transistor to carry out electric signal conduction, including one or more layer insulations
Layer.Above-mentioned second interconnection layer 23 can further include: one or more contacts in interlayer insulating film and one or more
A interconnection conductors layer.Contact and interconnection conductors layer are made of an electrically conducting material, can be in tungsten, cobalt, copper, aluminium and metal silicide
One or more combination, or other suitable materials.Interlayer insulating film is made of insulating material, and can be oxidation
One of silicon, silicon nitride, silicon oxynitride and doped silicon oxide or a variety of combinations, or other suitable materials.
203: adhesive layer 31 as shown in Figure 2 E being provided, the first of interconnection array layer back segment metal is formed in adhesive layer 31
Interconnection layer 32.
Above-mentioned first interconnection layer 32 can be formed by semiconductor fabrication process that is existing or will having, above-mentioned semiconductors manufacture
Technique should be that those skilled in the art knows that details are not described herein.First interconnection layer 32 may include: array layer 11
Bit line and bit line contact, upper bit line contact is exposed to the first bonding surface 41, and is electrically connected rheme as shown in figure 2i
Line and array layer 11, thus by the digit line communication of array layer 11 to the CMOS transistor 22 in peripheral components layer 21.
First interconnection layer 32 can also include: common source contact and wordline contact.Above-mentioned common source contact is electrically connected above-mentioned array
The common source line of layer 11, above-mentioned wordline contact are electrically connected the word line contact structure 12 in above-mentioned array layer 11, above-mentioned common source contact and
Above-mentioned wordline contact is exposed to the first bonding surface 41, so that the wordline of array layer 11 and common source line are communicated to peripheral components layer
CMOS transistor 22 in 21.
As shown in figure 5, providing adhesive layer 31 may further include step:
2031: third substrate 33 being provided, and carries out note hydrogen processing on the top of third substrate 33 as shown in fig. 2c, with shape
At first medium layer 35 as shown in Figure 2 D.
Correspondingly, above-mentioned first medium layer 35 can be note hydrogen layer.Above-mentioned third substrate 33 can be by suitable material system
At, including but not limited to, SiGe, germanium or silicon on insulator (SOI).
2032: it is mutual to sequentially form the first metal throuth hole 34 and first in adhesive layer 31 in the upper surface of first medium layer 35
Even layer 32, and with the surface of the first interconnection layer 32 for the first bonding surface 41.
It will be understood to those skilled in the art that the method for the offer adhesive layer 31 that above-mentioned steps 2031-2032 is provided, only
It is a kind of preferred embodiment provided in this embodiment, is mainly used for forming note hydrogen layer 35 on the top of third substrate 33, in order to rear
The operation of continuous removing third substrate 33.
In other embodiments, those skilled in the art can also carry out porous oxidation to the upper surface of third substrate 33
Processing, to form porous silica layer.Above-mentioned porous oxidation processing is a kind of porosity processing and two techniques of thermal oxide,
The method of electric insulation layer is formed on silicon face.This method overcomes the methods of planar process, carrying out local oxide isolation and air insulated
In technologic difficulty, its main feature is that thicker insulating layer can be formed by not needing high temperature or prolonged heat treatment.This field
Technical staff can using porous silica layer as first medium layer 35, thus similarly realize convenient for subsequent removing third lining
The purpose that bottom 33 operates.
204: the first wafer 10 of bonding, the second wafer 20 and adhesive layer 31, so that adhesive layer 31 is in above-mentioned three-dimensional storage
Short transverse on connect array layer 11 and peripheral components layer 21.
Above-mentioned bonding operation refers under certain condition, makes wafer key by Van der Waals force, molecular force or even atomic force
Synthesize the technology being integrated.Those skilled in the art should know specific relevant technical details, and details are not described herein.
Adhesive layer 31 connects array layer 11 in the short transverse (up and down direction shown in Fig. 2 I) of above-mentioned three-dimensional storage
With peripheral components layer 21, wherein the first bonding surface 41 and the array layer 11 of adhesive layer 31 bond, the second bonding of adhesive layer 31
Surface 42 and peripheral components layer 21 bond.Array layer 11 is electrically connected with peripheral components layer 21 by adhesive layer 31.
As shown in fig. 6, the first wafer 10 of bonding, the second wafer 20 and adhesive layer 31 may further include step:
2041: as shown in Figure 2 F, the array layer 11 of the first wafer 10 being bonded to the first bonding surface 41, thus by array
First interconnection layer 32 of the digit line communication of layer 11 to adhesive layer 31.
2042: being cutting interface 43, cutting with interface of the first medium layer 35 in third substrate 33 as shown in Figure 2 G
Third substrate 33；And as illustrated in figure 2h, first medium layer 35 is removed, to expose the second bonding surface 42 of adhesive layer 31, and is made
First metal throuth hole 34 is exposed to the second bonding surface 42.
Above-mentioned cutting can be executed by the method for smart peeling (smart cut), be cut into using smart peeling
The uniformity for cutting interface 43 is cut into much higher than the prior art using hard mask deposition/photoengraving/dry or wet etch
Interface uniformity.Those skilled in the art should appreciate that the concrete technology of smart peeling, and details are not described herein.
Above-mentioned first medium layer 35 can be removed by the method for dry or wet etch, can also pass through smart peeling
The method of (smart cut) executes.
2043: the peripheral components layer 21 of the second wafer 20 is bonded to the second gluing of surfaces 42.
As shown in figure 2i, the first bonding surface 41 of adhesive layer 31 is bonded with array layer 11, the second bonding of adhesive layer 31
Surface 42 and peripheral components layer 21 bond.Array layer 11 is electrically connected with peripheral components layer 21 by adhesive layer 31.
It will be understood to those skilled in the art that the method for the offer adhesive layer 31 that above-mentioned steps 2031-2032 is provided, with
And above-mentioned steps 2041-2043 provide bonding the first wafer 10, the second wafer 20 and adhesive layer 31 method, only this implementation
A kind of concrete scheme that example provides.In other embodiments, those skilled in the art can also use following steps:
Third substrate 33 is provided；
The first interconnection layer 32 and first in adhesive layer 36 as shown in Figure 3 is sequentially formed in the upper surface of third substrate 33
Metal throuth hole 34, and the first metal throuth hole 34 is made to be exposed to the second bonding surface 42.The structure for the adhesive layer 36 that Fig. 3 is provided, on
The adhesive layer 31 provided in Fig. 2 E is provided down.
Correspondingly, those skilled in the art can also further use following steps:
The peripheral components layer 21 of second wafer 20 is bonded to the second bonding surface 42；
Third substrate 33 is removed, to expose the first bonding surface 41 of adhesive layer 31, wherein the first bonding surface 41 is the
The surface of one interconnection layer 32；
The array layer 11 of first wafer 10 is bonded to the first bonding surface 41, so that obtaining one is identical to Fig. 2 I offer
Three-dimensional storage.
Therefore, the method for the offer adhesive layer 36 provided through the foregoing embodiment, and the first wafer of bonding 10, second are brilliant
The method of circle 20 and adhesive layer 36, can obtain the effect for being identical to the present embodiment.
Based on above description, the manufacturing method of above-mentioned three-dimensional storage provided in this embodiment, can by adhesive layer 31 with
Array layer 11 and peripheral components layer 21 separate, and its advantages essentially consist in:
(1) by being respectively formed adhesive layer 31 and array layer 11, when can effectively shorten the processing to form array wafer
Between, so as to shorten the manufacturing time of entire three-dimensional storage.
(2) by being respectively formed adhesive layer 31 and array layer 11, can be effectively reduced array wafer formation process and
Interactive interference degree between CMOS wafer formation process, to promote adaptability.If above-mentioned array wafer or above-mentioned CMOS are brilliant
Round technique or structure changes, then only needs correspondingly to change adhesive layer structure, the work without changing another wafer
Skill or structure.
Although for simplify explain the above method is illustrated to and is described as a series of actions, it should be understood that and understand,
The order that these methods are not acted is limited, because according to one or more embodiments, some movements can occur in different order
And/or with from it is depicted and described herein or herein it is not shown and describe but it will be appreciated by those skilled in the art that other
Movement concomitantly occurs.
According to another aspect of the present invention, the present invention also provides a kind of embodiments of three-dimensional storage.
As shown in figure 2i, above-mentioned three-dimensional storage provided in this embodiment, comprising: array layer 11,21 and of peripheral components layer
Adhesive layer 31, wherein the first interconnection layer 32 for being interconnected to 11 back segment metal of array layer is formed in adhesive layer 31.
Array layer 11 is mainly used for the store function of above-mentioned three-dimensional storage, can specifically include: grade layer stack, common source
Line, wordline, the channel hole along above-mentioned short transverse through above-mentioned grade layer stack, the channel layer in above-mentioned channel hole, with
And the drain electrode of the above-mentioned channel layer of contact, above-mentioned drain electrode are electrically connected with upper bit line contact.
In some embodiments, array layer 11 may include one or more insulating layers.Above-mentioned array layer 11 can also be into
One step includes one or more bit line contacts in insulating layer, and one or more conductor layers.Above-mentioned conductor layer is by conduction material
Material is made, and can specifically be made of one of tungsten, cobalt, copper, aluminium and metal silicide or a variety of combinations, can also be by other
Suitable material is constituted.Above-mentioned insulating layer is made of insulating material, specifically can be exhausted by silica, silicon nitride and high dielectric constant
One of edge material or a variety of combinations are constituted, and can also be made of other suitable materials.
Peripheral components layer 21 may include: the second interconnection layer of 22 back segment metal of peripheral components 22 and interconnection periphery device
23。
Peripheral components 22 may include the logic control circuit of multiple transistors and its composition, and above-mentioned multiple transistors can be with
For CMOS transistor, it is mainly used for controlling the conducting and shutdown of the second wafer 20, and then electric current is conducted by flash memory string to common source
Contact.
Second interconnection layer 23 can be formed by technology semiconductor fabrication process that is existing or will having, wherein may include:
Second metal throuth hole 24, above-mentioned second metal throuth hole 24 are electrically connected with the first metal throuth hole 34, thus by peripheral components layer 21
CMOS transistor 22 be communicated to bit line, wordline and/or the common source line of array layer 11.
Above-mentioned second interconnection layer 23 covers CMOS transistor to carry out electric signal conduction, including one or more layer insulations
Layer.Above-mentioned second interconnection layer 23 can further include: one or more contacts in interlayer insulating film and one or more
A interconnection conductors layer.Contact and interconnection conductors layer are made of an electrically conducting material, can be in tungsten, cobalt, copper, aluminium and metal silicide
One or more combination, or other suitable materials.Interlayer insulating film is made of insulating material, and can be oxidation
One of silicon, silicon nitride, silicon oxynitride and doped silicon oxide or a variety of combinations, or other suitable materials.
Adhesive layer 31 connects array layer 11 in the short transverse (up and down direction shown in Fig. 2 I) of above-mentioned three-dimensional storage
With peripheral components layer 21, wherein the first bonding surface 41 and the array layer 11 of adhesive layer 31 bond, the second bonding of adhesive layer 31
Surface 42 and peripheral components layer 21 bond.Array layer 11 is electrically connected with peripheral components layer 21 by adhesive layer 31.
As shown in Figure 2 E, the first interconnection layer 32 may include: the bit line and bit line contact of array layer 11, upper bit line contact
It is exposed to the first bonding surface 41, and is electrically connected above-mentioned bit line and array layer 11 as shown in figure 2i, thus by array layer 11
Digit line communication is to the CMOS transistor 22 in peripheral components layer 21.
Correspondingly, as shown in Figure 2 A, array layer 11 is mainly used for the store function of above-mentioned three-dimensional storage, may include:
Grade layer stack, common source line, wordline, along above-mentioned short transverse through above-mentioned grade layer stack channel hole, be located at above-mentioned channel
Channel layer in hole, and the drain electrode of the above-mentioned channel layer of contact, above-mentioned drain electrode are electrically connected with upper bit line contact.
It will be understood to those skilled in the art that 32 structure of the first interconnection layer and battle array as shown in Figure 2 A as shown in Figure 2 E
11 structure of column layer, only a kind of concrete scheme provided in this embodiment, specific structure can be carried out according to actual use demand
Correspondingly change.
In other embodiments, those skilled in the art can also be using first including common source contact and wordline contact
32 structure of interconnection layer.Above-mentioned common source contact is electrically connected the common source line in above-mentioned array layer 11, and above-mentioned wordline contact electrical connection is above-mentioned
Word line contact structure 12 in array layer 11, above-mentioned common source contact and above-mentioned wordline contact are exposed to the first bonding surface 41, from
And the wordline of array layer 11 and common source line are communicated to the CMOS transistor 22 in peripheral components layer 21.
Correspondingly, array layer 11 may include: grade layer stack, grid gap 13, common source line and word line contact structure 12.Grid
Above-mentioned grade layer stack is run through along above-mentioned short transverse in gap 13, and above-mentioned common source line is formed in above-mentioned grid gap 13, thus will
Common source line in substrate picks out.Word line contact structure 12 runs through above-mentioned grade layer stack along above-mentioned short transverse part, to draw
Grid layer in above-mentioned grade layer stack.
In other embodiments, those skilled in the art may also correspond to array layer 11 under, and peripheral components layer
21 in upper manufacturing method, using 36 structure of adhesive layer shown in Fig. 3, to sequentially form in the upper surface of first medium layer 35
Bit line contact and bit line；Or wordline contact, wordline, common source contact and common source line, thus the array layer of the first wafer 10 of connection
11 and second wafer 20 peripheral components layer 21.
It as shown in Figure 2 E, can also include: the first metal throuth hole 34 in adhesive layer 31, the first metal throuth hole 34 electrical connection the
One interconnection layer 32 and peripheral components layer 21.First metal throuth hole 34 is exposed to the second bonding surface 42.
Correspondingly, as shown in Figure 2 B, peripheral components layer 21 may include: 22 back segment of peripheral components 22 and interconnection periphery device
Second interconnection layer 23 of metal.May include: the second metal throuth hole 24 in second interconnection layer 23, above-mentioned second metal throuth hole 24 with
First metal throuth hole 34 electrical connection, thus by the CMOS transistor 22 in peripheral components layer 21 be communicated to array layer 11 bit line,
Wordline and/or common source line.
It will be understood to those skilled in the art that it will be understood to those skilled in the art that as shown in Figure 2 E first mutually
Connect 32 structure of layer and 21 structure of peripheral components layer as shown in Figure 2 B, only a kind of concrete scheme provided in this embodiment.At it
In his embodiment, those skilled in the art can also correspondingly change its specific structure according to actual use demand.
Based on above description, above-mentioned three-dimensional storage provided in this embodiment, can by adhesive layer 31 and array layer 11 and
Peripheral components layer 21 separates, and its advantages essentially consist in: the adhesive layer 31 and array layer 11 manufactured respectively can effectively drop
Interactive interference degree between low array wafer formation process and CMOS wafer formation process, to promote adaptability.If above-mentioned
The technique or structure of array wafer or above-mentioned CMOS wafer change, then only need correspondingly to change 31 structure of adhesive layer, without
Need to change the technique or structure of another wafer.
Offer is to make any person skilled in the art all and can make or use this public affairs to the previous description of the disclosure
It opens.The various modifications of the disclosure all will be apparent for a person skilled in the art, and as defined herein general
Suitable principle can be applied to other variants without departing from the spirit or scope of the disclosure.The disclosure is not intended to be limited as a result,
Due to example described herein and design, but should be awarded and principle disclosed herein and novel features phase one
The widest scope of cause.
Claims (6)
1. a kind of manufacturing method of three-dimensional storage characterized by comprising
First wafer is provided, the array layer of the three-dimensional storage is formed on first wafer；
Second wafer is provided, the peripheral components layer of the three-dimensional storage is formed on second wafer；
Adhesive layer is provided, the first interconnection layer of interconnection array layer back segment metal is formed in the adhesive layer；
First wafer, second wafer and the adhesive layer are bonded so that the adhesive layer is in the three-dimensional storage
The array layer and the peripheral components layer are connected in short transverse；Wherein the first bonding surface of the adhesive layer and the battle array
Column layer bonding, the second bonding surface of the adhesive layer and the peripheral components layer bond, the array layer and the peripheral device
Part layer is electrically connected by the adhesive layer.
2. manufacturing method as described in claim 1, which is characterized in that providing the adhesive layer further comprises:
Third substrate is provided；
The first metal throuth hole and first interconnection layer in the adhesive layer are sequentially formed in the upper surface of the third substrate,
The surface of first interconnection layer is first bonding surface；
Being bonded first wafer, second wafer and the adhesive layer further comprises:
The array layer of first wafer is bonded to first bonding surface；
The third substrate is removed with second bonding surface of the exposure adhesive layer, first metal throuth hole is exposed to
Second bonding surface；
The peripheral components layer of second wafer is bonded to second gluing of surfaces.
3. manufacturing method as described in claim 1, which is characterized in that providing the adhesive layer further comprises:
Third substrate is provided；
First interconnection layer and the first metal throuth hole in the adhesive layer are sequentially formed in the upper surface of the third substrate,
First metal throuth hole is exposed to second bonding surface；
Being bonded first wafer, second wafer and the adhesive layer further comprises:
The peripheral components layer of second wafer is bonded to second bonding surface；
The third substrate is removed with first bonding surface of the exposure adhesive layer, first bonding surface is described
The surface of first interconnection layer；
The array layer of first wafer is bonded to first bonding surface.
4. manufacturing method as claimed in claim 2 or claim 3, which is characterized in that the offer third substrate further comprises: in institute
It states third substrate top and forms first medium layer, the adhesive layer is formed in the upper surface of the first medium layer；
The removing third substrate further comprises: being with interface of the first medium layer in the third substrate
Cut third substrate described in interface cut, remove the first medium layer, with the first bonding surface of the exposure adhesive layer or
Second bonding surface.
5. manufacturing method as claimed in claim 4, which is characterized in that third substrate top formed first medium layer into
One step includes:
The processing of note hydrogen is carried out on the surface of the third substrate to form note hydrogen layer, and the first medium layer is the note hydrogen layer.
6. manufacturing method as claimed in claim 4, which is characterized in that third substrate top formed first medium layer into
One step includes:
It carries out porous oxidation on the surface of the third substrate to handle to form porous silica layer, the first medium layer is institute
State porous silica layer.
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