WO2017091155A1 - Tsv embedded thyristor for short discharge path and reduced loading in stacked dies - Google Patents

Tsv embedded thyristor for short discharge path and reduced loading in stacked dies Download PDF

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Publication number
WO2017091155A1
WO2017091155A1 PCT/SG2016/050582 SG2016050582W WO2017091155A1 WO 2017091155 A1 WO2017091155 A1 WO 2017091155A1 SG 2016050582 W SG2016050582 W SG 2016050582W WO 2017091155 A1 WO2017091155 A1 WO 2017091155A1
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Prior art keywords
thyristor
doping regions
adjoining
tsv
accordance
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PCT/SG2016/050582
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French (fr)
Inventor
Ka Fai CHANG
Roshan WEERASEKERA
King Jien Chui
Suryanarayana Shivakumar Bhattacharya
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Agency For Science, Technology And Research
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Publication of WO2017091155A1 publication Critical patent/WO2017091155A1/en

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Definitions

  • the present invention generally relates to thyristor structures and their in- process fabrication, and more particularly relates to through silicon via (TSV) attached thyristor structures for electrostatic discharge (ESD) protection and methods for their fabrication.
  • TSV through silicon via
  • ESD electrostatic discharge
  • Electrostatic discharge (ESD) protection devices are essential to prevent integrated circuit (IC) damage due to high energy, short duration electrostatic charge dissipation through the ICs.
  • Silicon controlled rectifier (SCR) devices also called thyristors
  • SCR Silicon controlled rectifier
  • thyristors are utilized for ESD protection devices due to their low holding voltage and high current density.
  • a shorter discharge path through the ICs leads to faster discharge and therefore lower over-voltage stress to the core circuits. Therefore, regardless of device characteristics, ESD protection devices should be placed as close as possible to core circuits that need ESD protection.
  • low capacitive loading to the core circuits is one of the criteria for selecting ESD protection devices as the core circuit speed will be degraded with additional capacitive loading.
  • TSVs Through silicon vias
  • ESD protection devices can be attached to the TSVs to protect the circuits connected to the associated TSVs.
  • ESD protection devices are fabricated in the vertical space between stacked dies but this procedure requires additional fabrication process steps to build the ESD protection devices.
  • an electrostatic discharge (ESD) protection device includes a thyristor structure having a through silicon via (TSV) formed in one or more first thyristor doping regions of the thyristor structure, wherein the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions.
  • TSV through silicon via
  • a method for fabrication of an electrostatic discharge (ESD) protection device in a silicon substrate includes fabricating a thyristor structure in the silicon substrate and fabricating a through silicon via (TSV) embedded in the thyristor structure.
  • TSV through silicon via
  • a semiconductor junction is formed at an interface of the TSV with the thyristor structure to enable electrostatic discharge through the interface.
  • a stacked semiconductor structure includes a first integrated circuit (IC) device and a second IC device.
  • the first IC device includes a thyristor structure having a TSV formed in one or more first thyristor doping regions of the thyristor structure.
  • the second device is connected to the first IC device in a stacked die arrangement and at least one circuit formed in the second IC device is coupled to one or more circuits formed in the first IC device via the TSV.
  • the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions to provide ESD protection for the one or more circuits formed in the first IC device.
  • FIG. 1 depicts a cross- sectional view of a through silicon via (TSV) embedded thyristor structure in accordance with a present embodiment.
  • An equivalent circuit diagram of the TSV embedded thyristor structure is depicted overlaying the cross-sectional view.
  • FIG. 2 comprising FIGs. 2A to 2K, depicts side planar cross-sectional views of steps in a method for fabrication of the TSV embedded thyristor structure of FIG. 1 in accordance with the present embodiment.
  • TSV through silicon via
  • ESD electrostatic discharge
  • IC stacked integrated circuit
  • the metal semiconductor junctions can be used as the ESD current discharge path, which is the shortest path when compared with external metal routings in a conventional design. Furthermore, the parasitic capacitances at the metal semiconductor junctions are in series with the thyristor so that equivalent capacitance observed at the TSV terminal is reduced. Also, in comparison to a conventional ESD structure, the structure in accordance with the present embodiment significantly saves silicon real estate by implementing the TSV in the doping region of the stacked IC configuration.
  • a cross- sectional view 100 depicts a through silicon via (TSV) embedded thyristor structure formed in an integrated circuit 101 in accordance with a present embodiment.
  • An equivalent circuit diagram 150 of the TSV embedded thyristor structure is depicted overlaying the cross-sectional view.
  • a TSV 102 is fabricated in a lightly doped p type diffusion region 104, a N well region 106 and a p- type silicon substrate 108 of the thyristor structure and is connected to front and back side metal terminals 107, 109.
  • the TSV 102 is electrically isolated from the silicon substrate 108 by surrounding the TSV 102 with an insulator layer 110.
  • the TSV 102 has no electrical insulation with the N well region 106 and the lightly doped p-type diffusion region 104 formed within the N well 106, forming metal semiconductor junctions with them individually.
  • a normal TSV 112 is fully covered by an insulator layer 114 and used to make connection between front and back side metal terminals 116, 118.
  • a conventional thyristor is composed of semiconductor doping regions arranging in a p-n-p-n configuration.
  • the associated p-n-p-n doping regions correspond to the lightly doped p type diffusion region 104 in the N well 106 - the N well 106 - a P well 120 - a heavily doped n type diffusion region 122 in the P well 120, respectively.
  • STI blocks 126 are inserted between adjacent doping regions (e.g., the heavily doped n type diffusion region 122 and the heavily doped p type diffusion region 124 in the P well 120) to suppress current leakage between them.
  • the p-n-p combination of the p type diffusion region 104 in the N well 106, the N well 106, and the P well 120 forms a PNP bipolar transistor Ql 130 with the N well 106 acting as the base.
  • Rl 132 is used to model the N well 106 resistance.
  • NPN bipolar transistor Q2 134 is composed of the N well 106, the P well 120, and the n type diffusion region 122 in the P well 120 while R2 135 corresponds to the P well 120 resistance.
  • the base of each bipolar transistor 130, 134 is equivalently connected to the collector of the other bipolar transistor 134, 130 as they share the same doping regions (e.g., N well 106, P well 120).
  • the thyristor cathode 136 of Q2 134 corresponds to the joint connection of the P well 120 and the n type diffusion region 122 in the P well 120 and is connected to ground 138 in an integrated circuit 139 stacked on the integrated circuit 101.
  • the thyristor anode 140 jointly connects to the N well 106 and the p type diffusion region 104 in the N well 106.
  • the thyristor anode would couple to core circuits in the integrated circuit 139 through the TSV 102 by back end of line (BEOL) or redistribution layer (RDL) metallization layers.
  • BEOL back end of line
  • RDL redistribution layer
  • the TSV 102 is built directly in the doping regions 104, 106 thereby eliminating the need for a metal connection between the TSV 102 and the thyristor anode 140. Instead metal semiconductor junctions are formed at the interface of the TSV 102 with the N well 106 and the p type diffusion region 104 in the N well 106, respectively. These metal semiconductor junctions 142, 144 behave like schottky diodes Dl, D2 which have low forward bias voltage drop and very fast switching characteristics.
  • a passivation layer 145, the metallization pads 109, 118 and solder bumps 146, 148 are added to the first integrated (IC) device 139 so that the first IC device 139 can be stacked on a second IC device 160 in a stacked semiconductor die arrangement with the thyristor-embedded TSV 102 coupling one or more circuits in the first IC device 139 to at least one circuit in the second IC device 160.
  • the electrical connection between the TSV 102 and the thyristor anode 140 is realized by the metal semiconductor junctions 142, 144 longitudinally inside the thyristor structure, thereby providing a discharge path therethrough which is the shortest path to discharge ESD current directly to the thyristor.
  • the schottky diodes 142, 144 and the thyristor are connected in series.
  • the parasitic capacitance when looking at the TSV terminal is, therefore, less than the thyristor parasitic capacitance. Since the parasitic capacitive loading is reduced, the core circuit performance is advantageously improved
  • FIG. 2 comprising FIGs. 2A to 2K, a method for fabrication of TSV formation in the thyristor structure on the device wafer to form the TSV embedded thyristor in accordance with the present embodiment is depicted.
  • the fabrication process flow of TSV formation in the thyristor in accordance with the present embodiment is demonstrated in FIGs. 2A to 2K which depict fabrication steps that are processed at the back side of device wafers having the thyristor formed therein. Additional steps are included so that TSVs formed in the thyristors are partially covered with an insulator to be electrically isolated only from the silicon substrate while other TSVs not formed in thyristors are fully covered with an insulator in a conventional manner.
  • a side planar cross-sectional view 200 depicts a p-n-p- n thyristor structure 202 fabricated in a p type silicon substrate 204. For simplicity, only metal 1 (Ml) formed on the silicon substrate 204 is shown.
  • Ml metal 1
  • the heavily doped p type diffusion region 124 and the n type diffusion region 122 in the P well 120 is joined by a Ml 206 through ohmic contacts 208, 210 while the Ml metallization layer 107 on top of the lightly doped p type diffusion region 104 in the N well 106 is floating, i.e., the Ml metallization layer 107 has no electrical connection with any underneath doping regions including the N well 106 and the p type diffusion region 104.
  • the device wafer may need to be attached to a temporary carrier on its front side (the top side in the view 200) for wafer handling. All remaining processes demonstrated in FIG. 2 are implemented on the back side of the device wafer, and the temporary carrier is not shown in the views of FIGs. 2A to 2K.
  • a side planar view 214 depicts vias 216, 218 formed through the silicon substrate 204 by a TSV etch process applied from the back side of the device wafer until the Ml layer is exposed at an end of the vias 216, 218 for electrical connection.
  • the via 216 is also formed through the N well 106 and the p type diffusion region 104.
  • the vias 216, 218 are then filled with copper to form the TSVs 102, 112 and their electrical connections with Ml (i.e., the metallization layers 107, 116) are formed.
  • Ml i.e., the metallization layers 107, 116
  • a side planar view 224 depicts a second TSV etch process performed from the back side of the device wafer through a photoresist layer 226 having an opening 228 which permits only etching in the substrate surrounding the TSV 102.
  • the material in the silicon substrate around the TSV 102 is etched away to break the electrical connection between the TSV 102 and the silicon substrate 204.
  • the etch depth is controlled to only etch the silicon substrate 204 to the bottom of the N well 106. Over etching partially into the N well 106 can also be performed in accordance with the present embodiment. It is important that the metal semiconductor junctions between the TSV 102 and the two individual doping regions 104, 106 should remain.
  • a third TSV etch process applied from the back side of the device wafer is depicted in a side planar view 230 of FIG. 2E.
  • a photoresist layer 232 with an opening 234 allows etching the silicon substrate 204 around the TSV 112 to electrically isolate it from the silicon substrate 204 entirely. Note that the TSV 102 embedded in the thyristor is covered by the photoresist layer 232, preventing further etching.
  • FIGs. 2F to 2K Three different ways to form an electrical insulation layer between the TSVs 102, 112 and the silicon substrate 204 in accordance with variants of the present embodiment are depicted in FIGs. 2F to 2K.
  • the etched hollow rings in the silicon substrate 204 around the TSVs 102, 112 shown in FIG. 2E can be filled completely with silicon oxide 250 as shown in FIGs. 2F and 2G or filled completely with polymer 260 as shown in FIGs. 2H and 21.
  • the etched hollow rings in the silicon substrate 204 around the TSVs 102, 112 can be partially sealed with silicon oxide 270 at the bottom of the silicon substrate 204, leaving an air cavity 272 inside for electrical insulation as shown in FIGs. 2J and 2K.
  • Either an etch-back process or a chemical mechanical polishing (CMP) process can then be performed to expose the TSVs 102, 112 at the device wafer back side for electrical connection.
  • CMP chemical mechanical polishing
  • the back side passivation formation of a passivation layer 280
  • bumping formation of pads 282 and solder bumps 284 in the passivation layer 280
  • RDL redistribution layer
  • the resulting TSV embedded thyristor fabricated in accordance with FIG. 2 provides a short discharge path for ESD events (i.e., discharge through the metal semiconductor junctions at the interface of the embedded TSVs 102 in the thyristor structure) and capacitive loading reduction (due to series connection of the schottky diode and the thyristor). It is applicable for ESD protection for high speed input/output (I/O) buffers in three-dimensional integrated circuit (3D IC) stacks.
  • ESD events i.e., discharge through the metal semiconductor junctions at the interface of the embedded TSVs 102 in the thyristor structure
  • capacitive loading reduction due to series connection of the schottky diode and the thyristor
  • the thyristor can be fabricated in accordance with the present embodiment with other active devices in the same die during the foundry front end of line (FEOL) process, no extra fabrication steps are needed in implanting the doping regions 104, 106, 120, 122, 124 in the thyristor structure.
  • ESD protection devices are fabricated in a second active layer while the circuit devices needed for protection are built in a first active layer with TSVs, thus disadvantageously requiring extra fabrication steps to form the ESD protection devices.
  • the circuit devices experience ESD stresses before ESD protection devices can be activated due to delay through the TSVs.
  • the TSV is located inside the thyristor and, thus, ESD stresses will advantageously discharge first before reaching the circuit devices.
  • the present embodiment provides a TSV embedded thyristor structures for ESD protection and a highly scalable fabrication methods for fabricating such TSV embedded thyristor ESD protection structures in 2.5D/3D IC die stacks without requiring extra fabrication steps.
  • the TSV is advantageously built inside the thyristor so that the combined device can be used for both signal transmission and ESD protection.
  • the ESD discharge path is located in the thyristor through the metal semiconductor junctions at the interface between the TSV and doping regions in the thyristor.
  • the TSV/thyristor combination design in accordance with the present embodiment advantageously offers the most direct, shortest discharge path without external interconnections.

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Abstract

An electrostatic discharge (ESD) protection device, a method for fabrication of an ESD protection device in a silicon substrate, and a stacked semiconductor structure are provided. The ESD protection device includes a thyristor structure having a through silicon via (TSV) formed in one or more first thyristor doping regions of the thyristor structure, wherein the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions. The stacked semiconductor structure includes a first integrated circuit (IC) device and a second IC device, the first IC device including a thyristor structure having a TSV formed in one or more first thyristor doping regions of the thyristor structure. The second device is connected to the first IC device in a stacked die arrangement and at least one circuit formed in the second IC device is coupled to one or more circuits formed in the first IC device via the TSV.

Description

TSV EMBEDDED THYRISTOR FOR SHORT DISCHARGE PATH AND REDUCED LOADING IN STACKED DIES
PRIORITY CLAIM
[0001] This application claims priority from Singapore Patent Application No. 10201509754P filed on 26 November 2015.
TECHNICAL FIELD
[0002] The present invention generally relates to thyristor structures and their in- process fabrication, and more particularly relates to through silicon via (TSV) attached thyristor structures for electrostatic discharge (ESD) protection and methods for their fabrication.
BACKGROUND OF THE DISCLOSURE
[0003] Electrostatic discharge (ESD) protection devices are essential to prevent integrated circuit (IC) damage due to high energy, short duration electrostatic charge dissipation through the ICs. Silicon controlled rectifier (SCR) devices (also called thyristors) are utilized for ESD protection devices due to their low holding voltage and high current density. A shorter discharge path through the ICs leads to faster discharge and therefore lower over-voltage stress to the core circuits. Therefore, regardless of device characteristics, ESD protection devices should be placed as close as possible to core circuits that need ESD protection. Furthermore, low capacitive loading to the core circuits is one of the criteria for selecting ESD protection devices as the core circuit speed will be degraded with additional capacitive loading. [0004] In stacked ICs, 2.5D/3D integrated circuits provide a new degree of freedom to arrange the circuit blocks with different functionality, thereby improving the system performance. Through silicon vias (TSVs) are used to make connection between different dies in the IC die stacks. ESD protection devices can be attached to the TSVs to protect the circuits connected to the associated TSVs. In accordance with one conventional procedure, ESD protection devices are fabricated in the vertical space between stacked dies but this procedure requires additional fabrication process steps to build the ESD protection devices.
[0005] Thus, what is needed are TSV attached thyristor structures for ESD protection and highly scalable fabrication methods for fabricating such TSV attached thyristor ESD protection structures in 2.5D/3D IC die stacks without requiring extra fabrication steps. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.
SUMMARY
[0006] According to at least one embodiment of the present invention, an electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a thyristor structure having a through silicon via (TSV) formed in one or more first thyristor doping regions of the thyristor structure, wherein the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions.
[0007] According to another embodiment of the present invention, a method for fabrication of an electrostatic discharge (ESD) protection device in a silicon substrate is provided. The method includes fabricating a thyristor structure in the silicon substrate and fabricating a through silicon via (TSV) embedded in the thyristor structure. A semiconductor junction is formed at an interface of the TSV with the thyristor structure to enable electrostatic discharge through the interface.
[0008] According to a further embodiment of the present invention a stacked semiconductor structure is provided. The stacked semiconductor structure includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a thyristor structure having a TSV formed in one or more first thyristor doping regions of the thyristor structure. The second device is connected to the first IC device in a stacked die arrangement and at least one circuit formed in the second IC device is coupled to one or more circuits formed in the first IC device via the TSV. The thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions to provide ESD protection for the one or more circuits formed in the first IC device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to illustrate various embodiments and to explain various principles and advantages in accordance with a present embodiment.
[0010] FIG. 1 depicts a cross- sectional view of a through silicon via (TSV) embedded thyristor structure in accordance with a present embodiment. An equivalent circuit diagram of the TSV embedded thyristor structure is depicted overlaying the cross-sectional view. [0011] And FIG. 2, comprising FIGs. 2A to 2K, depicts side planar cross-sectional views of steps in a method for fabrication of the TSV embedded thyristor structure of FIG. 1 in accordance with the present embodiment.
[0012] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been depicted to scale.
DETAILED DESCRIPTION
[0013] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. It is the intent of the present embodiment to present a through silicon via (TSV) embedded thyristor structure for electrostatic discharge (ESD) protection in a stacked integrated circuit (IC) configuration. Preferably, the TSV is built inside the thyristor in accordance with a present embodiment and metal semiconductor junctions are formed at the interface between the TSV and the doping regions inside the thyristor. The metal semiconductor junctions can be used as the ESD current discharge path, which is the shortest path when compared with external metal routings in a conventional design. Furthermore, the parasitic capacitances at the metal semiconductor junctions are in series with the thyristor so that equivalent capacitance observed at the TSV terminal is reduced. Also, in comparison to a conventional ESD structure, the structure in accordance with the present embodiment significantly saves silicon real estate by implementing the TSV in the doping region of the stacked IC configuration.
[0014] Referring to FIG. 1, a cross- sectional view 100 depicts a through silicon via (TSV) embedded thyristor structure formed in an integrated circuit 101 in accordance with a present embodiment. An equivalent circuit diagram 150 of the TSV embedded thyristor structure is depicted overlaying the cross-sectional view. A TSV 102 is fabricated in a lightly doped p type diffusion region 104, a N well region 106 and a p- type silicon substrate 108 of the thyristor structure and is connected to front and back side metal terminals 107, 109. The TSV 102 is electrically isolated from the silicon substrate 108 by surrounding the TSV 102 with an insulator layer 110. In this manner, the TSV 102 has no electrical insulation with the N well region 106 and the lightly doped p-type diffusion region 104 formed within the N well 106, forming metal semiconductor junctions with them individually. In contradistinction, a normal TSV 112 is fully covered by an insulator layer 114 and used to make connection between front and back side metal terminals 116, 118.
[0015] A conventional thyristor is composed of semiconductor doping regions arranging in a p-n-p-n configuration. In accordance with the present embodiment, the associated p-n-p-n doping regions correspond to the lightly doped p type diffusion region 104 in the N well 106 - the N well 106 - a P well 120 - a heavily doped n type diffusion region 122 in the P well 120, respectively. There is also a heavily doped p type diffusion region 124 in the P well 120, which is used to make electrical ohmic connection with the P well 120. STI blocks 126 are inserted between adjacent doping regions (e.g., the heavily doped n type diffusion region 122 and the heavily doped p type diffusion region 124 in the P well 120) to suppress current leakage between them. The p-n-p combination of the p type diffusion region 104 in the N well 106, the N well 106, and the P well 120 forms a PNP bipolar transistor Ql 130 with the N well 106 acting as the base. Rl 132 is used to model the N well 106 resistance. Furthermore, NPN bipolar transistor Q2 134 is composed of the N well 106, the P well 120, and the n type diffusion region 122 in the P well 120 while R2 135 corresponds to the P well 120 resistance. The base of each bipolar transistor 130, 134 is equivalently connected to the collector of the other bipolar transistor 134, 130 as they share the same doping regions (e.g., N well 106, P well 120).
[0016] The thyristor cathode 136 of Q2 134 corresponds to the joint connection of the P well 120 and the n type diffusion region 122 in the P well 120 and is connected to ground 138 in an integrated circuit 139 stacked on the integrated circuit 101. On the other hand, the thyristor anode 140 jointly connects to the N well 106 and the p type diffusion region 104 in the N well 106. Conventionally, the thyristor anode would couple to core circuits in the integrated circuit 139 through the TSV 102 by back end of line (BEOL) or redistribution layer (RDL) metallization layers. However, in accordance with the present embodiment, the TSV 102 is built directly in the doping regions 104, 106 thereby eliminating the need for a metal connection between the TSV 102 and the thyristor anode 140. Instead metal semiconductor junctions are formed at the interface of the TSV 102 with the N well 106 and the p type diffusion region 104 in the N well 106, respectively. These metal semiconductor junctions 142, 144 behave like schottky diodes Dl, D2 which have low forward bias voltage drop and very fast switching characteristics.
[0017] A passivation layer 145, the metallization pads 109, 118 and solder bumps 146, 148 are added to the first integrated (IC) device 139 so that the first IC device 139 can be stacked on a second IC device 160 in a stacked semiconductor die arrangement with the thyristor-embedded TSV 102 coupling one or more circuits in the first IC device 139 to at least one circuit in the second IC device 160.
[0018] Unlike using metallization structures or metal wires to connect externally, the electrical connection between the TSV 102 and the thyristor anode 140 is realized by the metal semiconductor junctions 142, 144 longitudinally inside the thyristor structure, thereby providing a discharge path therethrough which is the shortest path to discharge ESD current directly to the thyristor. Additionally, the schottky diodes 142, 144 and the thyristor are connected in series. Thus, when the thyristor is not activated, its parasitic capacitance is in series with the schottky diode capacitance. The equivalent capacitance when looking at the TSV terminal is, therefore, less than the thyristor parasitic capacitance. Since the parasitic capacitive loading is reduced, the core circuit performance is advantageously improved
[0019] Referring to FIG. 2, comprising FIGs. 2A to 2K, a method for fabrication of TSV formation in the thyristor structure on the device wafer to form the TSV embedded thyristor in accordance with the present embodiment is depicted. The fabrication process flow of TSV formation in the thyristor in accordance with the present embodiment is demonstrated in FIGs. 2A to 2K which depict fabrication steps that are processed at the back side of device wafers having the thyristor formed therein. Additional steps are included so that TSVs formed in the thyristors are partially covered with an insulator to be electrically isolated only from the silicon substrate while other TSVs not formed in thyristors are fully covered with an insulator in a conventional manner.
[0020] Referring to FIG. 2A, a side planar cross-sectional view 200 depicts a p-n-p- n thyristor structure 202 fabricated in a p type silicon substrate 204. For simplicity, only metal 1 (Ml) formed on the silicon substrate 204 is shown. The heavily doped p type diffusion region 124 and the n type diffusion region 122 in the P well 120 is joined by a Ml 206 through ohmic contacts 208, 210 while the Ml metallization layer 107 on top of the lightly doped p type diffusion region 104 in the N well 106 is floating, i.e., the Ml metallization layer 107 has no electrical connection with any underneath doping regions including the N well 106 and the p type diffusion region 104.
[0021] Depending on wafer thickness, the device wafer may need to be attached to a temporary carrier on its front side (the top side in the view 200) for wafer handling. All remaining processes demonstrated in FIG. 2 are implemented on the back side of the device wafer, and the temporary carrier is not shown in the views of FIGs. 2A to 2K.
[0022] In FIG. 2B, a side planar view 214 depicts vias 216, 218 formed through the silicon substrate 204 by a TSV etch process applied from the back side of the device wafer until the Ml layer is exposed at an end of the vias 216, 218 for electrical connection. The via 216 is also formed through the N well 106 and the p type diffusion region 104.
[0023] Referring to a side planar view 220 of the next step (FIG. 2C), the vias 216, 218 are then filled with copper to form the TSVs 102, 112 and their electrical connections with Ml (i.e., the metallization layers 107, 116) are formed. Note that there is no insulation material deposited at the interface of the TSVs 102, 112 and the silicon substrate 204. In addition, there is no insulation material deposited at the interface of the TSV 102 and the doping regions (i.e., the N well 106 and the p type diffusion region 104), thereby forming metal semiconductor junctions between the TSV 102 and the doping regions 104, 106.
[0024] In FIG. 2D, a side planar view 224 depicts a second TSV etch process performed from the back side of the device wafer through a photoresist layer 226 having an opening 228 which permits only etching in the substrate surrounding the TSV 102. The material in the silicon substrate around the TSV 102 is etched away to break the electrical connection between the TSV 102 and the silicon substrate 204. The etch depth is controlled to only etch the silicon substrate 204 to the bottom of the N well 106. Over etching partially into the N well 106 can also be performed in accordance with the present embodiment. It is important that the metal semiconductor junctions between the TSV 102 and the two individual doping regions 104, 106 should remain.
[0025] A third TSV etch process applied from the back side of the device wafer is depicted in a side planar view 230 of FIG. 2E. A photoresist layer 232 with an opening 234 allows etching the silicon substrate 204 around the TSV 112 to electrically isolate it from the silicon substrate 204 entirely. Note that the TSV 102 embedded in the thyristor is covered by the photoresist layer 232, preventing further etching.
[0026] Three different ways to form an electrical insulation layer between the TSVs 102, 112 and the silicon substrate 204 in accordance with variants of the present embodiment are depicted in FIGs. 2F to 2K. The etched hollow rings in the silicon substrate 204 around the TSVs 102, 112 shown in FIG. 2E can be filled completely with silicon oxide 250 as shown in FIGs. 2F and 2G or filled completely with polymer 260 as shown in FIGs. 2H and 21. Alternatively, the etched hollow rings in the silicon substrate 204 around the TSVs 102, 112 can be partially sealed with silicon oxide 270 at the bottom of the silicon substrate 204, leaving an air cavity 272 inside for electrical insulation as shown in FIGs. 2J and 2K. Either an etch-back process or a chemical mechanical polishing (CMP) process can then be performed to expose the TSVs 102, 112 at the device wafer back side for electrical connection. Afterwards, as shown in FIGs. 2G, 21 and 2K, the back side passivation (formation of a passivation layer 280) and bumping (formation of pads 282 and solder bumps 284 in the passivation layer 280) can be performed so that the device can be stacked on other die. There is also an option to include one or more redistribution layer(s) (RDL(s)) at the back side of the device wafer for routing and/or pad reassignment.
[0027] The resulting TSV embedded thyristor fabricated in accordance with FIG. 2 provides a short discharge path for ESD events (i.e., discharge through the metal semiconductor junctions at the interface of the embedded TSVs 102 in the thyristor structure) and capacitive loading reduction (due to series connection of the schottky diode and the thyristor). It is applicable for ESD protection for high speed input/output (I/O) buffers in three-dimensional integrated circuit (3D IC) stacks.
[0028] As the thyristor can be fabricated in accordance with the present embodiment with other active devices in the same die during the foundry front end of line (FEOL) process, no extra fabrication steps are needed in implanting the doping regions 104, 106, 120, 122, 124 in the thyristor structure. Conventionally, ESD protection devices are fabricated in a second active layer while the circuit devices needed for protection are built in a first active layer with TSVs, thus disadvantageously requiring extra fabrication steps to form the ESD protection devices.
[0029] In addition to extra fabrication steps to form ESD protection devices, the circuit devices experience ESD stresses before ESD protection devices can be activated due to delay through the TSVs. In accordance with the present embodiment, the TSV is located inside the thyristor and, thus, ESD stresses will advantageously discharge first before reaching the circuit devices.
[0030] Thus, it can be seen that the present embodiment provides a TSV embedded thyristor structures for ESD protection and a highly scalable fabrication methods for fabricating such TSV embedded thyristor ESD protection structures in 2.5D/3D IC die stacks without requiring extra fabrication steps. The TSV is advantageously built inside the thyristor so that the combined device can be used for both signal transmission and ESD protection. The ESD discharge path is located in the thyristor through the metal semiconductor junctions at the interface between the TSV and doping regions in the thyristor. Compared with conventional ESD protection devices that require additional interconnects to connect the TSV and the ESD protection devices for discharge, the TSV/thyristor combination design in accordance with the present embodiment advantageously offers the most direct, shortest discharge path without external interconnections.
[0031] While exemplary embodiments have been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should further be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, operation, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of steps and method of operation described in the exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.

Claims

CLAIMS What is claimed is:
1. An electrostatic discharge (ESD) protection device comprising a thyristor structure having a through silicon via (TSV) formed in one or more first thyristor doping regions of the thyristor structure, wherein the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions.
2. The ESD protection device in accordance with Claim 1 wherein the one or more first thyristor doping regions comprise at least two adjoining thyristor doping regions of opposite polarities.
3. The ESD protection device in accordance with Claim 2 wherein one of the at least two adjoining thyristor doping regions of opposite polarities comprises a doped well.
4. The ESD protection device in accordance with Claim 3 wherein another one of the at least two adjoining thyristor doping regions of opposite polarities comprises a doped diffusion region formed within the doped well.
5. The ESD protection device in accordance with Claim 2 wherein one of the at least two adjoining thyristor doping regions of opposite polarities comprises a doped diffusion region.
6. The ESD protection device in accordance with Claim 1 wherein the thyristor structure further comprises one or more second thyristor doping regions connected to at least one of the one or more first thyristor doping regions.
7. The ESD protection device in accordance with Claim 6 wherein the one or more first thyristor doping regions comprise two adjoining first thyristor doping regions of opposite polarities, and wherein the one or more second thyristor doping regions also comprise two adjoining second thyristor doping regions of opposite polarities, and wherein one of the two adjoining first thyristor doping regions connects to one of the two adjoining second thyristor doping regions, the one of the two adjoining first thyristor doping regions having a polarity opposite to a polarity of the one of the two adjoining second thyristor doping regions.
8. The ESD protection device in accordance with Claim 7 wherein the one of the two adjoining first thyristor doping regions comprises a first doped well, and wherein the one of the two adjoining second thyristor doping regions comprises a second doped well, and wherein the first and second doped wells have opposite polarities.
9. The ESD protection device in accordance with Claim 1 wherein the TS V and the metal semiconductor junctions provide an ESD current discharge path to a ground connection of the thyristor structure.
10. The ESD protection device in accordance with Claim 2 wherein parasitic capacitances at connections between the metal semiconductor junctions and the at least two adjoining thyristor doping regions of opposite polarities provide equivalent capacitance reduction at a terminal of the TSV.
11. A method for fabrication of an electrostatic discharge (ESD) protection device in a silicon substrate, the method comprising:
fabricating a thyristor structure in the silicon substrate; and
fabricating a through silicon via (TSV) embedded in the thyristor structure, wherein a semiconductor junction formed at an interface of the TSV with the thyristor structure enables electrostatic discharge therethrough.
12. The method in accordance with Claim 11 wherein the step of fabricating the thyristor structure comprises fabricating the thyristor structure by forming at least two adjoining thyristor doping regions of opposite polarities in the silicon substrate, and wherein the step of fabricating the TSV comprises fabricating the TSV through the at least two adjoining thyristor doping regions of opposite polarities.
13. The method in accordance with Claim 12 wherein the step of forming the at least two adjoining thyristor doping regions of opposite polarities comprises: forming a doped well in the silicon substrate of a first polarity; and
forming a diffusion region of a second polarity in the doped well, the second polarity opposite to the first polarity, and wherein the step of fabricating the TSV comprises fabricating the TSV through the doped well and the diffusion region.
14. A stacked semiconductor structure comprising: a first integrated circuit (IC) device comprising a thyristor structure having a through silicon via (TSV) formed in one or more first thyristor doping regions of the thyristor structure; and
a second IC device connected to the first IC device in a stacked die arrangement, wherein at least one circuit formed in the second IC device is coupled to one or more circuits formed in the first IC device via the TSV, and
wherein the thyristor structure includes metal semiconductor junctions formed at an interface between the TSV and each of the one or more first thyristor doping regions to provide electrostatic discharge (ESD) protection for the one or more circuits formed in the first IC device.
15. The stacked semiconductor structure in accordance with Claim 14 wherein the one or more first thyristor doping regions in the first IC device comprise at least two adjoining thyristor doping regions of opposite polarities.
16. The stacked semiconductor structure in accordance with Claim 15 wherein the at least two adjoining thyristor doping regions of opposite polarities in the first IC device comprise a doped well and a doped diffusion region formed within the doped well.
17. The stacked semiconductor structure in accordance with Claim 14 wherein the thyristor structure in the first IC device further comprises one or more second thyristor doping regions connected to at least one of the one or more first thyristor doping regions.
18. The stacked semiconductor structure in accordance with Claim 17 wherein the one or more first thyristor doping regions in the first IC device comprise two adjoining first thyristor doping regions of opposite polarities, and wherein the one or more second thyristor doping regions in the first IC device also comprise two adjoining second thyristor doping regions of opposite polarities, and wherein one of the two adjoining first thyristor doping regions connects to one of the two adjoining second thyristor doping regions, the one of the two adjoining first thyristor doping regions having a polarity opposite to a polarity of the one of the two adjoining second thyristor doping regions.
19. The stacked semiconductor structure in accordance with Claim 18 wherein the one of the two adjoining first thyristor doping regions in the first IC device comprises a first doped well, and wherein the one of the two adjoining second thyristor doping regions in the first IC device comprises a second doped well, and wherein the first and second doped wells have opposite polarities.
20. The stacked semiconductor structure in accordance with Claim 15 wherein parasitic capacitances at connections between the metal semiconductor junctions and the at least two adjoining thyristor doping regions of opposite polarities provide equivalent capacitance reduction at a terminal of the TSV in the first IC device.
PCT/SG2016/050582 2015-11-26 2016-11-25 Tsv embedded thyristor for short discharge path and reduced loading in stacked dies WO2017091155A1 (en)

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CN108109953A (en) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 For the TSV pinboards of system in package
WO2020097859A1 (en) * 2018-11-15 2020-05-22 华为技术有限公司 Integrated circuit
WO2022101473A1 (en) 2020-11-16 2022-05-19 Tdk Electronics Ag Silicon substrate with esd protection element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010108812A1 (en) * 2009-03-26 2010-09-30 International Business Machines Corporation Esd network circuit with a through wafer via structure and a method of manufacture
US20130083436A1 (en) * 2011-10-04 2013-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010108812A1 (en) * 2009-03-26 2010-09-30 International Business Machines Corporation Esd network circuit with a through wafer via structure and a method of manufacture
US20130083436A1 (en) * 2011-10-04 2013-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ENGIN A. E. ET AL.: "Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design.", IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC, 2 February 2011 (2011-02-02), pages 1 - 4, XP032235115, [retrieved on 20170113] *
KANG C. Y. ET AL.: "A Systematic Study of I/O Device Designs for TSV-based 3D Chip Stacking.", INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA, 27 April 2011 (2011-04-27), pages 1 - 2, XP031944096, [retrieved on 20170113] *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108109953A (en) * 2017-12-15 2018-06-01 西安科锐盛创新科技有限公司 For the TSV pinboards of system in package
CN108109953B (en) * 2017-12-15 2020-12-25 浙江清华柔性电子技术研究院 TSV adapter plate for system-in-package
WO2020097859A1 (en) * 2018-11-15 2020-05-22 华为技术有限公司 Integrated circuit
CN112020773A (en) * 2018-11-15 2020-12-01 华为技术有限公司 Integrated circuit
CN112020773B (en) * 2018-11-15 2023-09-08 华为技术有限公司 Integrated circuit
US11798934B2 (en) 2018-11-15 2023-10-24 Huawei Technologies Co., Ltd. Integrated circuit including ESD protection modules
WO2022101473A1 (en) 2020-11-16 2022-05-19 Tdk Electronics Ag Silicon substrate with esd protection element

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