KR101743864B1 - Vertical type cmos inverter device - Google Patents
Vertical type cmos inverter device Download PDFInfo
- Publication number
- KR101743864B1 KR101743864B1 KR1020160005678A KR20160005678A KR101743864B1 KR 101743864 B1 KR101743864 B1 KR 101743864B1 KR 1020160005678 A KR1020160005678 A KR 1020160005678A KR 20160005678 A KR20160005678 A KR 20160005678A KR 101743864 B1 KR101743864 B1 KR 101743864B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- layer
- gate
- polarity
- cmos inverter
- Prior art date
Links
- 239000002184 metal Substances 0.000 claims abstract description 132
- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000012535 impurity Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 101100170933 Arabidopsis thaliana DMT1 gene Proteins 0.000 description 28
- 101100170942 Arabidopsis thaliana MET4 gene Proteins 0.000 description 28
- 101150014095 MET2 gene Proteins 0.000 description 28
- 101100261242 Mus musculus Trdmt1 gene Proteins 0.000 description 28
- 101150043924 metXA gene Proteins 0.000 description 28
- 102100022087 Granzyme M Human genes 0.000 description 16
- 101000900697 Homo sapiens Granzyme M Proteins 0.000 description 16
- 101100186980 Arabidopsis thaliana NGA1 gene Proteins 0.000 description 10
- 101150068888 MET3 gene Proteins 0.000 description 9
- 101100022915 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) cys-11 gene Proteins 0.000 description 9
- 101100022918 Schizosaccharomyces pombe (strain 972 / ATCC 24843) sua1 gene Proteins 0.000 description 9
- 101100096958 Arabidopsis thaliana GPL1 gene Proteins 0.000 description 8
- 101100186981 Arabidopsis thaliana NGA2 gene Proteins 0.000 description 8
- PZOHPVWRSNXCRP-QRCCJXOFSA-N GPL-1 Chemical compound C([C@@H](NC(=O)CC(O)CCCCCCCCCCCCCCCCCCCCCCCCCCCCC)C(=O)N[C@H]([C@@H](C)OC1[C@@H]([C@H](O)[C@H](O)[C@H](C)O1)O[C@H]1[C@@H]([C@H](O)[C@@H](O)[C@H](C)O1)O)C(=O)N[C@H](C)C(=O)N[C@@H](C)COC1[C@@H]([C@H](OC)[C@@H](OC)[C@H](C)O1)O)C1=CC=CC=C1 PZOHPVWRSNXCRP-QRCCJXOFSA-N 0.000 description 8
- 102100026679 Carboxypeptidase Q Human genes 0.000 description 7
- 101100166333 Homo sapiens CPQ gene Proteins 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 101150072399 LSC1 gene Proteins 0.000 description 6
- 101100367016 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) LSC2 gene Proteins 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 208000020174 Autosomal recessive cutis laxa type 2 Diseases 0.000 description 1
- 102100040399 C->U-editing enzyme APOBEC-2 Human genes 0.000 description 1
- 101000964322 Homo sapiens C->U-editing enzyme APOBEC-2 Proteins 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
A vertical CMOS inverter device is published. The vertical CMOS inverter device of the present invention includes a first metal layer; A second metal layer formed on the first metal layer and having an input terminal and an output terminal patterned; A third metal layer formed on the second metal layer; A first gate poly layer formed between the first metal layer and the second metal layer, the first gate poly layer being patterned with a first gate terminal; A first semiconductor layer formed on a side surface of the first gate terminal and having a first metal layer and an output terminal electrically connected to the output terminal of the second metal layer in accordance with a level of a voltage applied to an input terminal of the second metal layer, The first semiconductor layer being driven; A second gate poly layer formed between the second metal layer and the third metal layer and having a second gate terminal patterned; And a second semiconductor layer formed on a side surface of the second gate terminal between the second metal layer and the third metal layer, wherein the second metal layer has a second metal layer, Layer and the second semiconductor layer driven to electrically conduct the third metal layer. In the vertical CMOS inverter device of the present invention as described above, the respective components are vertically stacked. Thus, according to the vertical CMOS inverter device of the present invention, the required layout area is remarkably reduced. Also, since the connection length of the components is shortened, the delay due to the connection is minimized, and high-speed operation is enabled.
Description
The present invention relates to a semiconductor circuit device, and more particularly, to a CMOS inverter device.
The semiconductor chip is formed to include various kinds of semiconductor circuit elements, among which a large number of CMOS inverter elements are formed. These CMOS inverter devices are generally formed across the surface of the semiconductor substrate in the horizontal direction.
However, the CMOS inverter device formed in the horizontal direction requires a large layout area, and the connection line of the signals becomes long, so that a delay occurs in the signal transmission. As a result, the size of the semiconductor chip becomes large and it becomes difficult to develop a high-speed circuit.
Therefore, it is required to develop a CMOS inverter device that reduces the required layout area and shortens the connection length between circuits as much as possible to enable high-speed operation.
SUMMARY OF THE INVENTION The present invention has been made in view of the above needs, and an object of the present invention is to provide a vertical CMOS inverter device capable of reducing a required layout area and enabling high-speed operation.
According to an aspect of the present invention, there is provided a vertical CMOS inverter device. A vertical CMOS inverter device of the present invention includes: a first metal layer formed on a semiconductor substrate and supplying a first supply voltage; A second metal layer formed on the first metal layer and having an input terminal and an output terminal patterned; A third metal layer formed on the second metal layer and supplying a second supply voltage; A first gate poly layer formed between the first metal layer and the second metal layer and patterned with a first gate terminal, the first gate terminal electrically connected to the input terminal of the second metal layer, The first gate poly layer being electrically insulated from output terminals of the first metal layer and the second metal layer; The first metal layer is formed on a side of the first gate terminal between the first metal layer and the second metal layer. The first metal layer is formed on the first metal layer, The first semiconductor layer being driven to conduct the output terminal of the second metal layer; A second gate poly layer formed between the second metal layer and the third metal layer and having a second gate terminal patterned thereon, the second gate terminal electrically connected to the input terminal of the second metal layer The second gate poly layer being electrically insulated from the output terminal of the second metal layer and the third metal layer; And a second semiconductor layer formed on a side surface of the second gate terminal between the second metal layer and the third metal layer, wherein the second metal layer has a second metal layer, Layer and the second semiconductor layer driven to electrically conduct the third metal layer.
In the vertical CMOS inverter device of the present invention as described above, the respective components are vertically stacked. Thus, according to the vertical CMOS inverter device of the present invention, the required layout area is remarkably reduced. Also, since the connection length of the components is shortened, the delay due to the connection is minimized, and high-speed operation is enabled.
A brief description of each drawing used in the present invention is provided.
1 is a cross-sectional view illustrating a vertical CMOS inverter device according to an embodiment of the present invention.
Figs. 2A and 2B are diagrams showing an equivalent circuit of the vertical CMOS inverter device of Fig. 1. Fig.
3 is a flowchart for explaining a method of manufacturing the vertical CMOS inverter device of FIG.
FIGS. 4 to 10 are cross-sectional views showing cross sections at respective steps according to the manufacturing method of FIG.
For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.
It should be noted that, in understanding each of the drawings, the same members are denoted by the same reference numerals whenever possible. Further, detailed descriptions of known functions and configurations that may be unnecessarily obscured by the gist of the present invention are omitted.
On the other hand, in order to clearly illustrate the layers (or films) and regions in the drawings, the thickness is enlarged. It is to be understood that when an element or layer is referred to as being "on" another part, it is understood that the term "layer", "film" . Conversely, when a part is referred to as being "directly on" another part, it means that there is no other part in the middle.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(Vertical type Seamos Of the inverter device Example )
1 is a cross-sectional view illustrating a vertical CMOS inverter device according to an embodiment of the present invention. Referring to FIG. 1, the vertical CMOS inverter device of the present invention includes a first metal layer MET1, a second metal layer MET2, a third metal layer MET3, a first gate poly layer GPL1, (FCD1), a second gate poly layer (GPL2), and a second semiconductor layer (FCD2).
The first metal layer MET1 is formed on the semiconductor substrate SUB and supplies the first supply voltage VPW1.
The second metal layer MET2 is formed on the first metal layer MET1, and the input terminal NIN and the output terminal NUT are patterned.
The third metal layer MET3 is formed on the second metal layer MET2 and supplies the second supply voltage VPW2.
The first gate poly layer GPL1 is formed between the first metal layer MET1 and the second metal layer MET2 and the first gate terminal NGA1 is patterned. At this time, the first gate terminal NGA1 is electrically connected to the input terminal NIN of the second metal layer MET2, and the output of the first metal layer MET1 and the output of the second metal layer MET2 And is electrically insulated from the terminal (NUT).
The first semiconductor layer FCD1 is formed on a side surface of the first gate terminal NGA1 between the first metal layer MET1 and the second metal layer MET2. At this time, the first semiconductor layer FCD1 is electrically connected to the first metal layer MET1 and the second metal layer MET2 according to the level of a voltage applied to the input terminal NIN of the second metal layer MET2, And the output terminal NUT of the transistor Q2 is electrically connected.
Preferably, the first semiconductor layer FCD1 includes a first source layer LSC1, a first channel layer LCH1, and a first drain layer LDR1.
The first source layer LSC1 includes an impurity of a first polarity and is connected to the first metal layer MET1.
The first channel layer LCH1 includes an impurity of a second polarity and is formed directly on the first source layer LSC1. At this time, the second polarity is opposite to the first polarity.
The first drain layer LDR1 is formed directly on the first channel layer LCH1. The first drain layer LDR1 includes an impurity of the first polarity and is connected to the output terminal NUT of the second metal layer MET2.
The second gate poly layer GPL2 is formed between the second metal layer MET2 and the third metal layer MET3 and the second gate terminal NGA2 is patterned. At this time, the second gate terminal NGA2 is electrically connected to the input terminal NIN of the second metal layer MET2, and the output of the third metal layer MET3 and the output of the second metal layer MET2 And is electrically insulated from the terminal (NUT).
The second semiconductor layer FCD2 is formed on the side surface of the second gate terminal NGA2 between the second metal layer MET2 and the second metal layer MET3. At this time, the second semiconductor layer FCD2 is electrically connected to the third metal layer MET3 and the second metal layer MET2 according to the level of the voltage applied to the input terminal NIN of the second metal layer MET2. And the output terminal NUT of the transistor Q2 is electrically connected.
Preferably, the second semiconductor layer FCD2 includes a second drain layer LDR2, a second channel layer LCH2, and a second source layer LSC2.
The second drain layer LDR2 includes an impurity of a second polarity and is connected to the output terminal NUT of the second metal layer MET2.
The second channel layer LCH2 includes an impurity of the first polarity and is formed directly on the second drain layer LDR2.
The second source layer LSC2 is formed directly on the first channel layer LCH1. The second source layer LSC2 includes an impurity of the second polarity and is connected to the third metal layer MET3.
In the vertical CMOS inverter device of the preferred embodiment, the first supply voltage VPW1 is lower than the second supply voltage VPW2, the first polarity is n-type, and the second polarity is p-type .
In this case, a vertical CMOS inverter device having an equivalent circuit as shown in Fig. 2A is realized. In FIG. 2A, the first supply voltage VPW1 is a ground voltage VSS and the second supply voltage VPW2 is a power supply voltage VDD.
In a vertical CMOS inverter device of another preferred embodiment, the first supply voltage VPW1 is higher than the second supply voltage VPW2, the first polarity is a p-type, the second polarity is an n-type to be.
In this case, a vertical CMOS inverter device having an equivalent circuit as shown in Fig. 2B is implemented. 2B, the first supply voltage VPW1 is a power supply voltage VDD and the second supply voltage VPW2 is a ground voltage VSS.
In the vertical CMOS inverter device of the present invention as described above, the respective components are vertically stacked. Accordingly, in the vertical CMOS inverter according to the present invention, each component is vertically stacked. Thus, according to the vertical CMOS inverter device of the present invention, the required layout area is remarkably reduced. Also, since the connection length of the components is shortened, the delay due to the connection is minimized, and high-speed operation is enabled.
(Vertical type Seamos Method of manufacturing inverter device)
Next, a method of manufacturing the vertical CMOS inverter device of the present invention is described.
3 is a flowchart for explaining a method of manufacturing the vertical CMOS inverter device of FIG.
Referring to FIG. 3, the vertical CMOS inverter device includes a first metal layer forming step S10, a first gate poly layer forming step S20, a first gate terminal / first semiconductor layer forming step S30 (S50), a second gate terminal / second semiconductor layer forming step (S60), and a third metal layer forming step (S70) .
In the first metal layer forming step (S10), as shown in FIG. 4, the first metal layer MET1 is formed on the prepared semiconductor substrate SUB. Specifically, a first insulating
In the first gate poly layer forming step S20, as shown in FIG. 5, a first gate poly layer GPL1 is formed on the first metal layer MET1. Specifically, a second insulating
The first gate poly layer GPL1 is patterned into a first gate region ARGAT1 and a third
In the first gate terminal / first semiconductor layer formation step (S30), a first gate terminal (NGA1) and a first semiconductor layer (FCD1) are formed as shown in FIG. More specifically, the third insulating
A first
At this time, the first source layer LSC1 is a semiconductor material (for example, silicon) including an impurity of a first polarity and is connected to the first metal layer MET1.
The first channel layer (LCH1) is a semiconductor material containing an impurity of a second polarity and is formed directly connected to the first source layer (LSC1).
The first drain layer LDR1 is a semiconductor material containing an impurity of the first polarity and is formed directly above the first channel layer LCH1.
In the second metal layer forming step S40, as shown in FIG. 7, a second metal layer MET2 is formed, and the input terminal NIN and the output terminal NUT are patterned. Specifically, the third insulating
The second metal layer MET2 is formed in a state where the first gate terminal NGA1 of the first contact region ARCT1 is open. The second metal layer MET2 is patterned to form the input terminal NIN and the output terminal NUT.
As a result, the input terminal NIN of the second metal layer MET2 is connected to the first gate terminal NGA1, and the output terminal NUT of the second metal layer MET2 is connected to the first And is connected to the first drain layer LDR1 of the semiconductor layer FCD1.
A fourth insulating
In the second gate poly layer forming step (S50), the second gate poly layer (GPL2) is formed as shown in Fig. Specifically, the fourth insulating
The second gate poly layer GPL2 is formed in a state where the input terminal NIN of the second metal layer MET2 is open. Then, the second gate poly layer GPL2 of the second gate region ARGAT2 is patterned.
A fifth insulating
In the second gate terminal / second semiconductor layer formation step (S60), a second gate terminal (NGA2) and a second semiconductor layer (FCD2) are formed as shown in Fig. Specifically, the fifth insulating
A second
At this time, the second drain layer LDR2 is a semiconductor material (silicon) including an impurity of a second polarity and is connected to the output terminal NUT of the second metal layer MET2.
The second channel layer LCH2 is a semiconductor material containing an impurity of a first polarity and is formed directly above the second drain layer LDR2.
The second source layer (LSC2) is a semiconductor material containing an impurity of the second polarity, and is formed directly above the second channel layer (LCH2).
In the third metal layer forming step S70, as shown in FIG. 10, a third metal layer MET3 is formed on the fifth insulating
Accordingly, the third metal layer MET3 is connected to the second source layer LSC2 of the second semiconductor layer FCD2, and is insulated from the second gate terminal NGA2.
According to the method of manufacturing the vertical CMOS inverter device of the present invention, the vertical CMOS inverter device of the present invention as shown in FIG. 1 is formed.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
For example, in the present specification, the first insulating layer 110 and the
Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.
Claims (4)
A first metal layer formed on the semiconductor substrate and supplying a first supply voltage;
A second metal layer formed on the first metal layer and having an input terminal and an output terminal patterned;
A third metal layer formed on the second metal layer and supplying a second supply voltage;
A first gate poly layer formed between the first metal layer and the second metal layer and patterned with a first gate terminal, the first gate terminal electrically connected to the input terminal of the second metal layer, The first gate poly layer being electrically insulated from output terminals of the first metal layer and the second metal layer;
The first metal layer is formed on a side of the first gate terminal between the first metal layer and the second metal layer. The first metal layer is formed on the first metal layer, The first semiconductor layer being driven to conduct the output terminal of the second metal layer;
A second gate poly layer formed between the second metal layer and the third metal layer and having a second gate terminal patterned thereon, the second gate terminal electrically connected to the input terminal of the second metal layer The second gate poly layer being electrically insulated from the output terminal of the second metal layer and the third metal layer; And
And a second semiconductor layer formed on a side surface of the second gate terminal between the second metal layer and the third metal layer, the second semiconductor layer being formed on the second metal layer in accordance with a level of a voltage applied to an input terminal of the second metal layer, And the second semi-conductor layer is electrically connected to the third metal layer through an output terminal of the third semiconductor layer.
The first semi-
A first source layer including an impurity of a first polarity, the first source layer being connected to the first metal layer;
A first channel layer including an impurity of a second polarity having a polarity opposite to the first polarity, the first channel layer being formed directly on the first source layer; And
And a first drain layer formed directly on the first channel layer, the first drain layer including an impurity of the first polarity, the first drain layer being connected to an output terminal of the second metal layer,
The second semiconductive layer
A second drain layer including an impurity of the second polarity and connected to an output terminal of the second metal layer;
A second channel layer including an impurity of the first polarity and formed directly on the second drain layer; And
And a second source layer formed directly on the second channel layer, the first source layer including an impurity of the second polarity and connected to the third metal layer, device.
Wherein the first supply voltage has a level lower than the second supply voltage,
Wherein the first polarity is n-type,
And the second polarity is p-type
Vertical CMOS inverter device.
The first supply voltage has a level higher than the second supply voltage,
Wherein the first polarity is p-type,
The second polarity is n-type
Vertical CMOS inverter device.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020150013624 | 2015-01-28 | ||
KR20150013624 | 2015-01-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20160092923A KR20160092923A (en) | 2016-08-05 |
KR101743864B1 true KR101743864B1 (en) | 2017-06-07 |
Family
ID=56711321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020160005678A KR101743864B1 (en) | 2015-01-28 | 2016-01-17 | Vertical type cmos inverter device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101743864B1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110970369B (en) * | 2018-09-30 | 2022-08-02 | 中芯国际集成电路制造(上海)有限公司 | CMOS inverter structure and forming method thereof |
KR102324232B1 (en) * | 2020-06-03 | 2021-11-08 | 연세대학교 산학협력단 | Vertical Transistor Having Gate-All-Around Structure and Manufacturing Method Thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100625933B1 (en) | 2005-09-29 | 2006-09-18 | 매그나칩 반도체 유한회사 | Semiconductor device and method for fabrication of the same |
KR101057438B1 (en) | 2007-05-30 | 2011-08-17 | 고쿠리츠다이가쿠호진 도호쿠다이가쿠 | Semiconductor devices |
KR101351794B1 (en) | 2012-10-31 | 2014-01-15 | (주)피델릭스 | Pilla type vertical channel transitor in semiconductor device and fabrication method therefor |
-
2016
- 2016-01-17 KR KR1020160005678A patent/KR101743864B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100625933B1 (en) | 2005-09-29 | 2006-09-18 | 매그나칩 반도체 유한회사 | Semiconductor device and method for fabrication of the same |
KR101057438B1 (en) | 2007-05-30 | 2011-08-17 | 고쿠리츠다이가쿠호진 도호쿠다이가쿠 | Semiconductor devices |
KR101351794B1 (en) | 2012-10-31 | 2014-01-15 | (주)피델릭스 | Pilla type vertical channel transitor in semiconductor device and fabrication method therefor |
Also Published As
Publication number | Publication date |
---|---|
KR20160092923A (en) | 2016-08-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10204996B2 (en) | Metal-oxide-semiconductor transistor and method of forming gate layout | |
US7705666B1 (en) | Filler circuit cell | |
CN103426915B (en) | There is the semiconductor device of autoregistration cross tie part | |
US7485925B2 (en) | High voltage metal oxide semiconductor transistor and fabricating method thereof | |
US20070033548A1 (en) | Semiconductor integrated circuit device | |
CN108063157B (en) | Semiconductor device with a semiconductor device having a plurality of semiconductor chips | |
JP6065190B2 (en) | Semiconductor device | |
US9136264B2 (en) | MOS transistors having low offset values, electronic devices including the same, and methods of fabricating the same | |
US10032779B2 (en) | Semiconductor device with plasma damage protecting elements | |
KR101743864B1 (en) | Vertical type cmos inverter device | |
JP6122556B2 (en) | Semiconductor device | |
TWI520330B (en) | Semiconductor device | |
US11088067B2 (en) | Semiconductor device and layout design thereof | |
JP2007157892A (en) | Semiconductor integrated circuit and manufacturing method thereof | |
US20090008740A1 (en) | Semiconductor Integrated Circuit Devices Having Conductive Patterns that are Electrically Connected to Junction Regions and Methods of Fabricating Such Devices | |
US7723801B2 (en) | Semiconductor device and method of fabricating the same, and nor gate circuit using the semiconductor device | |
US20170062417A1 (en) | Semiconductor device | |
US20170250197A1 (en) | Layout structure for semiconductor integrated circuit | |
US20170243788A1 (en) | Layout structure for semiconductor integrated circuit | |
US20070034970A1 (en) | Semiconductor device and method of fabricating the same | |
US20190214304A1 (en) | A semiconductor device including monolithically integrated pmos and nmos transistors | |
KR100773740B1 (en) | Semiconductor divice configured of pad having the same voltage level with the substrate | |
US8835996B2 (en) | Integrated circuit configuration having extension conductor structure and fabricating method thereof | |
TWI528528B (en) | Integrated circuit configuration and fabricating method thereof | |
KR100685578B1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right |