TWI528528B - Integrated circuit configuration and fabricating method thereof - Google Patents

Description

Integrated circuit component construction and manufacturing method

The present invention is a method and a manufacturing method for an integrated circuit component, and particularly relates to an integrated circuit component construction and manufacturing method for increasing the flexibility of circuit layout.

In the development of integrated circuit manufacturing technology, the pursuit of miniaturization of components is a very important part. In digital logic circuits, many logic gates are often used repeatedly to combine different functional circuits. Therefore, if the area occupied by the logic gate in the integrated circuit is improved, the area occupied by the functional circuit as a whole can be greatly reduced, thereby achieving the effect of downsizing and cost saving.

Please refer to FIG. 1A , which is a circuit diagram of a NAND gate, which mainly uses two P-type MOS transistors P1 and P2 and two N-type MOS transistors N1 and N2. . When the input terminals A and B are both high voltage, the output terminal Y is a low voltage. If at least one of the input terminals A and B is a low voltage, the output terminal Y is a high voltage.

As shown in FIG. 1A, the functional circuit such as the anti-gate and the cell library have corresponding standard cells, and how to propose a better standard component layout to improve the lack of conventional means. Further reducing the component size and increasing the flexibility of the circuit layout is the main purpose of developing the case.

An object of the present invention is to provide an integrated circuit device structure comprising: a substrate; a diffusion region formed in the substrate; a gate structure formed over the substrate and across the diffusion region; and an extended conductor structure formed Above the substrate and in contact with the diffusion region, extending outward along the surface of the substrate to a first position, the first position being outside the range of the diffusion region; a dielectric layer formed over the substrate, the gate structure and the extended conductor structure; a contact structure that contacts the first location of the extended conductor structure through the dielectric layer; and a metal wire formed on the surface of the dielectric layer and in contact with the contact structure.

In a preferred embodiment of the invention, the substrate is a semiconductor substrate.

In a preferred embodiment of the invention, the diffusion region includes a channel region, a source region, and a drain region, and the channel region is located below the gate structure.

In a preferred embodiment of the invention, the extended conductor structure contacts the source region of the diffusion region.

In a preferred embodiment of the invention, the extended conductor structure contacts the drain region of the diffusion region.

In a preferred embodiment of the invention, the extended conductor structure is a zeroth layer metal structure.

In a preferred embodiment of the invention, the extended conductor structure comprises a strip contact structure and a zero layer metal structure.

In a preferred embodiment of the invention, the contact structure is completed by a zeroth layer contact structure.

In a preferred embodiment of the invention, the dielectric layer is a metal interlayer dielectric layer.

In a preferred embodiment of the invention, the metal wire passes over the gate structure.

Another object of the present invention is to provide a method for fabricating an integrated circuit component, comprising the steps of: providing a substrate; forming a diffusion region in the substrate; forming a gate structure over the substrate, the gate structure spanning the diffusion region; Forming a delay above the substrate Extending the conductor structure, the extended conductor structure is in contact with the diffusion region, the extended conductor structure extends outward along the surface of the substrate to a first position, the first position is beyond the range of the diffusion region; and a substrate is formed above the gate structure and the extended conductor structure a dielectric layer; forming a contact structure in the dielectric layer, contacting the first position of the extended conductor structure through the dielectric layer; and forming a metal wire on the surface of the dielectric layer, the metal wire contacting the contact structure.

In a preferred embodiment of the invention, the substrate is a semiconductor substrate.

In a preferred embodiment of the invention, the method of forming the diffusion region includes the steps of: forming a channel region, the channel region being below the gate structure; forming a source region and forming a drain region.

In a preferred embodiment of the invention, the extended conductor structure contacts the source region of the diffusion region.

In a preferred embodiment of the invention, the extended conductor structure contacts the drain region of the diffusion region.

In a preferred embodiment of the invention, the extended conductor structure is a zeroth layer metal structure.

In a preferred embodiment of the invention, the method of forming the extended conductor structure comprises the steps of forming a strip contact structure and a zero layer metal structure.

In a preferred embodiment of the invention, the contact structure is completed by a zeroth layer contact structure.

In a preferred embodiment of the invention, the dielectric layer is a metal interlayer dielectric layer.

In a preferred embodiment of the invention, the metal wire passes over the gate structure.

Referring to FIG. 1B, it is a schematic top view of the layout developed by the applicant for the structure of the anti-gate circuit of FIG. 1A, wherein the dotted line area represents the N-type well area 10, and the N-type well area 10 is a P-type semiconductor. The substrate 1 and the P-type diffusion region 11 and the N-type substrate contact region 19 shared by the N-type MOS transistors N1 and N2 are completed in the N-type well region 10, and the P-type MOS transistors P1 and P2 are shared. The N-type diffusion region 12 and the P-type substrate contact region 18 are completed in the P-type semiconductor substrate 1. The gate structures 13 and 14 across the P-type diffusion region 11 and the N-type diffusion region 12 complete the input terminals A and B in FIG. 1A, and the contact point 16 and the P-type diffusion region 11 and the N-type substrate contact region. 19. The N-type diffusion region 12 and the P-type substrate contact region 18 are electrically connected to the metal wires 150, 151 and 152, respectively connected to the working voltage VDD, the grounding point and the output terminal Y, thereby completing a reverse gate circuit unit. .

As can be clearly seen from the drawing, the distance h between the metal wires 150 and 151 respectively connected to the working voltage VDD and the grounding point determines the size of the reverse gate circuit structure to a considerable extent, and other logic circuit units are also the same. . Therefore, how to shorten the distance h more effectively is what is to be expressed in the next embodiment.

Referring to FIG. 2A to FIG. 2D, there is shown a schematic diagram of the top view of the present invention for increasing the flexibility of the circuit layout. FIG. 2A shows a circuit layout diagram of a MOS transistor, in which the gate structure 21 straddles the diffusion region 22 and divides the diffusion region 22 into a source region 221, a drain region 222 and a gate structure 21. In the channel region 223, in order to increase the layout elasticity of the MOS transistor, the position of the contact via structures 231, 232 is moved to both sides of the diffusion region 22 so as to be formed on the dielectric layer (this figure is not The metal wires 241, 242 shown above can change the layout position. The change in position is mainly achieved by the extended conductor structures 251, 252 located under the dielectric layer (not shown in this figure) and in contact with the source region 221 and the drain region 222, respectively. In this way, the metal wire 241 can be prevented from avoiding the seal ring 29 on the left side, and the metal wire 241 and the metal wire 242 have a pitch that conforms to the design rule.

Referring to FIG. 2B, a circuit layout diagram of two metal oxide semi-transistors shown in FIG. 2A is shown, and the extension of the conductor structures 251 and 252 not only makes the metal wires 241 and the metal wires 242 conform to each other. The spacing of the design rules also facilitates the connection of multiple MOS transistors.

Referring to FIG. 2C, a circuit layout diagram of another metal oxide semi-transistor is shown. Similarly, the extended conductor structures 251 and 252 are used to adjust the distance between the metal wire 241 and the metal wire 242. In this example, the metal wire 241 is used. The distance between the metal wires 242 and the metal wires 242 is increased such that the other metal wires 243 can be located between the metal wires 241 and the metal wires 242.

Referring to FIG. 2D, a circuit layout diagram of another metal oxide semi-transistor is shown. In this example, the extended conductor structures 251 and 252 and the contact via structures 231 and 232 are used to adjust the metal conductor 241 and the metal conductor 242. Extending the direction, the metal wire 241 and the metal wire 242 are then connected to the upper metal wire 271 and the metal wire 272 by additional contact via structures 261, 262. This will minimize the footprint of this component.

Please refer to FIG. 3, which is a schematic diagram of the circuit layout of the standard cell by using the extended conductor structure. The figure shows the reverse gate of a complementary MOS transistor process (NAND). Gate) layout structure, used to complete the anti-gate function circuit shown in Figure 1A, so the input and output indicators are labeled with Figure 1A. As shown in FIG. 3, metal wires 350, 351, and 352 are connected to the operating voltage VDD, the grounding point, and the output terminal Y, respectively. In order to achieve the purpose of downsizing, this example uses the extended conductor structure to change the layout, thereby shortening the distance between the metal wires 350 and 351 respectively connected to the working voltage VDD and the ground point, and finally shortening the length h of the standard unit. As shown in the figure. As can be seen from the figure, the dotted line area represents the N-type well area 30, and the N-type well area 30 is the P-type semiconductor substrate 3, and the N-type well area 30 is completed with the N-type MOS semi-transistors N1, N2. Shared P-type diffusion region 31 And an N-type substrate contact region 39, and the N-type diffusion region 32 and the P-type substrate contact region 38 shared by the P-type MOS transistors P1 and P2 are completed in the P-type semiconductor substrate 3. The gate structures 33, 34 across the P-type diffusion region 31 and the N-type diffusion region 32 complete the input terminals A, B in FIG. 1A. The P-type diffusion region 31, the N-type substrate contact region 39, and the N-type diffusion region are respectively connected through the electrical connection of the extended conductor structures 361, 362, 363, 364, 365 and the contact structures 371, 372, 373, 374, and 375. 32 and the P-type base contact region 38 are electrically connected to the metal wires 350, 351 and 352, wherein the extended conductor structure 361 is electrically connected to the P-type diffusion region 31 and the N-type substrate contact region 39, and then through the contact structure 371. The metal wire 350 is connected to the upper side. The extended conductor structure 365 is electrically connected to the P-type base contact region 38 and the N-type diffusion region 32, and then electrically connected to the upper metal wire 351 through the contact structure 375. The extended conductor structure 362 is electrically connected to the P-type diffusion region 31 and then electrically connected to the upper metal wire 352 through the contact structure 372. The extended conductor structure 363 is electrically connected to the P-type diffusion region 31, and then electrically connected to the upper metal wire 350 through the contact structure 373. The extended conductor structure 364 is electrically connected to the N-type diffusion region 32, and then electrically connected to the upper metal wire 352 through the contact structure 374. Then, a reverse gate circuit unit is completed. As can be seen from the figure, since the metal wires 350 and 351 are retracted, the component height h will be effectively reduced, and the purpose of the development of the case is achieved.

4A and 4B, wherein FIG. 4A is a schematic cross-sectional view showing the first embodiment of the above-mentioned extended conductor structure and contact structure, which mainly shows that the extended conductor structure can be integrated into a general process and also has a zero-thick metal structure. (M0) 41 (material may be copper or tungsten) is completed together, and the contact structure is completed by the zeroth layer contact structure 42 also in the general process, and the metal wires 350, 351 and 352 are made of the first layer of metal. Structure 43 (material can be copper or tungsten) is used. The zero-layer metal structure 41 passes through the inner dielectric layer (ILD) 401 and the pre-metal dielectric (PMD) 402 to complete contact with the zero-layer contact structure 42 and is then connected between the metal layers. The first layer of metal structure 43 (the material may be copper or tungsten) in the dielectric layer (IMD) 403.

Referring to FIG. 4B, which is a cross-sectional view showing a second embodiment of the extended conductor structure and the contact structure, which mainly shows that the extended conductor structure can be integrated into a general-purpose process and has a strip contact 50 and The zero-thick metal structure (M0) 51 is completed together, and the contact structure is completed by the zero-thick contact structure 42 also in the general process, and the metal wires 350, 351 and 352 are formed by the first metal structure 43. carry out. A slot contact 50 passes through the inner dielectric layer (ILD) 401 to complete contact with the zeroth layer metal structure 51, and the zeroth layer metal structure 51 passes through the pre-metal deposition dielectric layer (Pre- The metal dielectric (PMD) 402 is in contact with the zero-layer contact structure 42 and is then connected to the first metal structure 43 in the inter-metal dielectric layer (IMD) 403.

Referring to FIG. 5, another circuit layout diagram of the standard structure of the logic circuit is illustrated by using the extended conductor structure. The figure shows a reverse gate completed by a complementary MOS transistor process. (inverter) layout structure. As shown in FIG. 5, metal wires 650, 651, and 652 are connected to the operating voltage VDD, the grounding point, and the output terminal Y, respectively. In this example, the inverter is capable of reducing the size, and the extension conductor structure is also used to change the layout, thereby shortening the distance between the metal wires 650 and 651 respectively connected to the working voltage VDD and the ground point, and finally shortening the distance. The height h of the standard unit is reduced to the one shown in the figure. As can be seen from the figure, the dotted area represents the N-type well region 60, while the N-type well region 60 is the P-type semiconductor substrate 6, and the N-type well region 60 is completed with the N-type oxy-oxygen semiconductor P-type. The diffusion region 61 is formed, and the N-type diffusion region 62 of the P-type MOS transistor is completed in the P-type semiconductor substrate 6. The gate structure 63 spanning the P-type diffusion region 61 and the N-type diffusion region 62 completes the input terminal of the reverse gate. The P-type diffusion region 61 and the N-type diffusion region 62 are electrically connected to the metal wires 650, 651, and 652 through the electrical connection of the extended conductor structures 661, 662, and 663 and the contact structures 671, 672, and 673, respectively. A reverse gate circuit unit. By It can be seen that since the metal wires 650 and 651 are retracted and the metal wires can pass above the gate structure, the component height h will be effectively reduced, and the purpose of the development of the present invention is achieved.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1, 3, 6‧‧‧ substrates

10, 30, 60‧‧‧N type well area

11, 31, 61‧‧‧P type diffusion zone

12, 32, 62‧‧‧N type diffusion zone

13, 14, 21, 33, 34, 63‧‧ ‧ gate structure

16‧‧‧Contact points

18, 38‧‧‧P type substrate contact area

19, 39‧‧‧N type substrate contact area

22‧‧‧Diffusion zone

29‧‧‧Seal ring

41, 51‧‧‧ zero-layer metal structure

42‧‧‧ Zero-layer contact structure

43‧‧‧First metal structure

50‧‧‧ strip contact structure

150, 151, 152‧‧‧Metal wires

221‧‧‧ source area

222‧‧‧Bungee Area

223‧‧‧Channel area

231, 232, 261, 262‧ ‧ contact through-hole structure

241, 242, 243, 271, 272‧‧‧ metal wires

251, 252‧‧‧Extended conductor structure

350, 351, 352‧‧‧Metal wires

361, 362, 363, 364, 365‧‧‧ extended conductor structure

371, 372, 373, 374, 375 ‧ ‧ contact structure

401‧‧‧Internal dielectric layer

402‧‧‧Dielectric layer before metal deposition

403‧‧‧Metal interlayer dielectric layer

650, 651, 652‧‧‧ metal wires

661, 662, 663‧‧‧ Extended conductor structure

671, 672, 673‧‧ ‧ contact structure

A, B‧‧‧ input

h‧‧‧The length of the standard unit of the logic circuit

N1, N2‧‧‧N type gold oxide semi-transistor

P1, P2‧‧‧P type gold oxide semi-transistor

Y‧‧‧ output

Figure 1A shows a circuit diagram of a NAND gate.

FIG. 1B is a top plan view showing a layout of the anti-gate circuit of FIG. 1A.

FIG. 2A to FIG. 2D are schematic diagrams showing the top view of the circuit layout for increasing the flexibility of the circuit layout.

Figure 3 shows a schematic diagram of the circuit layout of a standard unit for reducing logic using an extended conductor structure.

4A is a cross-sectional view showing the first embodiment of the extended conductor structure and contact structure of FIG. 3.

4B is a cross-sectional view showing a second embodiment of the extended conductor structure and contact structure of FIG. 3.

Figure 5 shows a schematic diagram of another circuit layout that utilizes an extended conductor structure to reduce the standard cells of a logic circuit.

21‧‧‧ gate structure

22‧‧‧Diffusion zone

29‧‧‧Seal ring

221‧‧‧ source area

222‧‧‧Bungee Area

223‧‧‧Channel area

231, 232‧‧‧ contact through-hole structure

241, 242‧‧‧Metal wires

251, 252‧‧‧Extended conductor structure

Claims (20)

An integrated circuit component structure comprising: a substrate; a diffusion region formed in the substrate; a gate structure formed over the substrate and spanning the diffusion region; and an extended conductor structure formed over the substrate And contacting the diffusion region, wherein a portion of the extended conductor structure is in direct contact with the surface of the substrate, and another portion of the extended conductor structure extends outwardly along the surface of the substrate to a first position, and the extending direction of the extended conductor structure is perpendicular to The diffusion region, wherein the first location is outside the range of the diffusion region; a dielectric layer is formed on the substrate, the gate structure and the extended conductor structure; and a contact structure is in contact through the dielectric layer To the first position of the extended conductor structure; and a metal wire formed on the surface of the dielectric layer and contacting the contact structure. The integrated circuit device structure of claim 1, wherein the substrate is a semiconductor substrate. The integrated circuit component structure of claim 1, wherein the diffusion region comprises a channel region, a source region and a drain region, the channel region being located under the gate structure. The integrated circuit component construction of claim 3, wherein the extended conductor structure contacts the source region in the diffusion region. The integrated circuit component construction of claim 4, wherein the extended conductor structure contacts the drain region in the diffusion region. The integrated circuit component structure of claim 1, wherein the extended conductor structure is a zero-thick metal structure. The integrated circuit component structure of claim 1, wherein the extended conductor structure comprises a strip contact structure and a zeroth layer metal structure. The integrated circuit component construction of claim 1, wherein the contact structure is completed by a zeroth layer contact structure. The integrated circuit device structure of claim 1, wherein the dielectric layer is a metal interlayer dielectric layer. The integrated circuit component construction of claim 1, wherein the metal wire passes over the gate structure. A method of manufacturing an integrated circuit component, comprising the steps of: providing a substrate; forming a diffusion region in the substrate; forming a gate structure over the substrate, the gate structure spanning the diffusion region; above the substrate Forming an extended conductor structure in contact with the diffusion region, the extended conductor structure extending outwardly along the surface of the substrate to a first position, the first location being outside the range of the diffusion region; the substrate, the gate Forming a dielectric between the pole structure and the extended conductor structure Forming a contact structure in the dielectric layer, contacting the first position of the extended conductor structure through the dielectric layer; and forming a metal wire on the surface of the dielectric layer, the metal wire contacting The contact structure. The method of manufacturing an integrated circuit component according to claim 11, wherein the substrate is a semiconductor substrate. The method of manufacturing an integrated circuit component according to claim 11, wherein the method of forming the diffusion region comprises the steps of: forming a channel region under the gate structure; forming a source region and forming A bungee area. The method of manufacturing an integrated circuit component according to claim 13, wherein the extended conductor structure contacts the source region in the diffusion region. The method of manufacturing an integrated circuit component according to claim 14, wherein the extended conductor structure contacts the drain region in the diffusion region. The method of manufacturing an integrated circuit component according to claim 11, wherein the extended conductor structure is a zeroth layer metal structure. The method of manufacturing an integrated circuit component according to claim 11, wherein the method of forming the extended conductor structure comprises the steps of: forming a strip contact structure and a zero layer metal structure. The method of manufacturing an integrated circuit component according to claim 11, wherein the contact structure is completed by a zero-layer contact structure. The method of manufacturing an integrated circuit component according to claim 11, wherein the dielectric layer is a metal interlayer dielectric layer. The method of manufacturing an integrated circuit component according to claim 11, wherein the metal wire passes over the gate structure.