JPH0864827A - Semiconductor device and method of fabrication thereof - Google Patents

Abstract

PURPOSE: To prevent gate electrodes from being displaced therebetween by constructing a first gate electrode below an ultrathin film, a single crystal ultra-thin film and a second gate electrode with the same mask in a self matching manner. CONSTITUTION: A 300nm thick Si film and a 100nm thick Si oxide film are deposited by a chemical vapor reaction, and are patterned whereby a minimum 200nm wide second gate electrode 12 and a gate protective insulating film 13 are formed. A second gate insulating film 10, an Si ultrathin film 5, and an oxide film 9 are processed using the gate protective insulating film 13 as a mask. Then, anisotropic dry etching is applied using the gate protective insulating film 13 as a mask to process an Si film 3 substantially vertically for patterning a first gate electrode 15. Accordingly, the gate electrodes are prevented from being displaced by constructing the first and second gate electrodes 12, 15, and the Si ultrathin film 5 in a self aligning manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed on an insulating film and a manufacturing method thereof, and more particularly to an ultra thin film double gate structure MOS transistor excellent in current driving capability and a manufacturing method thereof.

[0002]

2. Description of the Related Art A technique for forming a transistor in a single crystal ultrathin film formed on a semiconductor substrate with an insulating film interposed is SOI.
It is called technology and is well known. In particular, a structure in which a gate electrode is arranged so as to sandwich a single crystal ultra-thin film from above and below via a thin gate insulating film is also known as a double gate structure.

FIG. 2 shows a cross-sectional structure of a semiconductor device having the above double gate structure. In the figure, 1 is a semiconductor substrate,
Reference numeral 2 is a buried insulating film, and 50 is a single crystal ultra-thin film, which is sandwiched by the first gate electrode 140 and the second gate electrode 110 via the insulating films 24 and 90. 9
Reference numeral 0 is an element isolation insulating film, 180 and 190 are source diffusion layers and drain diffusion layers formed in the single crystal ultrathin film 50, and 25 and 26 are source electrodes and drain electrodes.

In the above structure, the element isolation insulating film 90, the first gate insulating film and the first gate electrode 140, and even the thick semiconductor film or insulating film 91 are formed on the semiconductor substrate 50, and the thick semiconductor film or insulating film is formed. The surface of the film 91 is flattened and polished,
It is based on a technique of bonding another semiconductor substrate 1 having an insulating film 2 formed on its surface by a wafer bonding technique. After the bonding step, the single crystal ultra-thin film 50 is formed by grinding and polishing from the back surface side of the semiconductor substrate 50 to a thickness defined by the back surface of the element isolation insulating film 90.

Single crystal ultra-thin film 50 formed by this process
The second gate electrode 110, the source diffusion layer 180,
The drain diffusion layer 190 and the like are formed based on the conventional manufacturing process. In the ultra thin film double gate structure transistor based on the above conventional manufacturing method, the current can be increased by a factor of 2 or more as compared with the normal transistor manufactured on the semiconductor substrate.

[0006]

In the conventional double gate transistor, as is apparent from the manufacturing method, the second gate electrode 110 is formed separately in alignment with the first gate electrode 140. The displacement between the electrodes was unavoidable. In particular, since the source / drain diffusion layers 180 and 190 are introduced into the ultrathin film 50 using the second gate electrode 110 as a mask, the source / drain diffusion layers 180,
The parasitic capacitance between the gate electrodes 190 and 190 and the first gate electrode fluctuates according to the positional deviation, and thus the dynamic characteristics of the transistor fluctuate.

The basic operating speed of a MOS transistor is proportional to C · V / I, where C is the parasitic capacitance, V is the power supply voltage, and I is the source / drain current. Drain diffusion layer 18
0 and 190 and the first parasitic capacitance between the gate electrodes were increased, but the feature of increasing the driving current was also small in the effect of improving the basic operation speed. Furthermore, in this structure, the gate electrode is formed twice, and the conventional semiconductor device manufacturing process such as the bonding of the patterned wafer (including the high temperature heat treatment process for improving the bonding strength), the grinding and the polishing process during the manufacturing process. As compared with the conventional transistor, an unclean manufacturing process must be performed, and an increase in the number of manufacturing processes is inevitable compared with a normal transistor. This inevitably causes an increase in manufacturing cost and a decrease in yield of non-defective products.

In particular, the step of laminating the patterned wafer is
Since two wafers having an insulating film or the like formed on the semiconductor surface and having different warp states are bonded to each other, pattern distortion cannot be avoided, which causes a serious problem in alignment.

Another drawback of the conventional double-gate transistor is that the current path from directly under the gate to the source electrode is defined by the thickness of the ultrathin film, so that the source series resistance of the source series resistor, which has a large feature of increasing the channel conductance. Therefore, it had the drawback of being hindered.

[0010]

According to the present invention, in order to solve the above-mentioned drawbacks of an ultrathin film double gate transistor, an insulating film, a semiconductor thin film, a thin first gate insulating film, and a single crystal are formed on a supporting substrate. A multi-layered semiconductor substrate in which ultra thin films are sequentially formed is prepared. A second gate insulating film and a gate electrode are formed on the single-crystal ultra-thin film of the substrate based on a general MOS transistor manufacturing method, and subsequently, the second gate insulating film and the single-crystal ultra-thin film are left as the gate electrode processing mask. , The first gate insulating film and further the semiconductor thin film are patterned to form a first gate electrode.

Prior to the above patterning of the semiconductor thin film, a thin side wall insulating film is formed so as to cover at least the side surface of the single crystal ultra thin film. After patterning the semiconductor thin film, impurities are diffused from the sidewall of the first gate electrode by using the sidewall insulating film as a mask to reduce the resistance. At the same time, the second gate electrode may be doped with impurities from above to reduce the resistance. Then, after removing the insulating film on the side surface of the single crystal ultra-thin film, a wet oxide film is used to form a thick oxide film on the exposed portions of the first and second gate electrodes and a thin oxide film on the side surface of the single crystal ultra-thin film. Form a film.

When the thin oxide film on the side surface of the single crystal ultra-thin film is removed by etching, the insulating film is left in a self-aligned manner only on the first and second gate electrode portions. From this state, a semiconductor thin film with a high concentration of impurities is deposited on the entire surface,
Impurities are diffused from the side surface of the single crystal ultra-thin film by the subsequent heat treatment to form source and drain diffusion layers. After that, the semiconductor thin film to which impurities are added at a high concentration is patterned to serve as source and drain extraction electrodes. Finally, the source and drain electrodes and the like may be formed by depositing an insulating film and opening at desired locations, and further depositing a wiring metal film and patterning the same. The phenomenon that a thick oxide film is selectively formed on the exposed portions of the first and second gate electrodes is based on the phenomenon that accelerated oxidation is performed in a semiconductor region to which a high concentration of impurities is added.

[0013]

According to the above method, the first gate electrode, the single crystal ultra thin film, and the second gate electrode, which are arranged under the ultra thin film, are formed in a self-aligned relationship by the same mask. Variations in parasitic capacitance between the first gate electrodes are essentially eliminated. Based on the above method,
The number of manufacturing steps is the same as that of normal MOS transistors,
Not only the miniaturization technology in the usual MOS transistor manufacturing can be applied as it is, but also the number of manufacturing steps can be reduced as compared with the conventional manufacturing of a double gate transistor. Moreover, it is not necessary to use unclean steps such as grinding and polishing during the manufacturing process. Therefore, it is possible to realize a fine transistor which is excellent in large-current characteristics and can operate at an ultrahigh speed without increasing the manufacturing cost.

Further, according to the present invention, not only the dimensions of the first and second gate electrodes but also the film thickness of the insulating film formed on the side walls thereof can be formed under the same conditions in the same manufacturing process, and the parasitic capacitance can be easily reduced. Become. Focusing on the first and second gate insulating films in the formation of the side wall insulating film, the phenomenon that the film thickness is thicker at the edges than at the inside is added due to the progress of oxidation from the edges of the ultrathin film. . As a result, it is possible to selectively increase the film thickness of the gate insulating film in the overlapping portion of the source / drain diffusion layers and the first and second gate electrodes formed at the end of the ultrathin film. Therefore, it is possible to reduce the occurrence of defects such as a source-gate short circuit defect, which is usually a problem at the gate end, and
This has the effect of reducing the parasitic parasitic capacitance between the source / gate and the drain / gate. That is, it is possible to provide a double gate transistor having excellent reliability and high-speed operation characteristics.

Further, according to the present invention, the semiconductor layer from the end portion of the gate electrode which acts as the source resistance to the connection with the metal wiring is not limited to the thickness of the single crystal ultra-thin film in which the transistor is formed and is sufficiently thick. , A metal film or a metal silicide film, the source resistance of the conventional double gate structure transistor cannot be reduced because it is limited by the thickness of the ultra-thin film semiconductor that constitutes the active layer, resulting in an obstacle to increasing the current. It also has the effect of eliminating the drawbacks.

[0016]

【Example】

(Embodiment 1) FIG. 1 is a sectional view of a semiconductor device based on the embodiment 1, and FIGS. 3 to 10 are sectional views showing manufacturing steps of the semiconductor device according to the embodiment 1. Note that the support substrate 1 at the bottom of the embedded insulating film 2 is not shown in FIGS.

In each drawing, the left side shows a cross section in the gate length direction of the transistor, and the right side shows a cross section in the gate width direction. A buried insulating film made of a silicon (Si) thermal oxide film having a thickness of 500 nm, a Si insulating film having a thickness of 300 nm, a Si gate film having a Si thermal oxide film having a thickness of 5 nm 4, and 100 nm thick Si single crystal ultra-thin film 5
A multi-layer semiconductor substrate having the above is prepared. The multi-layer semiconductor substrate is obtained by directly bonding a first single crystal Si substrate having an insulating film 2 formed on its main surface and a second single crystal Si substrate having a gate insulating film 4 and a Si film 3 sequentially formed on its main surface. After bonding by the bonding method and increasing the bond strength by high-temperature heat treatment at about 1100 ° C., the back surface of the first Si substrate is ground and polished to make a thin layer, and the layer thickness distribution is locally corrected to correct the layer thickness distribution. An ultra thin film is formed by etching.

In the above-mentioned multilayer semiconductor substrate, the Si film 3 may be made to have a low resistance by adding a high concentration of impurities such as phosphorus or boron at a high concentration. Further, the first gate insulating film 4 may be, for example, a oxynitride film obtained by nitriding an oxide film, a Si nitride film, or another deposited insulating film instead of the Si oxide film. The method for manufacturing the multilayer semiconductor substrate is not limited to the method based on this method, and may be based on, for example, the method of forming an oxide film having a desired film thickness at a predetermined depth position of the semiconductor substrate by the oxygen ion implantation method. Good (Figure 3).

Single crystal S of the multilayer semiconductor substrate shown in FIG.
Forming a laminated film composed of the thin Si oxide film 6 and the Si nitride film 7 on the surface of the i ultra-thin film 5, patterning so as to selectively leave it in a desired region, and then using the laminated film as a mask 5 × 1
Phosphorus of 0 ¹⁵ / cm ² was ion-implanted into the Si film 3, and a low resistance Si film region 8 was formed by subsequent heat treatment (FIG. 4).

From the state shown in FIG. 4, a 50 nm thick oxide film 9 is formed on the side surface of the Si ultra-thin film 5 exposed by selective oxidation using the Si nitride film 7 as an oxidation mask and on the surface of the low resistance Si film region 8. Then, the laminated film including the thin Si oxide film 6 and the Si nitride film 7 was selectively removed. A thermal oxide film having a thickness of 5 nm was formed again on the surface of the Si ultrathin film 5 exposed from this state to form the second gate insulating film 10. After that, an opening for connecting a first gate electrode and a second gate electrode, which will be described later, was formed in a desired portion of the oxide film 9 (FIG. 5).

From the state of FIG. 5, 300 by chemical vapor reaction
nm Si film and 100 nm Si oxide film are deposited,
By the patterning, the second gate electrode 12 having the minimum dimension of 200 nm width and the gate protective insulating film 13 were formed. A high concentration of impurities may be added to the Si film during deposition (FIG. 6).

From the state shown in FIG. 6, the second gate insulating film 10, the Si ultra-thin film 5, and the oxide film 9 are formed on the gate protective insulating film 13
Was used as a mask for anisotropic dry etching. Thereafter, a Si nitride film having a thickness of 10 nm is deposited on the entire surface, and then the Si nitride film on the flat portion is selectively removed by anisotropic dry etching to remove the second gate electrode 12 and Si.
The Si nitride film 14 was left only on the side wall of the ultrathin film 5 (FIG. 7).

Anisotropic dry etching was performed using the gate protection insulating film 13 remaining from the state of FIG. 7 as a mask, the Si film 3 was processed substantially vertically, and the first gate electrode 15 was patterned. Then, after removing the gate protection insulating film 13, POCl ₃ is diffused from the sidewall of the first gate electrode 15 exposed using the Si nitride film 14 as a diffusion blocking mask and from the upper portion of the second gate electrode 12. Then, phosphorus was diffused to reduce the resistance of the first gate electrode 15 (FIG. 8).

The Si nitride film 14 is selectively removed from the state shown in FIG. 8 to expose the sidewalls of the first gate electrode 15 and the single crystal Si ultrathin film 5, and the upper surface and sidewall surface of the second gate electrode 12. It was Then, an oxide film was formed on the exposed surface by a wet thermal oxidation method at an oxidation temperature of 800 ° C. to form a gate sidewall insulating film 16. 1 is formed on the exposed surface of the first gate electrode 15 and the second gate electrode 12 to which phosphorus is added at a high concentration by wet thermal oxidation.
An oxide film having a thickness of 50 nm was formed, but only a 15 nm oxide film was formed on the side wall of the single crystal Si ultrathin film 5 having a low impurity concentration. After that, the oxide film formed on the side wall of the single crystal Si ultra-thin film 5 was completely removed by a hydrogen fluoride (HF) solution diluted with water. The film thickness of the sidewall insulating film of the electrode 12 was 120 nm. From this state, a low resistance Si film 17 to which phosphorus is added at a high concentration is deposited to a thickness of 300 nm, and the subsequent heat treatment causes a high concentration n-type source diffusion layer 18 to be formed on the side wall of the single crystal Si ultrathin film 5, and The drain diffusion layer 19 was formed (FIG. 9).

From the state shown in FIG. 9, a resist film pattern 20 having a thickness such that the upper surface of the second gate electrode 12 and the upper surface of the second gate electrode 12 are substantially aligned with each other is formed by thickening the pattern of the second gate electrode 12 by 800 nm. The second gate electrode 12 is arranged at a substantially constant distance, and then a second resist film 21 is applied so as to fill the recesses other than the resist film pattern 20 and the second gate electrode 12, thereby flattening the surface. Let

Subsequently, the resist film was uniformly removed from the surface of the second resist film 21 by dry etching to expose the surface of the low resistance Si film 17 on the second gate electrode. Then, a low resistance Si film 17 is formed by isotropic dry etching.
Was etched by the thickness of the film. By this step, the low resistance Si film 17 is selectively removed on the second gate electrode 12 (FIG. 10).

From the state of FIG. 10, the resist film pattern 2
0 and the resist film 21 were completely removed, and then the low resistance Si film 17 was patterned to form a source extraction electrode 22 and a drain extraction electrode 23. The removal process of the low resistance Si film 17 on the second gate electrode 12 shown in FIG. 10 is omitted, and the Si film on the second gate electrode 12 is omitted in the process of forming the source extraction electrode 22 and the drain extraction electrode 23. 1
There is nothing wrong with removing 7. After forming the source lead-out electrode 22 and the drain lead-out electrode 23, a wiring interlayer insulating film 24 is deposited on the entire surface, an opening is formed at a desired portion thereof, and then a metal film containing Al as a main material is deposited and patterned to form a source metal. Wiring 25, drain metal wiring 26,
A wiring layer including the gate metal wiring 27 was formed (FIG. 1).

In the semiconductor device of this embodiment manufactured according to the manufacturing process sequence, the double gate complete control is performed by the two gate electrodes so that the extremely thin single crystal semiconductor thin film of 10 nm or less is sandwiched from above and below via the gate insulating film. Depleted MO
Regarding the S-transistor, the upper gate electrode 12, the ultra-thin single-crystal semiconductor layer 5 forming the channel, and the lower gate electrode 15 can be formed in the same sectional shape and in a self-aligned relationship. With this configuration, the source / drain diffusion region 18
Since and 19 are introduced from the side wall of the ultrathin single crystal semiconductor layer 5, the area where the source / drain diffusion layers 18 and 19 overlap the upper and lower gate electrodes is also uniquely determined by the self-alignment relationship. As a result, in the conventional double gate structure in which the upper and lower gate electrodes are not self-aligned, the source / drain diffusion layer introduced with the upper gate electrode as a diffusion element mask has an overlapping area with the lower gate electrode. There is a drawback that the input / output capacitance cannot be specified for each element, and in the worst case, the source / drain regions and the lower gate electrode do not overlap with each other, so that a so-called offset region is formed and the effect of the lower gate electrode varies. It was possible to essentially solve the problems such as the reduction of the current caused by the variation or the variation.

In the semiconductor device according to this embodiment, the single crystal semiconductor ultrathin film 4 is patterned in a self-aligned relationship with the first gate electrode 15 and the second gate electrode 16 by the same mask, and The sidewalls of the gate electrode 15 and the second gate electrode 16 can be formed by using the concentration difference oxidation method in which the film thickness formed in the high impurity concentration region reaches 10 times or more that in the low impurity concentration region. The sidewall insulating film 16 can be formed by once performing wet low temperature oxidation and removing the thin oxide film formed on the sidewall of the single crystal semiconductor ultrathin film 4, and is self-aligned with the first gate electrode 15 and the second gate electrode 16. Is composed of Therefore, the manufacturing process is simplified as compared with the conventional method of forming the sidewall insulating film by a plurality of steps, and it becomes possible to reduce the film thickness variation and precisely control the channel length and the like.

In the semiconductor device according to the present embodiment, an insulating film formed by thermally oxidizing the side wall of the gate electrode processed to the minimum dimension determined by the lithographic technique without using the deposited insulating film for forming the side wall insulating film. Is left. Therefore, the size of the gate electrode can be further miniaturized, and an ultrafine semiconductor device suitable for a large current and high speed operation can be realized by a conventional device without using a state-of-the-art manufacturing device.

Further, in the semiconductor device according to the present embodiment, the width of the single crystal ultra-thin film 5 into which the source / drain diffusion layers 18 and 19 are to be introduced is based on the formation of the gate side wall insulating film 16 so that Configured to be wider than the width,
The end portion of the single crystal ultra-thin film 5 is defined and configured so as to coincide with the region sandwiched by the gate sidewall insulating films 16. As a result, the end portions of the single crystal ultra-thin film 5 are protected by the gate side wall insulating film 16, and it is possible to prevent the gate insulating films 4 and 6 from being unexpectedly scraped during the pretreatment for introducing the source and drain diffusion layers. It was also possible to prevent the occurrence of a short circuit defect between the diffusion layers 18 and 19 and the first or second gate electrode 15 or 12.

In the semiconductor device according to this embodiment, 100 n
The source and drain diffusion layers 18 and 19 formed at the ends of the ultra-thin single crystal semiconductor ultrathin film 5 of m or less are connected to the source and drain extraction electrodes 22 and 23 forming a sufficiently wide current path. It is connected to the metal electrodes 25 and 26. As a result, the source / drain series resistance is reduced as compared with a conventional semiconductor device using a semiconductor ultrathin film, in which the current path to the connection holes with the metal electrodes 25 and 26 is narrower than that defined by the single crystal semiconductor ultrathin film. Could be reduced. That is, in a transistor having a mask structure in which the distance from the connection hole with the metal electrodes 25 and 26 to the end of the gate electrode is 0.3 μm and the gate width is 10 μm,
The source / drain series resistance of the conventional structure transistor was 9.6Ω, which was not negligible, whereas the transistor according to the present embodiment was 3.2Ω and 1/3.
It was possible to reduce the series resistance.

In the semiconductor device according to this embodiment, n-conductivity type impurities are used as impurities to be added to the first and second gate electrodes 15 and 12. This is due to the fact that the concentration difference oxide film formation phenomenon by wet thermal oxidation is more remarkable on the surface of the semiconductor region to which the n-conductivity type impurity is added at a higher concentration than on the surface of the semiconductor region to which the p-conductivity type high concentration impurity is added. Based on. That is,
An oxide film of 150 nm is formed on the n-conductivity type high-concentration semiconductor region and 40 nm is formed on the p-conductivity type high-concentration semiconductor region under the condition that the film thickness formed on the side wall of the single crystal semiconductor ultra-thin film 5 without introducing impurities is 10 nm. Was done. Thus, for the purpose of leaving the insulating film having a sufficient film thickness on the gate side wall, the n-conductivity-type high-concentration impurity is added to the gate electrodes 12 and 15.
Is preferably added to.

In the manufacture of the semiconductor device according to this embodiment, the impurity addition to the first and second gate electrodes 15 and 12 is carried out at the same time in the same manufacturing process after processing the first gate electrode 15. Simplification of has been achieved.

(Embodiment 2) FIG. 11 is a sectional view of the semiconductor device according to the second embodiment of the present invention during the manufacturing process, and the completed sectional view is shown in FIG. Based on Example 1, a semiconductor device was manufactured up to the state shown in FIG. The second gate electrode length was set to 0.3 μm. From this state, phosphorus was diffused using POCl ₃ as a diffusion source to reduce the resistance of the entire Si film 3 to the lower part of the single crystal semiconductor ultrathin film 5. It is to be noted that the impurities should be introduced into the upper gate electrode 12 before the gate processing.
Phosphorus is diffused by using OCl ₃ as a diffusion source to reduce the resistance (FIG. 11).

From the state shown in FIG. 11, the silicon nitride film 14 used as the diffusion mask is selectively removed with a hot phosphoric acid solution, and then vertical dry etching is performed using the gate protective insulating film 13 as an etching mask to form the first gate electrode 15. Formed.
After that, the gate protection insulating film 13 used as the processing mask of the first gate electrode 15 is removed, and the first gate electrode 15 and the second gate electrode 15 and the second gate electrode 15 which have been converted into the high-concentration n conductivity type by the low temperature wet oxidation method at 800 ° C. 200 nm on the exposed surface of the gate electrode 12
25 nm of oxide film was grown on the exposed side wall surface of the single crystal semiconductor ultrathin film 5 in which the high concentration n conductivity type impurity was not introduced.

From this state, the oxide film formed on the exposed side wall surface of the single crystal semiconductor ultrathin film 5 was removed with a hydrogen fluoride solution diluted with water.
5 and the thickness of the sidewall insulating film 16 of the second gate electrode 12 was 150 nm. After the sidewall insulating film 16 is selectively left, according to the first embodiment, phosphorus having a high concentration is added to the low resistance S.
The formation of the n-conductivity type source diffusion layer 18 and the drain diffusion layer 19 on the side wall of the single crystal Si ultrathin film 5 by the deposition of the i film 17 and the subsequent heat treatment, and further the source extraction electrode 22, the drain extraction electrode 23, and the source. A metal wiring 25, a drain metal wiring 26, a gate metal wiring, etc. were formed (FIG. 1).

In the semiconductor device manufactured according to this embodiment, the first gate electrode 15 is processed after removing the Si nitride film 14 used to prevent the introduction of impurities into the side wall of the single crystal semiconductor ultrathin film 5. can do. As a result, as compared with the semiconductor device according to the first embodiment, the first gate electrode 15
The size of can be made almost the same as that of the second gate electrode 12. As a result, the size of the first gate electrode 15 can be made almost the same as the processing mask size, and the overlapping parasitic capacitance between the first gate electrode 15 and the source / drain diffusion layers can be reduced.

In the manufacturing process of the semiconductor device according to this embodiment, the side wall insulating film 16 is formed to be slightly thicker than that of the first embodiment. However, as the side wall insulating film 16 is formed thicker, the first gate insulating film is formed. The film thicknesses of the fourth and second gate insulating films 10 are configured to be thicker on the side wall portion than in the inside. That is, while the film thickness inside was 5 nm, the film thickness at the side wall was 8 nm or more. As a result, the withstand voltage between the gate electrodes 15 and 12 and the source / drain diffusion layers was improved to about 6.5 V, which is more than 1.5 times higher.

(Embodiment 3) After manufacturing a semiconductor device up to the state of FIG. 7 in Embodiment 2, a thickness Si of about 30 nm is further added.
After etching the film 3 in the vertical direction, phosphorus was diffused using POCl ₃ as a diffusion source to reduce the resistance of the entire Si film 3 and lower the resistance down to the single crystal semiconductor ultrathin film 5.
Thereafter, according to the second embodiment, the semiconductor device is manufactured by performing the manufacturing steps after the processing of the first gate electrode 15.

In the semiconductor device according to this embodiment, the Si film 3 is used.
It was possible to improve the production yield in the high-concentration diffusion process of phosphorus to the substrate. That is, in the processing of the first gate insulating film 4, a part of the single crystal semiconductor ultra-thin film 5 is exposed at the side wall portion due to processing variations, and phosphorus is erroneously introduced into the single crystal semiconductor ultra-thin film 5. Although there was a certain probability in the method of manufacturing a semiconductor device according to the second embodiment, the defect could be completely eliminated by the method according to the present embodiment. This defect is due to the processing of the first gate insulating film 4, and if a part of the first gate insulating film 4 is exposed even if the single crystal semiconductor ultra-thin film 5 is not exposed, the defect may occur during the phosphorus diffusion process. It is considered that the first gate insulating film 4 cannot play the role of diffusion prevention because the first gate insulating film 4 is made of phosphorus.

Based on the above consideration, in the manufacture of the semiconductor device according to the present embodiment, a semiconductor device in which the first gate insulating film 4 is composed of the Si nitride film instead of the Si oxide film is formed. Even when part of the film 4 was exposed, introduction of phosphorus into the single crystal semiconductor ultrathin film 5 could be completely prevented. Therefore, it is effective to use the Si nitride film having a large impurity diffusion blocking effect as the first gate insulating film 4 and the second gate insulating film 10.

The second gate electrode 12 which acts as a diffusion blocking film also when high-concentration diffusion of phosphorus is performed after the processing of the first gate electrode 15 as in the manufacture of the semiconductor device according to the first embodiment. The Si nitride film 14 remaining on the side wall of the first gate insulating film 4 is formed after processing the first gate insulating film 4 and slightly etching the Si film 3.
It is desirable that the structure be protected by the nitride film 14.

(Embodiment 4) FIG. 12 is a sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention, and FIG.
Is a completed sectional view thereof. 12 and 13 are cross-sectional views of the transistor in the channel length direction. Formation of gate sidewall insulating film 16 and ultra-thin single crystal Si film 5 according to the first embodiment
The side wall was exposed. In this state, after a Si film having no added impurities is deposited on the entire surface, a p-channel type M
An n-channel MOS transistor is formed by selectively covering the Si film of the OS transistor constituent portion with a resist film, performing high-concentration ion implantation of arsenic using the resist film as a mask, removing the resist film, and further performing heat treatment for activating the implanted ions. N conductive type low resistance Si film 17 is selectively formed only on the Si film on the constituent region.
Was converted to.

By the above heat treatment, the n-conductivity type source diffusion layer 18 and the drain diffusion layer 19 were simultaneously formed on the side wall of the single crystal Si ultrathin film 5. Next, an oxide film 38 was formed on the surface of the Si deposition film by a low temperature wet oxidation method at 750 ° C., but about 150 nm on the n-conductivity type low resistance Si film 17 region,
An oxide film having a thickness of about 8 nm was formed on the Si film in which the impurities of the p-channel type MOS transistor constituent portion were not yet introduced. High-concentration boron ion implantation using the thick oxide film 38 formed on the n-conductivity type low resistance Si film 17 region as an ion implantation blocking mask and subsequent heat treatment are performed to self-align with the n-conductivity type low resistance Si film 17 region. Therefore, the Si film in the adjacent region was converted into the p-conductive type low resistance Si film 28. By the heat treatment, the p-conductivity type source diffusion layer 30 and the drain diffusion layer 29 were simultaneously formed on the side wall of the single crystal Si ultrathin film 51 (FIG. 12).

From the state of FIG. 12, the ion implantation blocking oxide film 3
8 is removed and then the n-conductivity type source extraction electrode 31, the drain extraction electrode 32, the p-conduction type source extraction electrode 34, and the drain extraction electrode 33 are formed according to the first embodiment, and further, the wiring protection insulating film 24 is formed. The desired metal wiring including the formation, the ground potential metal wiring 35, the output metal terminal 36, and the power supply metal wiring 37 was formed (FIG. 13).

In the semiconductor device according to this embodiment manufactured through the above manufacturing steps, the single crystal Si ultrathin films 5 and 51 are provided with the first gate electrode 15 via the gate insulating films 4 and 10.
It was possible to manufacture a complementary MOS transistor having a self-aligned structure with a double-gate structure transistor which is configured to be sandwiched from above and below by the second gate electrode 12. In the complementary transistor, since the upper and lower gate electrodes and the source and drain diffusion layers are configured in a self-aligned relationship with each other, the parasitic capacitance between the gate electrode and the source and drain can be designed to be minimal, and Since the alignment margin between the first and second gate electrodes is essentially negligible, the device size can be miniaturized. This has made it possible to realize a complementary transistor that enables ultra-high-speed operation in combination with the characteristics of the double gate structure.

Further, in the semiconductor device according to the present embodiment, a complicated and expensive manufacturing method in the conventional method for manufacturing a double-gate structure transistor, that is, a patterned wafer manufactured up to an intermediate step using a mirror inversion mask is used in the semiconductor manufacturing process. With the wafer bonding technology of different type, it is possible to supply high-performance complementary transistors at a low price because there is no need for a method applied during the manufacturing process. Incidentally, the complementary MOS transistor according to this embodiment can be manufactured only with the same photolithographic mask used for manufacturing the complementary MOS transistor of the conventional structure which is normally manufactured on the substrate regardless of the double gate structure, so that a new mask design is made. High-performance complementary MO capable of ultra-high-speed operation without the need to install new semiconductor device manufacturing equipment
The S transistor can be provided at a low price.

(Embodiment 5) This embodiment is characterized by claims 1 to 1.
5 relates to a signal transmission processing device constituted by a semiconductor device manufactured according to the present invention described in 5, and particularly to a signal transmission processing device relating to an asynchronous transmission system (referred to as an ATM switch). 14 will be described.

In FIG. 14, an information signal transmitted at a high speed in series by an optical fiber is converted into an electric signal (O / E conversion) and is parallelized (S / P conversion) through a device. Integrated circuit (BF) composed of double-gate MOS transistors manufactured according to the first embodiment of the present invention.
MLSI).

The electric signal subjected to the addressing processing in the integrated circuit is serialized (P / S conversion) and converted into an optical signal (E / O conversion) and output through the optical fiber. BFMLSI is a multiplexer (M
UX), buffer memory (BFM), and separator (DM)
UX). BFMLSI is a memory control L
LSI with SI and free address allocation control function
(Empty address FIFO memory LSI). This signal transmission processing device is a device having a function of a switch for transmitting an ultra high speed transmission signal sent to a desired address at an ultra high speed regardless of an address to be transmitted.

Since the operation speed of the BFMLSI is remarkably slower than the transmission speed of the input optical signal, the input signal cannot be directly switched, and the input signal is temporarily stored, and the stored signal is switched, and then the ultrahigh-speed optical signal is switched. Is used for transmission to a desired address. If the operation speed of the BFMLSI is slow, a large storage capacity is required. In the ATM switch according to the present embodiment, since the BFMLSI is composed of the semiconductor device manufactured according to the first embodiment, the operating speed is three times as high as that of the conventional BFMLSI, and the cost is low. It has become possible to reduce the storage capacity to about 1/3 of the conventional one. This allows AT
It was possible to reduce the manufacturing cost of the M exchanger.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to the block diagram of the computer shown in FIG. The present embodiment is an example in which the semiconductor device manufactured according to the present invention according to claims 1 to 15 is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel.

In this embodiment, since the complementary semiconductor device embodying the present invention has a high degree of integration, one side of the processor 500 for processing instructions and operations, the system control device 501, the main storage device 502, etc. It could be composed of about 10 to 30 mm silicon semiconductor chip. A processor 500 for processing these commands and operations, a system controller 501, and a data communication interface 5 composed of a compound semiconductor integrated circuit.
03 was mounted on the same ceramic substrate 506. Also,
The data communication interface 503 and the data communication control device 504 are mounted on the same ceramic substrate 507. These ceramic substrates 506 and 507 and the ceramic substrate on which the main memory device 502 is mounted have a size of about 5 sides.
A central processing unit 508 of a large-scale computer was formed by mounting it on a substrate of about 0 cm or less.

Data communication in the central processing unit 508,
Data communication between a plurality of central processing units, or data communication between the data communication interface 503 and the substrate 509 on which the input / output processor 505 is mounted is performed via an optical fiber 510 indicated by double-ended arrow lines in the figure. It was In this computer, a processor 500 that processes instructions and operations, a system control device 501, a main storage device 50
The semiconductor devices such as No. 2 and the like operate in parallel at high speed, and the data communication is performed through the optical medium, so that the number of instruction processings per second can be significantly increased.

Although an example of a large-scale electronic computer has been described in the present embodiment, the semiconductor device based on the manufacturing method according to claims 1 to 15 of the present invention is not limited to a device systematized as a large-scale computer. Without the processor 500
It also applies when manufacturing only. This is naturally applied to the manufacture of so-called massively parallel processor components in which a large number of processors are connected in parallel.

[0057]

According to the present invention, a large current can be expected,
Regarding high-performance ultra-thin film double gate transistor capable of ultra-high speed operation, reduction of gate-source / drain overlap capacitance, improvement of operating characteristic variation by eliminating misalignment between gates, miniaturization of device dimensions by eliminating alignment margin, This has the effects of reducing the number of manufacturing steps, simplifying the manufacturing method, and providing a semiconductor device at a low cost that enables ultra-high-speed operation without the need for new mask design or introduction of new semiconductor device manufacturing equipment.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to first and second embodiments of the present invention.

FIG. 2 is a sectional view of a conventional semiconductor device.

FIG. 3 is a sectional view showing a first step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 4 is a sectional view showing a second step of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a third step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 6 is a sectional view showing a fourth step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 7 is a sectional view showing a fifth step of manufacturing the semiconductor device according to Example 1 of the present invention.

FIG. 8 is a sectional view showing a sixth step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 9 is a cross-sectional view showing the seventh step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 10 is a sectional view showing an eighth step of manufacturing the semiconductor device of Example 1 of the invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 12 is a sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 14 is an explanatory diagram of a signal transmission processing device according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram of a computer according to a sixth embodiment of the present invention.

[Explanation of symbols]

2 ... Buried insulating film, 4 ... First gate insulating film, 5 ... Si
Single crystal ultra-thin film, 6 ... Thin Si oxide film, 9 ... Oxide film, 10
... second gate insulating film, 11 ... opening, 12 ... second gate electrode, 15 ... first gate electrode, 16 ... gate sidewall insulating film, 18 ... n type source diffusion layer, 19 ... n type drain diffusion layer , 22 and 31 ... N-type source extraction electrode, 23 ... N
Type drain extraction electrode, 24 ... Wiring interlayer insulating film, 25 ...
Source metal wiring, 26 ... Drain metal wiring, 27 ... Gate metal wiring.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 29/78 301 H 9056-4M 617 S

Claims (17)

[Claims] 1. A semiconductor device comprising a first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, and a second gate electrode in this order on an insulating film,
The distance between the edge of the single crystal semiconductor thin film and the edge of the first gate electrode is equal to the distance between the edge of the single crystal semiconductor thin film and the edge of the second gate electrode. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein both side walls of the single crystal semiconductor thin film are respectively connected to low resistance semiconductor films constituting source and drain extraction electrodes. 3. The semiconductor device according to claim 1, wherein the first and second gate electrodes are composed of an n-conductivity type low resistance polycrystalline semiconductor film. 4. A semiconductor device comprising a first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, and a second gate electrode in this order on an insulating film,
The semiconductor device, wherein the first gate insulating film is composed of a silicon nitride film or a silicon oxynitride film. 5. A semiconductor device in which a first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, and a second gate electrode are formed in this order on an insulating film,
A semiconductor device, wherein each of the first and second gate insulating films is configured to be thin at a central portion of a channel and thick at an end portion of the channel. 6. A method of manufacturing a semiconductor device comprising a first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, and a second gate electrode in this order on an insulating film. 2. The method for manufacturing a semiconductor device according to, wherein the single crystal semiconductor thin film and the first gate electrode are processed using the second gate electrode as a mask. 7. A method of manufacturing a semiconductor device comprising a first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, and a second gate electrode in this order on an insulating film. 2. The method for manufacturing a semiconductor device according to, wherein the insulating films formed on the sidewalls of the first gate electrode and the second gate electrode are formed in the same manufacturing process. 8. The insulating film on the side wall of the single crystal semiconductor thin film according to claim 6, wherein the insulating film is selectively left only on the side wall portions of the first gate electrode and the second gate electrode. A method for manufacturing a semiconductor device, the method for removing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 6, 7 or 8, wherein the insulating film formed on the sidewalls of the first gate electrode and the second gate electrode is formed by a thermal oxidation method. 10. A first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, on the insulating film.
In a method of manufacturing a semiconductor device having a second gate electrode in this order, the second gate electrode and the second gate insulating film, the single crystal semiconductor thin film and the first gate insulating film, and the first gate insulating film. A method for manufacturing a semiconductor device, wherein impurities are selectively introduced into the first gate electrode after the patterning of the gate electrode. 11. A first gate electrode, a first gate insulating film, a single crystal semiconductor thin film, a second gate insulating film, on the insulating film.
A method of manufacturing a semiconductor device comprising a second gate electrode in this order, wherein impurities are introduced into the first gate electrode and the second gate electrode in the same manufacturing process. . 12. The semiconductor device according to claim 10, wherein the impurity introduction step is performed after patterning of the second gate electrode and the second gate insulating film, the single crystal semiconductor thin film and the first gate insulating film. Production method. 13. The impurity doping step according to claim 10, wherein the underlying semiconductor film is formed after patterning the second gate electrode and the second gate insulating film, the single crystal semiconductor thin film and the first gate insulating film. A method of manufacturing a semiconductor device, wherein a desired thickness is removed by the same mask. 14. The semiconductor device according to claim 1, 2, 3, 4, or 5, wherein the semiconductor device is a complementary MOS transistor. 15. Claims 6, 7, 8, 9, 10, 11, 1
2 or 13, wherein the semiconductor device manufactured by the method for manufacturing a semiconductor device is a complementary MOS transistor. 16. An asynchronous transmission mode device according to claim 1, 2, 3, 4, 5 or 14. 17. A processor device according to claim 1, 2, 3, 4, 5, or 14.