JP2001313394A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2001313394A
JP2001313394A JP2000129098A JP2000129098A JP2001313394A JP 2001313394 A JP2001313394 A JP 2001313394A JP 2000129098 A JP2000129098 A JP 2000129098A JP 2000129098 A JP2000129098 A JP 2000129098A JP 2001313394 A JP2001313394 A JP 2001313394A
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Prior art keywords
conductivity type
type
metal source
gate
drain region
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JP2000129098A
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JP4750244B2 (en
Inventor
Takehide Shirato
白土猛英
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Takehide Shirato
白土 猛英
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Abstract

PROBLEM TO BE SOLVED: To manufacture a high-speed, highly integrated and highly reliable SOI type C-MOS semiconductor device. SOLUTION: The SOI type C-MOS semiconductor device has a following damascene double-gate type common metal source drain among different channel structures. First, second, and third metal source drain regions (6a, 6b, 6c) are formed partly in contact with opposite side faces of each of a pair of p type and n type SOI substrate (3, 4) which are laminated on a semiconductor substrate 1 via an insulation film 2 and are made thin and are insularly insulated and separated from each other. In the parts of the SOI substrates which are in contact with the metal source drain regions, heavily-doped and lightly-doped source drain regions (10, 11, 12, 13), having the opposite conductivity type from that of the SOI substrates are formed. Being insulated and separated from each metal source drain region, a first gate electrode 9 is embedded flat on the lower surface of both SOI substrates via a first gate oxide film 7 and a second gate electrode 16 is embedded flat on the upper surface via a second gate oxide film 14, with the first and second gate electrodes being connected to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an SOI structure, and more particularly to a short-channel C-MOS type semiconductor device having an SOI structure of high speed, low power, high reliability, high performance and high integration (especially C-MOS semiconductor device). C-MOS SRAM using a MOS inverter and a flip-flop). Conventionally, with respect to a C-MOS semiconductor device including N-channel and P-channel MIS field-effect transistors having an SOI structure, a short-channel N-channel and P-channel MIS field-effect transistor having an LDD structure using sidewalls are surrounded by It is formed on each SOI substrate separated by an insulating film, and is intended to achieve high speed and low power by reducing junction capacitance, gate depletion layer capacitance, threshold voltage and the like. Because the contact resistance of the source / drain region is increased and the resistance of each element is not reduced, high speed has not been achieved despite miniaturization. An isolation region must be provided at the boundary of the P-channel MIS field-effect transistor. Despite the thinning, high integration has not been achieved, and when an off voltage of one MIS field effect transistor is applied to a conductor (semiconductor substrate) under an SOI substrate, the other MIS field effect transistor S
The bottom of the OI substrate is always in the ON state, and regardless of the voltage applied to the gate electrode, high current and high performance due to the inability to prevent minute current leakage due to the formation of a back channel at the bottom of the SOI substrate. There are drawbacks such as lack of reliability. Therefore, not only miniaturization of elements but also higher integration can be achieved, the resistance of each element including contact resistance can be reduced, higher speed can be achieved, and back channel leakage can be completely controlled. There is a demand for means capable of forming a MOS semiconductor device.

[0002]

2. Description of the Related Art FIG. 13 is a schematic side sectional view of a conventional semiconductor device, and shows an SO formed by using a bonded SOI wafer.
A part of a C-MOS semiconductor integrated circuit comprising N-channel and P-channel MIS field-effect transistors having an I structure is shown, and a reference numeral 51 denotes a p-type first silicon (Si) substrate;
Is an oxide film for bonding, 53 is a p-type second silicon substrate (p-type SOI substrate), 54 is an n-type second silicon substrate (n-type SOI substrate), and 55 is an element isolation region. A trench for formation and a buried oxide film, 56 is an n-type source / drain region, 57 is an n + -type source / drain region, 58 is a p-type source / drain region, 59 is a p + -type source / drain region, and 60 is a gate oxide film (SiO 2 ), 61 is a gate electrode, 62 is a base oxide film, 63 is a sidewall, 64 is an oxide film for impurity blocking, 65 is a PSG film, 66 is a barrier metal (Ti / TiN), 67
Is a plug (W), 68 is a barrier metal (Ti / TiN), 69 is
AlCu wiring 70 indicates a barrier metal (Ti / TiN). In the figure, a p-type thin film is bonded on a p-type first silicon substrate 51 via an oxide film 52, and is insulated and isolated in an island shape by a trench for forming an isolation region and a buried oxide film 55. A second silicon substrate (p-type SOI substrate) 53 and an n-type second silicon substrate (n-type S
An OI substrate 54 is formed. On the p-type SOI substrate 53, an n-type source / drain region 56 self-aligned with the gate electrode 61 and an n + -type source / drain region 57 self-aligned with the sidewall 63 are formed. A MIS field-effect transistor having an N-channel LDD structure is formed. An n-type SOI substrate 54 has a p-type source / drain region 58 formed self-aligned with a gate electrode 61, and a p + formed self-aligned with a sidewall 63. A MIS field-effect transistor having a P-channel LDD structure including a source / drain region 59 is formed. Further, the n + -type source region 57 vertically extends through the barrier metal (Ti / TiN) via the barrier metal (Ti / TiN) 66 and the plug (W) 67.
It is connected to the AlCu wiring 69 having (68, 70), and a ground voltage is applied. On the other hand, the p + type source region 59 is an AlCu wiring having barrier metal (Ti / TiN) (68, 70) above and below via a barrier metal (Ti / TiN) 66 and a plug (W) 67.
Connected to 69, power supply voltage is applied. Although not shown in the drawing, the gate electrodes 61 of the N-channel MIS field-effect transistor and the P-channel MIS field-effect transistor are connected to the front or back of the cut surface, and the input voltage is applied to the gate electrode 61. The matching n + -type drain region 57 and p + -type drain region 59 have upper and lower barrier metals (Ti / TiN) (68, 70) via a barrier metal (Ti / TiN) 66 and a plug (W) 67, respectively. AlCu wiring
A C-MOS inverter that is connected to an output voltage output circuit 69 is configured. Therefore, a reduction in junction capacitance due to formation of a source / drain region surrounded by an insulating film, a reduction in depletion layer capacitance due to complete depletion of the SOI substrate, and a reduction in threshold voltage due to improvement in sub-threshold characteristics are usually achieved. N and P channel M formed on a bulk wafer
Compared to a C-MOS inverter including an IS field-effect transistor, higher speed and lower power can be achieved. However, in order to completely deplete the SOI substrate, it is necessary to make the SOI substrate considerably thin (about 0.1 μm). When etching the PSG at the time of opening the electrode contact window, the SOI substrate forming the source / drain region is over-etched. However, the speed is not increased in spite of the short channel due to an increase in the contact resistance of the source / drain region, the inability to reduce the resistance of the source / drain region, and an N-channel MIS field effect transistor. Although the same voltage is applied to the drain region of the P-channel MIS field effect transistor and the drain region of the P-channel MIS field effect transistor, it is necessary to form an element isolation region in which an oxide film is buried. The high integration could not be achieved, and the conductor (p-type first silicon substrate) under the SOI substrate For applying a ground voltage, p-type SOI of
The back channel of the N-channel MIS field-effect transistor formed on the substrate is kept off, but the n-type S
The back channel of the P-channel MIS field-effect transistor formed on the OI substrate is always on. As a result, the N-channel MIS field-effect transistor operates normally regardless of whether the voltage applied to the gate electrode is the ground voltage or the power supply voltage.
In the S field effect transistor, current flows in both the front channel and the back channel at the ground voltage, and the front channel is off (current does not flow) at the power supply voltage, but there is a small current leak in the back channel,
There is a drawback that erroneous operation cannot be avoided.

[0003]

The problem to be solved by the present invention is that, as shown in the prior art, in order to obtain a MIS field-effect transistor with improved high-speed performance, a fully depleted thin film SOI substrate is required. Is required. In order to form a source / drain region on the thinned SOI substrate,
When etching the interlayer insulating film at the time of opening the electrode contact window, it is inevitable that the SOI substrate forming the source / drain region is over-etched, and the contact with the wiring body can be obtained, but the contact resistance of the source / drain region can be obtained. Increases, and the capacity can be reduced, but the resistance of the thin source / drain region cannot be reduced. For this reason, high speed cannot be achieved despite miniaturization, and a C-MOS is formed. In this case, depending on the voltage applied to the semiconductor substrate, in either one of the MIS field-effect transistors, the back channel is turned on even though the off voltage is applied to the gate electrode, and current leakage occurs. SOI that combines high speed, high integration, and high reliability because malfunctions cannot be avoided. C-MO elephant of short channel
That is, the S semiconductor device could not be formed.

[0004]

The object of the present invention is to provide a semiconductor substrate, a first insulating film provided on the semiconductor substrate, and one conductivity type selectively provided on the first insulating film. The one conductivity type and the opposite conductivity type SOI substrate are disposed between the opposite conductivity type SOI substrate and the one conductivity type and the opposite conductivity type SOI substrate.
A first metal source / drain region (conductive film) provided partially in contact with a side surface of the substrate; and a S type of the one conductivity type and the opposite conductivity type in contact with the first metal source / drain region.
Second and third metal source / drain regions (conductive films) provided partially in contact with the respective opposite side surfaces of the OI substrate, and contact portions between the first and third metal source / drain regions facing each other. And a pair of opposite conductivity type impurity regions (part of the source / drain region) provided on the one conductivity type SOI substrate and the opposite conductivity of a contact portion between the opposed first and second metal source / drain regions. A pair of one conductivity type impurity regions (part of the source / drain region) provided on the SOI substrate of the first type and a first gate insulating film provided on at least the lower surface of the SOI substrate of the one conductivity type and the opposite conductivity type And at least one of the first, second and third metal source / drain regions buried under the SOI substrate of the one conductivity type and the opposite conductivity type via the first gate insulating film. A gate electrode, a second gate insulating film provided on at least an upper surface of the SOI substrate of one conductivity type and the opposite conductivity type, and insulated and separated from the first, second and third metal source / drain regions; A second gate electrode buried on at least the one conductivity type and the opposite conductivity type SOI substrate through the second gate insulating film;
The first, second, and third metal source / drain regions;
An SOI substrate of the one conductivity type and the opposite conductivity type, and a second insulating film provided on the remaining side surface of the first and second gate insulating films. The problem is solved by the SOI type C-MOS semiconductor device of the present invention having a damascene double-gate inter-channel common metal source / drain structure (strictly speaking, a common metal drain structure) provided with a wiring body for applying the same voltage. You.

[0005]

[Operation] That is, in the semiconductor device of the present invention, p
Selectively on an oxide film provided on a silicon substrate of
Type and n-type SOI substrates are provided.
Part of the first metal source is in contact with the side surfaces of both SOI substrates.
A source drain region, and a first metal source drain.
Opposite sides of both SOI substrates in contact with the in-region
A second and a third metal source / drain partially contacting the surface
An area is provided. In addition, the first and third facing
For the p-type SOI substrate at the contact part of the source / drain region
A pair of n+ Type and n-type source / drain regions are provided,
On the other hand, opposed first and second metal source / drain regions
A pair of p-types is provided on the n-type SOI substrate + Mold and p-type
A source drain region is provided. Also, both SOI substrates
Lower surface and metal source / drain regions facing each other
(1st and 3rd, 1st and 2nd)
Oxide film (SiOTwo/ TaTwoOFive ) Is provided, and the first game
1st having barrier metal (TiN) through an oxide film
The gate electrode (W) is buried flat, while both S
On the upper surface of the OI substrate, a second gate oxide film (SiOTwo/ Ta TwoO
Five ) Are provided, each facing the metal source drain
Side walls on the upper side surfaces of the first and third regions (first and third, first and second).
Insulating film (SiOTwo) Is provided, and the second gate oxide film and
Having barrier metal (TiN)
Two gate electrodes (W) are buried flat. Further
Metal source drain region, first and second gates
The electrode (connected to the same potential) has a barrier metal (Ti / Ti
N) and barrier metal up and down via plug (W)
Formed in a structure to connect AlCu wiring with (Ti / TiN)
Metamachine Double Gate Type Common Meta for Different Channels
SOI type C-MOS semiconductor device having a source-drain structure
Is configured. (Metal source drain of the present invention
Regions are different from normal metal source / drain regions,
A region consisting only of a metal film or alloy film that does not contain impurity regions
Area. ) In addition, around the element,
And buried oxide film (SiOTwo) By completely insulated
Separated. Therefore, conventionally, for forming an element isolation region,
Separated by trenches and buried oxide
N formed as a region+ Type drain region and p+ Type
Low resistance with the rain region as a fine common drain region
Can be formed by conductive film (metal film or alloy film)
You. The p-type and n-type SOI substrates have their respective channels.
Tunnel region, low concentration source / drain region and extremely small
Only high-concentration source / drain regions
The source / drain region is not an impurity region but a conductive film (metal
Film or alloy film) to reduce the junction capacitance
Resistance of source and drain regions can be reduced.
It is. Wiring in thicker metal source / drain region
Can be connected to the body, reducing contact resistance
It is. Furthermore, Ta with a high dielectric constantTwoOFive Gate acid membrane
Gate oxide film can be made thicker
Small current leakage between the gate electrode and the SOI substrate.
Improvements and reductions in gate capacitance are also possible. In addition, S of the thin film
Since the gate structure is formed on the OI substrate,
The inversion layer under the gate oxide can be completely depleted
It is possible to remove the depletion layer capacitance between
Voltage between the gate electrode and the inversion layer
Can be applied only to the sub-threshold
Can be improved, so that the threshold voltage can be reduced. Furthermore, both SO
First and second gate electrodes can be formed above and below the I-substrate
Because of this (on both sides due to slight structural deformation)
In conjunction with the applied voltage of the first and second gate electrodes,
Front channel of one MIS field-effect transistor
And back channel (if there is a side gate electrode
To completely turn off the side channel)
Prevent the front of the other MIS field effect transistor
Channel and back channel (side gate electrode
Can be turned on completely even if the side channel
It is possible to supply as much drive current as possible. Sou
The lead-out portion for connecting the first and second gate electrodes is removed.
Alignment with the element isolation region where the oxide film is embedded.
A first gate formed through a first gate oxide film
Each element (each metal source / drain area)
Region, p-type and n-type SOI substrates, second gate oxide film and
A second gate electrode with a low concentration and a high
Concentration p-type and n-type impurity source / drain regions)
It can also be done. Also, the second insulation of the element isolation region
Film, each metal source / drain region and second gate electrode
That the upper surface of the surface can be formed as a continuous flat surface with no steps
Highly reliable interlayer insulating film and wiring body formed
You can also. In other words, extremely high speed, low power, high signal
Reliable, high performance and highly integrated semiconductor integrated circuits can be formed.
Damascene double gate type common metal saw between different channels
Obtaining SOI type C-MOS semiconductor device having drain structure
Can be

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a schematic plan view of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of the first embodiment of the semiconductor device of the present invention (sectional view taken along the line pp in FIG. 1). FIG. 3 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention (a cross-sectional view taken along the line qq in FIG. 1), and FIG. 4 is a schematic plan view of a second embodiment of the semiconductor device of the present invention. Figure,
FIG. 5 is a schematic side sectional view of a second embodiment of the semiconductor device according to the present invention (cross-sectional view taken along line qq in FIG. 4), and FIG. 6 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention. FIG. 7
FIG. 12 to FIG. 12 are process cross-sectional views of one embodiment of a method for manufacturing a semiconductor device of the present invention. The same objects are denoted by the same reference numerals throughout the drawings. 1 to 3 show a first embodiment of a semiconductor device according to the present invention. FIG. 1 is a schematic plan view, FIG. 2 is a schematic side sectional view (sectional view taken along the line pp in FIG. 1, N-channel and P-channel). Channel direction of the MIS field-effect transistor),
FIG. 3 is a schematic side sectional view (a sectional view taken along the line qq in FIG. 1, a channel width direction of an N-channel MIS field-effect transistor).
Then, the short channel N channel and the P channel M of the SOI structure formed using the bonding SOI technique
1 shows a part of a semiconductor integrated circuit including a C-MOS inverter composed of IS field-effect transistors, where 1 is 10
15 cm -3 p-type first silicon substrate, 2 0.5 μm
Oxide film for bonding (SiO 2 ), thickness of 0.1 μm
A second p-type silicon substrate (p-type SOI substrate), 4 an n-type second silicon substrate (n-type SOI substrate) having a thickness of about 0.1 μm, 5 an element isolation region formation Trenches and buried oxide films (SiO 2 ), 6a, 6b, 6c
Is a first, second and third metal source / drain regions (W) each having a thickness of about 0.5 μm, 7 is a first gate oxide film (SiO 2 / Ta 2 O 5 ) of about 15 nm, and 8 is a first gate oxide film of about 20 nm. Barrier metal (TiN), 9 is a first gate electrode (W) having a gate length of about 0.2 μm, 10 is an n-type source / drain region of about 10 17 cm -3 , 11 is an n + type of about 10 20 cm -3 Source drain region, 12
Is a p-type source / drain region of about 10 17 cm -3 and 13 is 10 20 cm
A p + type source / drain region of about -3, a second gate oxide film (SiO 2 / Ta 2 O 5 ) of about 15 nm, a barrier metal (TiN) of about 20 nm, and a gate length of about 0.2 μm Second
Gate electrode (W), 17 is a sidewall insulating film (Si
O 2 ), 18 is a phosphosilicate glass (PSG) film of about 0.8 μm, 19 is
Barrier metal (Ti / TiN) of about 50 nm, 20 is a plug (W), 21 is a barrier metal (Ti / TiN) of about 50 nm, 22
Denotes an AlCu wiring of about 0.8 μm, and 23 denotes a barrier metal (Ti / TiN) of about 50 nm. In FIG. 1, an oxide film 2 provided on a p-type silicon substrate 1 is selectively formed on an oxide film 2.
And n-type SOI substrates (3, 4) are provided, and a part of the SOI substrates (3, 4) is interposed between the SOI substrates (3, 4).
A first metal source / drain region 6 in contact with the side surface of 4);
is provided, and the second and third metal source / drain regions (6b, 6c) are partially in contact with the respective opposite side surfaces of the SOI substrates (3, 4) in contact with the first metal source / drain region 6a. ) Is provided. In addition, the first
An n + -type source / drain region 11 is provided apart from the p-type SOI substrate 3 at a contact portion of the third metal source / drain region (6a, 6c), and is in contact with each n + -type source / drain region 11. An n-type source / drain region 10 is provided, while the p + -type source / drain region is separated from the n-type SOI substrate 4 at the contact portion of the first and second metal source / drain regions (6a, 6b) facing each other. 13 are provided, and p.sup. +
A type source / drain region 12 is provided. Also both SO
A first gate oxide film (SiO 2 / Ta 2 O 5 ) 7 is provided on the lower surface of the I-substrate (3, 4) and the lower side surface of the metal source / drain regions (6a and 6c, 6a and 6b) facing each other. A first gate electrode (W) 9 having a barrier metal (TiN) 8 is buried flat through the first gate oxide film 7, while the upper surfaces of both SOI substrates (3, 4) are A second gate oxide film (SiO 2 / Ta 2 O 5 ) 14 is provided, and the opposing metal source / drain regions (6a
And 6c, 6a and 6b) on the upper side surface, a sidewall insulating film (Si
O 2 ) 17, and a second gate oxide film 14 and a second barrier film (TiN) 15
An MIS field-effect transistor having an N-channel and P-channel LDD structure is formed in which the gate electrode (W) 16 is buried flat. Further, each metal source / drain region (6a, 6b, 6c), the first
A barrier metal (Ti / TiN) 19 and a plug (W) are connected to the second gate electrodes (9, 16) (connected to the same potential).
20 through the barrier metal (Ti / TiN) (21, 2
3), the power supply voltage (Vdd) is applied to the second metal source / drain region 6b, and the ground voltage (Vss) is applied to the third metal source / drain region 6c. An input voltage (Vin) is applied to the first and second gate electrodes (9, 16) thus obtained, and a damascene double gate extracting an output voltage (Vout) from the first metal source / drain region 6a. An SOI C-MOS inverter having a common metal source / drain structure between different types of channels is configured. The periphery of the device is completely insulated and separated by a trench for forming a device isolation region and a buried oxide film (SiO 2 ) 5. Note that p
No voltage is applied to the n-type and n-type SOI substrates (3, 4). Therefore, conventionally, a low-resistance conductive region in which an n + -type drain region and a p + -type drain region separated by a trench for forming an element isolation region and a buried oxide film and formed as separate regions is a fine common drain region. It can be formed by a film (metal film or alloy film). On the p-type and n-type SOI substrates, only the respective channel regions, low-concentration source / drain regions and extremely minute high-concentration source / drain regions are formed, and most of the source / drain regions are formed of conductive films instead of impurity regions. (A metal film or an alloy film), so that the junction capacitance can be reduced (almost zero) and the resistance of the source / drain region can be reduced. Further, since the connection with the wiring body can be established in the thick metal source / drain region, the contact resistance can be reduced. In addition, since a Ta 2 O 5 film having a high dielectric constant can be used as a gate oxide film, the thickness of the gate oxide film can be increased, and a small current leak between the gate electrode and the SOI substrate can be improved and the gate capacitance can be reduced. It is possible. In addition, SO of thin film
Since the gate structure is formed on the I substrate, the SOI substrate can be completely depleted, so that the depletion layer capacitance between the inversion layer below the gate oxide film and the substrate can be removed.
The voltage applied to the gate electrode can be applied only between the gate electrode and the inversion layer, and the sub-threshold characteristic can be improved, so that the threshold voltage can be reduced. Furthermore, since the first and second gate electrodes can be formed above and below both SOI substrates, the front channel and the back channel of one MIS field-effect transistor can be linked to the voltage applied to the connected first and second gate electrodes. The channel can be completely turned off to prevent leakage current, and the front channel and the back channel of the other MIS field-effect transistor can be completely turned on so that a drive current as sufficient as possible can flow. In addition, except for a lead-out portion for connection of the first and second gate electrodes, the first gate oxide film is formed via the first gate oxide film in alignment with the element isolation region in which the oxide film is embedded.
Self-aligned with the gate electrode of each element (each metal source / drain region, p-type and n-type SOI substrates, a second gate electrode with a second gate oxide film and a side wall insulating film interposed therebetween, a low concentration and a high concentration P-type and n-type impurity source / drain regions). Also, the second element isolation region
By forming the upper surfaces of the insulating film, the metal source / drain regions, and the second gate electrode on a continuous flat surface without any step, an extremely reliable interlayer insulating film and wiring body can be formed. As a result, a SOI of a damascene double-gate type inter-channel common metal source / drain structure having high speed, low power, high reliability, high performance and high integration.
Type C-MOS semiconductor device can be obtained.

4 and 5 show a second embodiment of the semiconductor device according to the present invention. FIG. 4 is a schematic plan view, and FIG. 5 is a schematic side sectional view (an N-channel sectional view taken along the line qq in FIG. 4). 4 shows a channel width direction of the MIS field-effect transistor shown in FIG.
(The cross section taken along arrow -p is the same as FIG. 2 in the channel length direction of the N-channel and P-channel MIS field-effect transistors.)
Then, the short channel N channel and the P channel M of the SOI structure formed using the bonding SOI technique
1 to 23 show a part of a semiconductor integrated circuit including a C-MOS inverter composed of IS field-effect transistors.
3 to FIG. 3 are shown. In the figure, a wiring body for connecting the first and second gate electrodes at both ends of the first and second gate electrodes is provided, and this wiring body (strictly, a plug via a barrier metal) is connected to the side. Except that the gate electrode (the gate oxide film is a thick oxide film for forming an element isolation region),
A C-MOS inverter composed of channel and P-channel MIS field-effect transistors is formed. In this embodiment, in addition to the effects of the first embodiment, the front channel, back channel and side channel of one MIS field-effect transistor are completely turned off in conjunction with the applied gate voltage, and the leakage current , The front channel, the back channel and the side channel of the other MIS field-effect transistor are completely turned on, the drive current can be supplied to the front channel and the back channel as much as possible. Can pass a small current.

FIG. 6 is a schematic side sectional view of a semiconductor device according to a third embodiment of the present invention (the schematic plan view is the same as that of FIG. 4 and the N-channel MIS field effect is taken along the line qq in FIG. 4). 4 shows the channel width direction of the transistor (the cross-sectional view taken along the line pp in FIG. 4 is the same as that of FIG. 2 in the channel length direction of the N-channel and P-channel MIS field-effect transistors), and is formed using the bonding SOI technique. 1 to 23 show a part of a semiconductor integrated circuit including a C-MOS inverter composed of short-channel N-channel and P-channel MIS field-effect transistors having an SOI structure. I have. In the figure, a wiring body for connecting the first and second gate electrodes at both ends of the first and second gate electrodes is provided, the second gate electrode is formed in a concave structure, and the first gate is formed. An N-channel and P-channel MIS field-effect transistor having the same structure as that of the first embodiment except that a gate electrode is formed so as to cover the SOI substrate via the first and second gate oxide films together with the electrodes. A C-MOS inverter is formed. In this embodiment, in addition to the effects of the first embodiment, the front channel, back channel and side channel of one MIS field-effect transistor are completely turned off in conjunction with the applied gate voltage, and the leakage current And the front channel, back channel and side channel of the other MIS field-effect transistor are completely turned on,
As much drive current as possible can flow, and higher reliability and higher speed can be achieved. The present invention is not limited to the above description. For example, the metal source / drain region may be formed by using two or more metal layers including a barrier metal, and the gate electrode may be formed by a general polycide gate (polySi / WSi). The source / drain region made of impurities may be formed by forming a source / drain region consisting only of a high concentration not including a low concentration region. A drain region is formed and a P-channel MIS is formed.
Even if the field effect transistor forms a source / drain region consisting only of a high concentration without including a low concentration region, the present invention is also satisfied.

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 7 to 12 and FIG. However, here, only the manufacturing method relating to the formation of the semiconductor device of the present invention is described, and description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit is omitted. I do. FIG. 7 A first trench is formed by selectively anisotropically dry-etching the p-type second silicon substrate 3 using a resist (not shown) as a mask layer by using ordinary photolithography technology. (The alignment pattern is also the first
Of the trench. Next, the resist (not shown) is removed. Next, a chemical vapor deposition oxide film (SiO 2 ) is grown and anisotropically dry-etched to form a buried element isolation region 5 in the first trench. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a part of the oxide film (lead portion for connecting a first gate electrode to be formed later) of the element isolation region 5 is formed. Perform anisotropic dry etching of about 0.2 μm. Continuously, the p-type second silicon substrate 3 is
A second trench is formed by anisotropic dry etching to a degree. Next, the resist (not shown) is removed. Next, a first gate oxide film 7 (SiO 2 / Ta 2 O 5 ) of about 15 nm is grown. Next, a barrier metal (TiN) 8 of about 20 nm and a tungsten film (W) 9 of about 0.2 μm as a first gate electrode are grown by continuous sputtering. Then chemical mechanical polishing (C hemical M echanical
P Olishing after abbreviated as CMP) by embedding a second trench for a first gate electrode, the first
Buried gate electrode structure including the gate oxide film 7, the barrier metal 8 and the first gate electrode 9 is formed. At this time, the unnecessary portions of the first gate electrode 9, the barrier metal 8, and the first gate oxide film 7 are also removed. Next, using the oxide film 5, the first gate oxide film 7, the barrier metal 8, and the first gate electrode 9 as a mask layer, the remaining p-type second silicon substrate 3 is subjected to anisotropic dry etching of about 0.5 μm. To form a third trench. Then, by chemical vapor deposition,
Tungsten film (W) is grown and chemically mechanically polished (CM
P) to fill the third trench, and to form first, second, and third metal source / drain regions (W) (6a, 6b, 6c).
) Is formed. Next, the device isolation region 5, the metal source drain region (6
a, 6b, 6c) and the p on which the first gate electrode 9 and the like are formed.
Is formed on the second silicon substrate 3 of the mold by chemical vapor deposition.
An oxide film (SiO 2 ) 2 for bonding having a thickness of about μm is grown. Next, the p-type second silicon substrate 3 is stacked with the side on which the oxide film (SiO 2 ) 2 for bonding is formed on the p-type first silicon substrate 1 facing down, and annealed at about 1000 ° C. With this addition, the p-type second silicon substrate 3 is bonded onto the p-type first silicon substrate 1. Next, the p-type second silicon substrate 3 is mechanically ground to about several μm (the end point is estimated by exposing the buried oxide film of the element isolation region 5), and thereafter, chemical etching is performed until the buried metal source / drain region 5 is exposed. Mechanical polishing (CMP), 0.3μm
A p-type second silicon substrate (p-type SOI substrate) 3 having a flat thickness is formed. The alignment pattern formed by the first trench in which the oxide film is buried is thus formed on the lower surface of the p-type second silicon substrate 3 (the upper surface up to FIG. 8). Can be formed. Thereafter, using this alignment pattern, p
Each element can be formed on the upper surface of the second silicon substrate 3 of the mold. Next, using a normal photolithography technique, a resist (not shown) and metal source / drain regions (6a,
Using 6b, 6c) as a mask layer, a part of the oxide film (lead portion for connecting a second gate electrode to be formed later) of the element isolation region 5 is anisotropically dry about 0.2 μm. Continuously, the p-type second silicon substrate 3 is
A fourth trench is formed by anisotropic dry etching to a degree. (The remaining p-type second silicon substrate having a thickness of about 0.1 μm becomes a p-type SOI substrate.) Then, the resist (not shown) is removed. Then, using normal photolithography technology, a resist (not shown),
Using the oxide film 5 in the element isolation region and the metal source / drain regions (6a, 6b) as mask layers, phosphorus is ion-implanted selectively into the p-type second silicon substrate (p-type SOI substrate) 3, and n-type. A second silicon substrate (n-type SOI substrate) 4 is formed. Next, the resist (not shown) is removed. Next, a second gate oxide film 14 (SiO 2 /
Ta 2 O 5) to grow. Next, a barrier metal (TiN) 15 of about 20 nm and a W film 16 of about 0.2 μm as a second gate electrode are grown by continuous sputtering. Next, the fourth gate for the second gate electrode is buried by chemical mechanical polishing (CMP) to form a buried gate electrode structure including the second gate oxide film 14, the barrier metal 15, and the second gate electrode 16. . At this time, the unnecessary portion of the second gate electrode 1
6, the barrier metal 15 and the second gate oxide film 14 are also removed. Next, the second gate oxide formed on the side surfaces of the metal source / drain regions (6a, 6c) by using a resist (not shown) and the metal source / drain regions (6a, 6c) as a mask layer by using a usual photolithography technique. The film 14 is anisotropically dry etched to form a fifth trench. Then, the p-type SO exposed under the fifth trench
Phosphorus ions are implanted into the I substrate 3. Next, the resist (not shown) is removed. Next, the second gate oxidation formed on the side surfaces of the metal source / drain regions (6a, 6b) by using a resist (not shown) and the metal source / drain regions (6a, 6b) as a mask layer by using a normal photolithography technique. The film 14 is anisotropically dry etched to form a sixth trench. Next, boron is ion-implanted into the n-type SOI substrate 4 exposed under the sixth trench. Next, the resist (not shown) is removed. Then, by applying N 2 annealing at about 950 ° C., the film is diffused in the lateral direction,
-Type source / drain region 10 and p-type source / drain region 12
To form Then, arsenic is ion-implanted into the p-type SOI substrate 3 by using a resist (not shown) and the metal source / drain regions (6a, 6c) as a mask layer by using a usual photolithography technique. Next, the resist (not shown) is removed. Next, using a normal photolithography technique, using a resist (not shown) and the metal source / drain regions (6a, 6b) as a mask layer, an n-type SO
Boron is ion-implanted into the I-substrate 4. Next, the resist (not shown) is removed. Next, N 2 annealing at about 900 ° C. is performed to form the n + -type source / drain region 11 and the p + -type
To form Next, a chemical vapor deposition oxide film (SiO 2 ) 17 is grown. Next, the fifth and sixth trenches are buried by chemical mechanical polishing (CMP). Next, by chemical vapor deposition, 0.8 μm
A degree of phosphosilicate glass (PSG) film 18 is grown. Next, the PSG film 18 is anisotropically dry-etched using a resist (not shown) as a mask layer to selectively open an electrode contact window using a normal photolithography technique. An electrode for connecting the first and second gate electrodes (9, 16) using a resist (not shown) as a mask layer (mask layer of two resists) continuously using a normal photolithography technique Only the contact window is opened (see FIG. 3), and the second gate electrode 16, the barrier metal 15,
The second gate oxide film 14, the oxide film 5, and the first gate oxide film 7 are sequentially subjected to anisotropic dry etching. Next, the resist (not shown) is removed. Next, Ti and TiN 19 serving as barrier metals are sequentially grown by sputtering. Next, a W film is grown on the entire surface by a blanket method of chemical vapor deposition, and anisotropically dry-etched to form a buried plug (W).
Form 20. At this time, the W film 20 and the barrier metal of the unnecessary part
19 is also etched away. FIG. 2 Next, Ti and TiN serving as barrier metals are sequentially grown by sputtering. Next, by sputtering, Al
(Including several% of Cu) is grown to about 0.8 μm. Next, Ti and TiN serving as barrier metals are sequentially grown by sputtering. Next, using normal photolithography technology, a resist (not shown) is used as a mask layer, and an AlCu wiring 22 is formed by anisotropically dry-etching the barrier metal, Al (including several percent of Cu) and the barrier metal. Then, a semiconductor device is completed. In the above manufacturing method, the buried layer is formed by anisotropic dry etching in some steps, but all of these steps may be performed by chemical mechanical polishing (CMP).
In determining the threshold voltage of the channel MIS field-effect transistor, the p-type SOI substrate is used as it is, but the concentration of the SOI substrate may be controlled by boron ion implantation. In the above manufacturing method, the thickness of the SOI substrate is controlled by etching both the upper surface and the lower surface of the p-type second silicon substrate. Using a thin oxide film and a nitride film (Si 3 N 4 ) of about 0.2 μm formed on the lower surface (the bottom surface in the final drawing), a first gate oxide film and a second gate oxide film are formed on a step formed by etching the nitride film and the oxide film. By forming the first gate electrode so as to be embedded, it is possible to control the thin SOI substrate by etching only the lower surface (the upper surface in the final drawing) of the p-type second silicon substrate.
In the above manufacturing method, the source / drain regions are formed by impurities after the formation of the second gate electrode.
The gate electrode is used as a dummy electrode, and after forming the source / drain region by the impurity, the dummy electrode and the dummy gate oxide film are once removed by etching, and then the second gate oxide film and the lower-resistance second metal oxide film made of a low melting point metal are used. Two gate electrodes (such as Al) may be formed. In this case, the number of manufacturing steps is slightly increased, and the first gate electrode (W and the like) and the second gate electrode (Al and the like) are different. However, it is particularly effective when the gate electrode wiring is to be a word line in a memory or the like. .

In manufacturing the semiconductor device of the third embodiment, when forming the fourth trench in FIG.
The oxide film forming the element isolation region and the first gate oxide film are subjected to anisotropic dry etching until the lead-out portion for connection of the gate electrode is exposed, and the p-type second silicon substrate is continuously formed. A fourth trench is formed by anisotropic dry etching of about 0.2 μm, and after removing the resist,
When the fourth trench is filled with the second gate electrode via the second gate oxide film, the periphery of the SOI substrate is covered with the first and second gate electrodes via the first and second gate oxide films. Such a structure can be formed. Thereafter, if the same steps as those described above are performed, the semiconductor device of the third embodiment can be manufactured.

[0011]

As described above, according to the semiconductor device of the present invention, a pair of p-type and n-type semiconductor layers which are bonded on a semiconductor substrate via an insulating film, are thinned, and are insulated and isolated in an island shape. Three metal source / drain regions are provided in partial contact with the respective side surfaces of the SOI substrate of the n-type, and a pair of n + -type and n-type are provided on the p-type SOI substrate at a contact portion with each metal source / drain region. A source / drain region is provided, and a pair of p + -type and p-type source / drain regions are provided on the n-type SOI substrate. A first gate electrode is buried via an oxide film, and a second gate electrode is buried flatly on a top surface via a second gate oxide film to form a structure in which the first and second gate electrodes are connected. Gate An SOI C-MOS semiconductor device having a common metal source / drain structure between different types of channels is formed. Therefore, in the SOI structure, the resistance of the source / drain region is reduced by forming the metal source / drain region, the junction capacitance is reduced, and the contact resistance is reduced.
Improvement of minute current leakage between gate electrode and SOI substrate and reduction of gate capacitance by using gate oxide film of high dielectric constant Ta 2 O 5 , removal of depletion layer capacitance and sub-threshold by using fully depleted SOI substrate Reduction of threshold voltage due to improvement of characteristics, fine formation of a common source / drain region between N-channel and P-channel MIS field-effect transistors by metal film or alloy film, first and second connected
It is possible to control the back channel and the side channel by the gate electrode, and to finely form each element by self-alignment. That is, an SOI C-MOS semiconductor device having a damascene double-gate type inter-channel common metal source / drain structure capable of forming a semiconductor integrated circuit with extremely high speed, low power, high reliability, high performance and high integration is obtained. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic side sectional view of a first embodiment of the semiconductor device according to the present invention (a sectional view taken along the line pp in FIG. 1);

FIG. 3 is a schematic side sectional view of a first embodiment of the semiconductor device of the present invention (a sectional view taken along the line qq in FIG. 1);

FIG. 4 is a schematic plan view of a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention (a sectional view taken along the line qq in FIG. 4);

FIG. 6 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention.

FIG. 7 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a schematic side sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 p-type first silicon (Si) substrate 2 bonding oxide film (SiO 2 ) 3 p-type second silicon substrate (p-type SOI substrate) 4 n-type second silicon substrate ( n-type SOI substrate 5 element isolation region forming trench and buried oxide film (SiO 2 ) 6a first metal source / drain region (W) 6b second metal source / drain region (W) 6c third metal source / drain Region (W) 7 First gate oxide film (SiO 2 / Ta 2 O 5 ) 8 Barrier metal (TiN) 9 First gate electrode (W) 10 n-type source / drain region 11 n + -type source / drain region 12 p Type source / drain region 13 p + type source / drain region 14 second gate oxide film (SiO 2 / Ta 2 O 5 ) 15 barrier metal (TiN) 16 second gate electrode (W) 17 sidewall insulating film (SiO 2 ) 18 Phosphosilicate glass (PSG) film 19 Barrier metal Ti / TiN) 20 plug (W) 21 barrier metal (Ti / TiN) 22 AlCu wiring 23 barrier metal (Ti / TiN)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/41 H01L 29/78 616S 21/336 617J 617N 627D F-term (Reference) 4M104 AA09 BB01 BB14 BB18 BB30 CC01 CC05 DD08 DD37 EE03 EE16 FF01 FF18 FF22 FF27 GG09 GG10 GG14 5F033 GG03 HH04 HH09 HH18 HH19 HH28 HH33 JJ18 JJ19 JJ33 KK19 MM01 MM08 MM13 NN06 NN07 PP06 PP15 Q1611 AQ04 Q16 Q14 A BB08 BB09 BB11 BB12 BB19 BC01 BC06 BC11 BF00 BF02 BF07 BF15 BF16 BG14 5F110 AA02 AA03 AA04 AA06 AA18 BB04 BB07 DD05 DD13 EE01 EE03 EE04 EE05 EE09 EE14 EE30 J04 GG02 FF02 GG01 HL04 HL06 HL12 HL14 HL23 HM15 NN04 NN25 NN35 NN62 NN65 QQ11 QQ16 QQ19

Claims (5)

    [Claims]
  1. A semiconductor substrate, a first insulating film provided on the semiconductor substrate, an SOI substrate of one conductivity type and an opposite conductivity type selectively provided on the first insulating film; A first metal source / drain region (conductive film) provided between the one conductivity type and the opposite conductivity type SOI substrate so as to partially contact a side surface of the one conductivity type and the opposite conductivity type SOI substrate;
    Second and third metal source / drain regions (conductive film) provided partially in contact with the opposite side surfaces of the one conductivity type and the opposite conductivity type SOI substrate in contact with the first metal source / drain region, respectively. ) And a pair of opposite conductivity type impurity regions (part of the source / drain region) provided on the one conductivity type SOI substrate at a contact portion of the opposed first and third metal source / drain regions. A pair of one conductivity type impurity regions (part of the source / drain region) provided on the opposite conductivity type SOI substrate at a contact portion between the first and second metal source / drain regions; And a first gate insulating film provided on the lower surface of the SOI substrate of the opposite conductivity type, and insulated and separated from the first, second and third metal source / drain regions.
    A first gate electrode buried under at least the one conductivity type and the opposite conductivity type SOI substrate via the gate insulating film, and at least the one conductivity type and the opposite conductivity type SOI substrate
    A second gate insulating film provided on the upper surface of the substrate is insulated from and separated from the first, second and third metal source / drain regions, and at least the one conductivity type is interposed via the second gate insulating film. A second gate electrode buried on an SOI substrate of the opposite conductivity type, the first, second, and third metal source / drain regions;
    An OI substrate, a second insulating film provided on the remaining side surfaces of the first and second gate insulating films, and a wiring body for applying the same voltage to the first and second gate electrodes is provided. A semiconductor device characterized in that:
  2. 2. A wiring body for applying the same voltage to the first and second gate electrodes is provided on both side surfaces of the second semiconductor substrate in a channel width direction via the second insulating film, and a side gate is provided. 2. The semiconductor device according to claim 1, wherein said semiconductor device is an electrode.
  3. 3. The semiconductor device according to claim 1, wherein said first and second gate electrodes are covered via said first and second gate insulating films provided around said one conductivity type and opposite conductivity type SOI substrates. The semiconductor device according to claim 1, wherein:
  4. 4. The first, second and third metal source / drain regions self-aligned with the first gate electrode, the one conductivity type and the opposite conductivity type SOI substrate, the one conductivity type and the opposite conductivity type. 2. The semiconductor device according to claim 1, further comprising a second impurity region and said second gate electrode.
  5. 5. A power supply voltage is applied to the second metal source / drain region, a ground voltage is applied to the third metal source / drain region, and an input voltage is applied to the first and second gate electrodes. 2. The semiconductor device according to claim 1, wherein an output voltage is taken out from said first metal source / drain region.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343686A (en) * 1992-06-04 1993-12-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0621455A (en) * 1992-06-30 1994-01-28 Sanyo Electric Co Ltd Thin-film transistor
JPH07169848A (en) * 1993-12-15 1995-07-04 Hitachi Ltd Semiconductor device and manufacture of it
JPH07202211A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Manufacture of semiconductor device
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0864827A (en) * 1994-08-23 1996-03-08 Hitachi Ltd Semiconductor device and method of fabrication thereof
JPH11103057A (en) * 1997-03-17 1999-04-13 Toshiba Corp Semiconductor device
JP2000068517A (en) * 1998-08-24 2000-03-03 Nec Corp Manufacture of semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343686A (en) * 1992-06-04 1993-12-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0621455A (en) * 1992-06-30 1994-01-28 Sanyo Electric Co Ltd Thin-film transistor
JPH07169848A (en) * 1993-12-15 1995-07-04 Hitachi Ltd Semiconductor device and manufacture of it
JPH07202211A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Manufacture of semiconductor device
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0864827A (en) * 1994-08-23 1996-03-08 Hitachi Ltd Semiconductor device and method of fabrication thereof
JPH11103057A (en) * 1997-03-17 1999-04-13 Toshiba Corp Semiconductor device
JP2000068517A (en) * 1998-08-24 2000-03-03 Nec Corp Manufacture of semiconductor device

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