JP2002016258A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2002016258A
JP2002016258A JP2000197634A JP2000197634A JP2002016258A JP 2002016258 A JP2002016258 A JP 2002016258A JP 2000197634 A JP2000197634 A JP 2000197634A JP 2000197634 A JP2000197634 A JP 2000197634A JP 2002016258 A JP2002016258 A JP 2002016258A
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Japan
Prior art keywords
effect transistor
substrate
type
semiconductor
soi substrate
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JP2000197634A
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JP4828682B2 (en
Inventor
Takehide Shirato
白土猛英
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Takehide Shirato
白土 猛英
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Abstract

PROBLEM TO BE SOLVED: To form an SOI-structure C-MOS semiconductor device which controls back channel leak and whose integration, reliability and speed are high. SOLUTION: In the SOI-structure C-MOS semiconductor device, metal source-drain regions (9a, 9b, 9c, 9d) composed of metal layers are formed on a one-conductivity-type SOI substrate (3) and an opposite-conductivity-type SOI substrate (4) installed via an insulating film on a one-conductivity-type semiconductor substrate 1, and source drain regions (6, 7, 8) composed of impurity diffusion layers are each formed on the respective SOI substrates, as well as a one-conductivity-type MIS field-effect transistor and an opposite-conductivity-type MIS field-effect transistor having a structures in which low-resistance-metal gates (11, 12) are embedded via high-permittivity gate oxide films 10 on the SOI substrate between the metal source drain regions are formed. In the one-conductivity-type MIS field-effect transistor, and opposite-conductivity-type impurity region 19, which is formed on the one-conductivity-type semiconductor substrate in the immediately lower part is used as a back channel gate electrode, the metal source region 9a is connected, and source voltage is applied. In the opposite- conductivity-type MIS field-effect transistor, the one-conductivity-type semiconductor substrate is used as a back channel gate electrode, and a constant voltage is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an SOI structure, and more particularly to a short channel C-MOS semiconductor device having an SOI structure having high integration, high speed and high reliability.
Conventionally, MIS of N channel and P channel of SOI structure
With respect to a C-MOS semiconductor device including a field effect transistor, when a voltage different from the off voltage of the MIS field effect transistor is applied to a conductor (semiconductor substrate or lower wiring) under the SOI substrate, a back channel is formed on the bottom surface of the SOI substrate. And a back channel leak occurs. In order to improve this, an MIS field effect transistor of the opposite conductivity type is formed on the one conductivity type SOI substrate on the one conductivity type SOI substrate. An MIS field-effect transistor of one conductivity type is formed on the SOI substrate of the opposite conductivity type on the impurity region of the opposite conductivity type formed on the substrate, and the off voltage of the MIS field-effect transistor is reduced by the semiconductor substrate of the one conductivity type and the impurity of the opposite conductivity type. Was applied to the area. However, the impurity region of the opposite conductivity type was not formed in a self-aligned manner in the MIS field-effect transistor of one conductivity type, and a special voltage application region had to be provided. Since the MIS field-effect transistor is formed in the SOI structure, the junction capacitance and the depletion layer capacitance of the source / drain region can be reduced, but the resistance of the source / drain region and the gate electrode cannot be reduced. However, there were drawbacks such as that high speed could not be achieved. Accordingly, a highly integrated and highly reliable SOI structure C-MO that can reduce the resistance of each element, achieve higher speed, and completely control the back channel leakage is provided.
There is a need for a means that can form an S semiconductor device.

[0002]

2. Description of the Related Art FIG. 12 is a schematic side sectional view of a conventional semiconductor device.
In, SIMOX (Separati-on byIm
plantedOxygen) method.
Semiconductor integration of C-MOS with SOI structure using oxide film
A part of the circuit is shown, 51 is an n-type silicon (Si) base
Plate, 52 is a SIMOX-formed oxide film, 53 is an n-type SOI group
Board, 54 is a p-type SOI substrate, 55 is for element isolation region formation
Trench and buried oxide film, 56 is n-type source / drain
Region, 57 is a p-type source / drain region, 58 is n+ Type source
Drain region, 59 is p+ Source / drain region, 60 is p
Type impurity region (back channel gate electrode), 61 is p+ 
Type impurity region (contact region), 62 is a gate oxide film
(SiOTwo), 63 is the gate electrode (polySi / WSi), 64 is the base
Oxide film, 65 is sidewall, 66 is acid for impurity blocking
Oxide film, 67 is a PSG film, 68 is a barrier metal (Ti / TiN),
69 is a plug (W), 70 is a barrier metal (Ti / TiN), 71
Indicates AlCu wiring, and 72 indicates barrier metal (Ti / TiN).
You. In the figure, the bottom is placed in an n-type silicon substrate 51.
Due to the oxide film 52 formed by implantation of oxygen ions,
Trench and buried oxide film for surface isolation
Thin film n-type SOI substrate insulated in island form by 55
53 and a p-type SOI substrate 54 are formed.
A self-aligned gate electrode 63 is formed on the I-substrate 54
Self-contained in n-type source / drain region 56 and sidewall 65
Aligned n+ Type source / drain region 58
-Channel MIS field-effect transistor with LDD structure
Is formed, and a SIMO is formed under the p-type SOI substrate 54.
P-type impurity region (back gate) via X-forming oxide film 52
Electrode) 60 is formed widely and p + Type impurity region (contour
A ground voltage is applied via the
A self-aligned gate electrode 63 is formed on the SOI substrate 53.
The p-type source / drain region 57 and sidewall 65
P+ Type source / drain region 59
P-channel MIS field-effect transistor with LDD structure
A transistor is formed and an SI is formed under the n-type SOI substrate 53.
An n-type silicon substrate 51 (this
The power supply voltage is applied to the
(Not shown). Accordingly
To form a source / drain region surrounded by an insulating film
Reduction of junction capacitance due to the capability, complete emptying of SOI substrate
Depletion layer capacity reduction and sub-thread
Reduction of threshold voltage, etc. by improving the shoulder characteristics
N channel formed on a normal bulk wafer by
C- composed of a P-channel MIS field-effect transistor
Higher speed and lower power are possible compared to MOS.
In addition, N channel and P channel MIS
Back channel leakage, a problem unique to field effect transistors
In the semiconductor substrate and the impurity region of the opposite conductivity type.
Apply the power supply voltage and the ground voltage, and keep them off.
And high reliability is also possible. I
However, a P-channel MIS formed on an n-type SOI substrate
The back channel gate electrode of the field effect transistor is n
N-type silicon substrate
Since the power supply voltage only needs to be applied from the back, the area does not increase.
Although there is no problem, the N channel formed on the p-type SOI substrate
Back channel of MIS field effect transistor
The gate electrode is a p-type impurity region formed on an n-type silicon substrate.
Each contact area requires a special contact area.
However, there is a disadvantage that the degree of integration does not increase because it is necessary.

[0003]

The problem to be solved by the present invention is, as shown in the conventional example, the problem of the N-type SOI structure.
The back channel leakage, which is a problem specific to the channel and P channel MIS field-effect transistors, is obtained by applying a power supply voltage and a ground voltage to each of the back channel gate electrodes of the one conductivity type semiconductor substrate and the opposite conductivity type impurity region, It can be prevented by keeping each in the off state (if the semiconductor substrate is of the opposite conductivity type, the applied voltage may be reversed), but if the opposite conductivity type impurity region is used as the back channel gate electrode, the MIS electric field Since an impurity region of the opposite conductivity type wider than the effect transistor must be provided and a contact region for applying a predetermined voltage from the surface of the semiconductor substrate must be formed, a highly integrated S region is formed.
That is, a short channel C-MOS semiconductor device having an OI structure could not be formed.

[0004]

The object of the present invention is to provide a semiconductor substrate, a first insulating film provided on the semiconductor substrate, and a semiconductor layer (SOI substrate) provided on the first insulating film.
A trench for isolating the semiconductor layer (SOI substrate) in an island shape, a second insulating film embedded in the trench,
An impurity region having a conductivity type opposite to that of the semiconductor substrate provided on the semiconductor substrate below the semiconductor layer (SOI substrate); and a MIS field-effect transistor provided on the semiconductor layer (SOI substrate). This problem can be solved by the SOI-structure C-MOS semiconductor device of the present invention in which the impurity region is connected to the source region of the MIS field-effect transistor through an opening provided in a part of the insulating film. .

[0005]

[Operation] That is, in the semiconductor device of the present invention, n
A pair of metal source / drain regions are provided on an oxide film formed by implanting oxygen ions into a silicon substrate of a p-type. A substrate is provided, an n + -type source / drain region is provided on a p-type SOI substrate in contact with the opposed metal source / drain region, and an n-type source / drain region is provided in contact with the n + -type source / drain region. In addition, a gate oxide film is provided on the p-type SOI substrate and on the side wall of the metal source / drain region opposed thereto, and a gate electrode having a barrier metal is buried flat through the gate oxide film. Part of the source region is connected to ap + -type impurity region (contact region) through an opening in the oxide film,
A source voltage is applied to the impurity region (back channel gate electrode), and an N-channel MIS field-effect transistor having a structure in which the periphery is completely insulated and separated by a trench for forming an element isolation region and a buried oxide film is formed. Have been. On the other hand, a pair of metal source / drain regions are provided on an oxide film formed by implanting oxygen ions into an n-type silicon substrate. SOI substrate is provided, ap + -type source / drain region is provided on an n-type SOI substrate in contact with the opposed metal source / drain region, and an n-type SOI substrate is provided.
A gate oxide film is provided on the I-substrate and on the side walls of the metal source / drain regions facing each other. A gate electrode having a barrier metal is buried flat through the gate oxide film, and a trench for forming an element isolation region is formed around the gate electrode. In addition, a P-channel MIS field-effect transistor having a structure completely insulated and separated by a buried oxide film is formed, and a power supply voltage is applied to an n-type silicon substrate serving as a back channel gate electrode. (The metal source / drain region of the present invention is different from a normal metal source / drain region in that it is a region composed of only a metal film or an alloy film that does not include an impurity region.) Therefore, in an N-channel MIS field-effect transistor, Self-aligned p-type impurity region (back channel gate electrode) in trench for forming element isolation region in which oxide film is embedded
Can be formed, and a direct connection with a metal source region to which a source voltage can be applied immediately below the metal source region can be formed. When an on-voltage is applied to the gate electrode, the source voltage also increases. The ON voltage is also applied, so that the back channel current can flow though the amount is small. When the OFF voltage is applied to the gate electrode, the ground voltage is applied to the source voltage and the back voltage is applied. Since channel leak can be completely prevented, an N-channel MIS field-effect transistor having an SOI structure linked to the gate electrode can be obtained. Further, a special voltage application region does not need to be formed. On the other hand, in a P-channel MIS field-effect transistor, an n-type silicon substrate is used as a back-channel gate electrode, and a power supply voltage is always applied. Therefore, an off-voltage is applied even when an on-voltage is applied to the gate electrode. It is possible to prevent back channel leaks even when the operation is in progress. Further, only a channel region, a low-concentration source / drain region (no P-channel MIS field-effect transistor is formed) and an extremely minute high-concentration source / drain region are formed on the fully depleted SOI substrate, and most of the source region is formed. Since the drain region can be formed of a low-resistance conductive film (metal film or alloy film) instead of the impurity region, the depletion layer capacitance can be removed, the junction capacitance can be reduced (almost zero), and the resistance of the source / drain region can be reduced. In addition, since the source / drain region due to impurities can be formed before the formation of the gate electrode, a low-resistance gate electrode made of a low-melting metal can be formed, and Ta 2 O 5 having a high dielectric constant is formed of a gate oxide film. The gate oxide film can be made thicker, and the gate electrode and SO
It is also possible to improve a small current leak between the I substrates and reduce the gate capacitance. That is, it is possible to obtain a C-MOS semiconductor device having an SOI structure having a back channel gate electrode which enables formation of a semiconductor integrated circuit with extremely high integration, high reliability, and high speed.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and FIG. FIG. 4 is a schematic side sectional view of a third embodiment of the present invention, FIG. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device of the present invention, and FIGS. It is sectional drawing. The same objects are denoted by the same reference numerals throughout the drawings. FIG. 1 shows a first example of the semiconductor device of the present invention.
1 is a schematic side sectional view of an embodiment of the present invention, showing a part of a C-MOS semiconductor integrated circuit having an SOI structure using an oxide film formed by a SIMOX method, wherein 1 denotes n of about 10 15 cm −3.
Type silicon substrate, 2 is a SIMOX formed oxide film (SiO 2 ) of about 0.1 μm, 3 is an n-type SOI substrate of about 0.1 μm thickness, 4 is a p-type SOI substrate of about 0.1 μm thickness, 5 is Trench and buried oxide film (Si
O 2 ) and 6 are n-type source / drain regions of about 10 17 cm -3 ;
10 20 cm -3 of about n + -type source and drain regions, 8 10 20
A p + type source / drain region of about cm -3 , 9a has a thickness of 0.4
9b is a metal source region of an N-channel MIS field-effect transistor having a thickness of about 0.3 μm, and 9b is a metal drain region of an N-channel MIS field-effect transistor having a thickness of about 0.3 μm.
c is a metal source region of a P-channel MIS field-effect transistor having a thickness of about 0.3 μm, 9 d is a metal drain region of a P-channel MIS field-effect transistor having a thickness of about 0.3 μm, and 10 is a gate oxide film (SiO 2 / SiO) of about 15 nm. Ta 2 O
5 ), 11 is a barrier metal (TiN) of about 20 nm, 12 is a gate electrode (Al) having a gate length of about 0.2 μm, 13 is a phosphosilicate glass (PSG) film of about 0.8 μm, and 14 is a barrier metal of about 50 nm ( Ti / TiN), 15 is a plug (W), 16 is a barrier metal (Ti / TiN) of about 50 nm, 17 is an AlCu wiring of about 0.8 μm, 18 is a barrier metal (Ti / TiN) of about 50 nm, and 19 is 10
Reference numeral 20 denotes a p-type impurity region (back channel gate electrode) of about 16 cm -3, and reference numeral 20 denotes a p + -type impurity region (contact region) of about 10 20 cm -3 . In FIG. 1, a pair of metal source / drain regions (9a, 9b) are provided on an oxide film 2 formed by implanting oxygen ions into an n-type silicon substrate 1, and these metal source / drain regions (9a, 9b) are provided. 9b), a p-type SOI substrate 4 is provided in contact with a part of the metal source / drain region (9a, 9b), and the p-type SOI substrate comes in contact with the opposing metal source / drain region (9a, 9b).
An n + -type source / drain region 7 is provided on the substrate 4, an n-type source / drain region 6 is provided in contact with the n + -type source / drain region 7, and an n + -type source / drain region 6 is provided. A gate oxide film (SiO 2 / Ta 2 O 5 ) 10 is provided on the side walls of the drain regions (9a, 9b), and a barrier metal (TiN) is interposed through the gate oxide film (SiO 2 / Ta 2 O 5 ) 10. A gate electrode (Al) 12 having 11 is buried flat, and a part of the metal source region 9a is a p + -type impurity region (contact region) through an opening of the oxide film 2.
, A source voltage is applied to the p-type impurity region (back channel gate electrode), and the periphery is completely insulated and separated by a trench for forming an isolation region and a buried oxide film (SiO 2 ) 5. N channel MI having
An S field effect transistor is formed. On the other hand, a pair of metal source / drain regions (9c, 9c) are formed on the oxide film 2 formed by implanting oxygen ions into the n-type silicon substrate 1.
9d) is provided, and the metal source / drain regions (9c,
9d), an n-type SOI substrate 3 is provided in contact with a part of the metal source / drain regions (9c, 9d), and is in contact with opposing metal source / drain regions (9c, 9d). p + -type source and drain region 8 is provided, also n-type SOI substrate 3 and on the opposing metal source drain region (9c, 9d) gate oxide layer on the sidewall of the (SiO 2 / Ta 2 O 5 ) 10 and the gate oxide film (Si
A gate electrode (Al) 12 having a barrier metal (TiN) 11 is buried flat through O 2 / Ta 2 O 5 ) 10 and a trench for forming an element isolation region and a buried oxide film (Si)
O 2 ) 5 forms a P-channel MIS field effect transistor having a structure completely insulated and separated. (Here, the n-type silicon substrate is a back channel gate electrode, and although not shown, a power supply voltage is applied.) Therefore, in the N-channel MIS field-effect transistor, an oxide film is buried. A self-aligned p-type impurity region (back channel gate electrode) can be formed in a deep trench for forming an element isolation region, and a direct connection with a metal source region to which a source voltage can be applied immediately below the metal source region can be formed. When the on-voltage is applied to the gate electrode, the source voltage also increases, so that the on-voltage is also applied to the back channel gate electrode. When a voltage is applied, the ground voltage is applied to the source voltage, and the Since channel leakage can be completely prevented, an N-channel MIS field-effect transistor having an SOI structure linked to the gate electrode can be obtained. Further, since a special voltage application region does not need to be formed, the device can be formed very finely. On the other hand, in a P-channel MIS field-effect transistor, an n-type silicon substrate is used as a back channel gate electrode, and a power supply voltage is always applied. Therefore, an off-voltage is applied even when an on-voltage is applied to the gate electrode. The back channel leak can be prevented even when it is in operation.
Further, only a channel region, a low-concentration source / drain region (no P-channel MIS field-effect transistor is formed) and an extremely minute high-concentration source / drain region are formed on the SOI substrate, and most of the source / drain region is formed as an impurity region. Instead, it can be formed of a low-resistance conductive film (metal film or alloy film), so that the junction capacitance can be reduced (almost zero) and the resistance of the source / drain region can be reduced. Since it can be formed before the formation of the gate oxide film, it is possible to form a low-resistance gate electrode made of a low-melting-point metal (Al), and since Ta 2 O 5 having a high dielectric constant can be used as the gate oxide film, the gate oxide film can be formed. It is possible to improve the minute current leakage between the gate electrode and the SOI substrate and to reduce the gate capacitance. As a result, S which has both high integration, high reliability and high speed
A C-MOS semiconductor device having an OI structure can be obtained.

FIG. 2 shows a second embodiment of the semiconductor device according to the present invention, which is a part of a C-MOS semiconductor integrated circuit having an SOI structure using an oxide film formed by the SIMOX method as in FIG. , 1 to 8 and 13 to 20 are the same as those in FIG. 1, 21 is a gate oxide film (SiO 2 ), and 22 is a gate electrode (poly).
Si / WSi), 23 is a base oxide film (SiO 2 ), 24 is a sidewall (SiO 2 ), 25 is an oxide film for impurity blocking (SiO 2 ),
26 indicates a p-type source / drain region. In the figure, both the N-channel and the P-channel MIS field-effect transistors use the same LDD as the conventional one using the sidewall.
Since the MIS field-effect transistor having the structure is formed and the metal source / drain region is not formed, a plug of the source region of the N-channel MIS field-effect transistor is provided extending to the p + -type impurity region. Except for this, a SOI structure C-MOS semiconductor device having the same structure as that of FIG. 1 is formed. In this embodiment, even if a conventional MIS field-effect transistor is used, the same effect as that of the first embodiment can be obtained although the speed is reduced.

FIG. 3 is a schematic side sectional view of a semiconductor device according to a third embodiment of the present invention. As in FIG. 1, an MIS field effect of low voltage driving and high voltage driving using an oxide film formed by the SIMOX method is used. 2 shows a part of a C-MOS semiconductor integrated circuit having an SOI structure incorporating a transistor,
18 and 26 are the same as those in FIGS. 1 and 2, 10a is a gate oxide film (SiO 2 / Ta 2 O 5 ) of a P-channel MIS field-effect transistor driven at a high voltage, and 12a is a P-channel M transistor driven at a high voltage.
Gate electrode (Al) of IS field effect transistor, 27 is p
-Type silicon substrate, 28 denotes an n-type impurity region (back channel gate electrode), and 29 denotes an n + -type impurity region (contact region). In the figure, a low-voltage driven N-channel and P-channel MIS field-effect transistor and a high-voltage driven P-channel MIS field-effect transistor are provided, and p-type silicon is used as a back-channel gate electrode of the N-channel MIS field-effect transistor. A ground voltage is applied to the substrate 27 (not shown), and an n + -type impurity region 29 is formed in an n-type impurity region 28 serving as a back channel gate electrode of a P-channel MIS field-effect transistor (short gate length) driven at low voltage. A source voltage (low power supply voltage) is applied from the metal source region 9c via the
Except that a source voltage (high power supply voltage) is applied from a metal source region 9e to an n-type impurity region 28 serving as a back channel gate electrode of an IS field-effect transistor (having a long gate length) via an n + -type impurity region 29. Are formed in the same structure as in FIG. In the present embodiment, the semiconductor substrate to be used is limited to the p-type and the n-type impurity region is restricted to the back channel gate electrode. However, the first embodiment is also applicable to the low-voltage and high-voltage driven C-MOS. Example effects can be obtained. (However, the effects of the P-channel MIS field-effect transistor and the N-channel MIS field-effect transistor are reversed.)

FIG. 4 is a schematic side sectional view of a semiconductor device according to a fourth embodiment of the present invention, in which low-voltage driving and high-voltage driving using an oxide film formed by a SIMOX method and a bonding oxide film. 2 to 18, 26, 27, and 29 denote the same parts as those shown in FIGS. 1, 2, and 3, and show a part of a SOI-structure C-MOS semiconductor integrated circuit having a built-in MIS field-effect transistor. Is an oxide film (SiO 2 ) for bonding, 31
Indicates an n-type semiconductor layer (back channel gate electrode). In the figure, an oxide film is formed on a p-type silicon substrate 27.
An oxide film formed by implanting oxygen ions into a thinned n-type silicon substrate bonded through the thin film 30 through the n-type silicon substrate has an n-type SOI
The substrate 3 (partially formed as a p-type SOI substrate 4) and a lower n-type semiconductor layer 31 are separated from each other.
A low-voltage driven N-channel MIS field-effect transistor is provided on the substrate 4, a low-voltage and high-voltage driven P-channel MIS field-effect transistor is provided on the n-type SOI substrate 3,
An n + -type impurity region is formed in an n-type semiconductor layer 31 serving as a back channel gate electrode of an N-channel MIS field-effect transistor.
A source voltage (ground voltage) is applied from the metal source region 9a through 29, and n + is applied to the n-type semiconductor layer 31 serving as the back channel gate electrode of the P-channel MIS field-effect transistor (short gate length) driven at low voltage. Source voltage (low power supply voltage) from the metal source region 9c via the p-type impurity region 29
Is applied to an n-type semiconductor layer 31 serving as a back-channel gate electrode of a P-channel MIS field-effect transistor (having a long gate length) driven by high voltage via an n + -type impurity region 29,
The structure is similar to that of FIG. 3 except that a source voltage (high power supply voltage) is applied from the metal source region 9e. In the present embodiment, a desired source voltage can be applied by using the semiconductor layer under the SIMOX oxide film as a simple conductor regardless of the type of the underlying semiconductor substrate, and even in a low-voltage and high-voltage driven C-MOS. The effect of the first embodiment can be obtained. (However, the effects of the P-channel MIS field-effect transistor and the N-channel MIS field-effect transistor are reversed.)

Note that the present invention is not limited to the above description.
A metal film, an alloy film, two or more metal films including a barrier metal may be used, the gate electrode may be a normal polycide gate (polySi / WSi), and a contact region for a back channel gate electrode may be formed. Regarding the high-concentration impurity region, it is always necessary at the present time to improve the Schottky barrier in the case of the n-type and to establish a connection with the ohmic wiring body, but it is not necessary to omit it in the case of the p-type. It is possible.

Next, a method for manufacturing a semiconductor device according to the present invention.
One embodiment will be described with reference to FIGS. 5 to 11 and FIG.
I will tell. However, here, in forming the semiconductor device of the present invention,
Only the manufacturing method related to semiconductor integrated circuits.
Various mounted elements (other transistors, resistors, capacitors
Etc.) are not described. FIG. 5 A thermal oxide film (SiO 2) of about 10 nm is formed on an n-type silicon substrate 1.Two) 32
To form Then 10 18cm-2A small dose of oxygen
Inject ON. Then NTwo Atmosphere, about 1250 ° C for about 1 hour
About 0.1 μm n-type SOI
The plate 3 and the SIMOX formed oxide film 2 of about 0.1 μm are formed.
To achieve. (A commercially available SOI wafer may be used.) FIG. 6 Next, a nitride film (SiThree
NFour To grow 33). Then normal photolithography
Using a resist (not shown) as a mask layer
The nitride film 33, the oxide film 32, the n-type SOI substrate 3, the SIM
OX forming oxide film 2 and n-type silicon substrate 1 (0.5 μm
Trench) by selective anisotropic dry etching
To form Next, the resist (not shown) is removed.
Next, a chemical vapor deposition oxide film (SiOTwoGrow anisotropic
Lie-etched and buried in trench
5 is formed. Fig. 7 Next, using ordinary photolithography technology,
SIMOX forming acid as a mask (not shown)
Boron is selectively implanted into the n-type silicon substrate 1 under the oxide film 2.
Injection. Continuously selectively boron on the n-type SOI substrate 3
The element is ion-implanted. Next, the resist (not shown) is removed.
Leave. Then N at about 1100 ° CTwoTo add annealing
Of the p-type impurity region (back channel gate electrode) 19
Forming a part of the n-type SOI substrate 3 into a p-type SOI substrate
Convert to Fig. 8 Next, using ordinary photolithography technology,
The nitride film 33 is selectively formed using a mask (not shown) as a mask layer.
Anisotropic dry etching with metal source drain
Open the formation area. Next, the resist (not shown) is removed.
Leave. Then use normal photolithography technology
And a resist (not shown) and a tray embedded with an oxide film.
P-type SOI group using the mask 5 and the nitride film 33 as a mask layer.
The plate 4 is ion-implanted with phosphorus. Then resist (shown
Are removed. Then N at 950 ° C for about 30 minutesTwoAnnealing
Is diffused in the lateral direction by adding
An in-region 6 is formed. Then normal photolithography
Resist (not shown) and oxide film
With the trench 5 and the nitride film 33 embedded as mask layers,
Arsenic is ion-implanted into the p-type SOI substrate 4. Then
The dist (not shown) is removed. Then the normal photo library
Using lithography technology, resist (not shown), acid
The trench 5 in which the oxide film is embedded and the nitride film 33 are used as a mask layer.
Then, boron is ion-implanted into the n-type SOI substrate 3.
Next, the resist (not shown) is removed. Then 900 ° C
About 20 minutes NTwoLateral expansion by adding annealing
Sprinkle, n+ Type source / drain region 7 and p+ Type source
A drain region 8 is formed. FIG. 9 Next, the oxide film 32 and the SOI substrate (3, 4) immediately below are anisotropically.
Dry etching. Next, normal photolithography
Using a fee technology, a resist (not shown) is used as a mask layer
As the source of an N-channel MIS field-effect transistor.
P-type impurity region (back channel gate)
Boron is ion-implanted into a part of the electrode 19. Continuous SI
Selectively anisotropic dry etching of MOX forming oxide film 2
I do. Next, the resist (not shown) is removed. Then
N for about 10 minutes at 900 ° CTwoBy adding annealing, p
+ A type impurity region (contact region) 20 is formed. Next
To grow a tungsten film (W) by sputtering. Next
Ide chemical mechanical polishing (C-ChemicalMecha
nicalPabbreviated as CMP hereinafter
Buried flat, metal source drain region
(9a, 9b, 9c, 9d). Figure 10 Next, use normal photolithography technology
Then, an oxide film is formed using a resist (not shown) as a mask layer.
Oxidation of a part of the buried element isolation region forming trench 5
About 0.2μm of film (lead part for connecting gate electrode)
Anisotropically dry-etched and continuously left nitride film 33
Then, the oxide film 32 is subjected to anisotropic dry etching. Then
The dist (not shown) is removed. Next, a 15nm game
Oxide film 10 (SiOTwo/ TaTwoOFive Grow). Then about 20nm
Degree of barrier metal (TiN) 11 and gate of about 0.2μm
An Al film 12 serving as an electrode is grown by continuous sputtering. Next
Buried flat by chemical mechanical polishing (CMP)
A gate electrode 12 is formed. Fig. 11 Next, the phosphorous silicate glass
(PSG) film 13 is grown. Then normal photolithography
Masks resist (not shown) using luffy technology
As a layer, the PSG film 13 is selected by anisotropic dry etching.
Alternatively, an electrode contact window is opened. Then to spatter
Then, Ti and TiN 14 serving as barrier metals are sequentially grown.
Next, the entire surface is tanned by a blanket method of chemical vapor deposition.
Gusten film is grown and filled by anisotropic dry etching
A plug (W) 15 is formed. Fig. 1 Next, barrier metal Ti, TiN 16
Grow sequentially. Next, by sputtering, Al
Grow 17 (including several percent of Cu) to about 0.8 μm. Then
Sputtering of Ti and TiN 18 to become barrier metal sequentially by sputtering
grow up. Then use normal photolithography technology.
Using a resist (not shown) as a mask layer
Anisotropic metal, Al (including several% Cu) and barrier metal
AlCu wiring 17 is formed by reactive dry etching,
Complete the installation. In the above manufacturing method, some processes
Buried layer by anisotropic dry etching
However, all of these processes are
Polishing (CMP) can be performed, and
When determining the threshold voltage of the P-MOS, an n-type SOI group
Although the plate is used as it is, the ion implantation of phosphorus
The concentration of the OI substrate may be controlled. In addition, the above manufacturing method
In order to form the SOI structure,
Oxidized two layers of semiconductor substrate
So-called bonded SOI wafers bonded through a film
The invention of the present application is established even if an eher is used.

[0012]

As described above, according to the semiconductor device of the present invention, a part of the semiconductor device is in contact with the one conductivity type and the opposite conductivity type SOI substrate provided on the one conductivity type semiconductor substrate via the insulating film. A metal source / drain region made of a metal layer is formed, a source / drain region made of an impurity diffusion layer is formed in each SOI substrate, and a gate oxide film having a high dielectric constant is formed on the SOI substrate between the metal source / drain regions. A MIS field-effect transistor of one conductivity type and an opposite conductivity type having a structure in which a gate electrode of a low-resistance metal is buried through the MIS field-effect transistor of one conductivity type is formed. The opposite conductivity type impurity region formed in the semiconductor substrate is used as a back channel gate electrode, the metal source region is connected, a source voltage is applied, and the opposite conductivity type is formed. Of the MIS field-effect transistor, a first conductivity type semiconductor substrate and a back-channel gate electrode, C over MOS semiconductor device of SOI structure constant voltage is applied is formed. Therefore, in the SOI structure, the resistance of the source / drain region is reduced and the junction capacitance is reduced by forming the metal source / drain region, and the Ta having a high dielectric constant is used.
Improvement of minute current leak between gate electrode and SOI substrate and reduction of gate capacitance by using 2 O 5 gate oxide film, removal of depletion layer capacitance by using fully depleted SOI substrate, back connected to metal source region It is possible to control the back channel leak and the like by finely forming the channel gate electrode (impurity region). That is, it is possible to obtain an SOI type C-MOS semiconductor device having a back channel gate electrode capable of forming a highly integrated, highly reliable and high speed semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention.

FIG. 3 is a schematic side sectional view of a third embodiment of the semiconductor device of the present invention.

FIG. 4 is a schematic side sectional view of a fourth embodiment of the semiconductor device according to the present invention;

FIG. 5 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a process sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 12 is a schematic side sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 n-type silicon (Si) substrate 2 SIMOX formation oxide film (SiO 2 ) 3 n-type SOI substrate 4 p-type SOI substrate 5 trench for forming element isolation region and buried oxide film (SiO 2 ) 6 n-type Source / drain region 7 n + type source / drain region 8 p + type source / drain region 9a Metal source region (W) of N channel MIS field effect transistor 9b Metal drain region (W) of N channel MIS field effect transistor 9c P channel MIS electric field Metal source region (W) of the effect transistor 9d Metal drain region (W) of the P-channel MIS field-effect transistor 9e Metal source region (W) of the P-channel MIS field-effect transistor driven at a high voltage 9f P-channel MIS electric field driven at a high voltage Effect transistor metal drain region (W) 10 Gate oxide film (SiO 2 / Ta 2 O) 5 ) 10a Gate oxide film (SiO 2 / Ta 2 O 5 ) of P-channel MIS field-effect transistor driven by high voltage 11 Barrier metal (TiN) 12 Gate electrode (Al) 12a P-channel MIS field-effect transistor driven by high voltage Gate electrode (Al) 13 Phosphosilicate glass (PSG) film 14 Barrier metal (Ti / TiN) 15 Plug (W) 16 Barrier metal (Ti / TiN) 17 AlCu wiring 18 Barrier metal (Ti / TiN) 19 p-type impurity region (Back channel gate electrode) 20 p + impurity region (contact region) 21 gate oxide film (SiO 2 ) 22 gate electrode (polySi / WSi) 23 base oxide film (SiO 2 ) 24 sidewall (SiO 2 ) 25 impurity block Oxide film (SiO 2 ) 26 P-type source / drain region 27 P-type silicon (Si) substrate 28 N-type impurity region (back channel gate electrode) 29 n + -type impurity region (contact region) 30 Oxidation for bonding Film (SiO 2 ) 31 n-type semiconductor layer (back channel gate electrode) 32 oxide film (SiO 2 ) 33 nitride film (Si 3 N 4 )

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/8238 H01L 21/76 D 27/092 27/08 321B 27/08 331 29/78 613A 616T 617K 621 F-term (reference) 4M104 AA09 BB30 CC05 DD03 DD75 FF01 FF18 GG09 5F032 AA35 AA44 BA01 CA14 CA17 DA07 DA25 DA30 DA33 DA43 DA53 DA60 DA71 DA78 5F048 AA01 AA07 AC01 AC03 BA09 BB05 BB08 BB09 BF11 BF11 BF11 BF11 BF11 BF11 AA03 AA06 AA12 BB04 CC02 DD05 DD13 DD24 EE01 EE03 EE05 EE09 EE30 EE31 EE44 FF01 FF02 FF09 GG02 GG12 GG25 HJ01 HJ04 HJ13 HJ15 HJ23 NN02 HK02 HK04 HK05 HK06 HK09 HK14 HL01 HM04

Claims (5)

[Claims]
1. A semiconductor substrate, a first insulating film provided on the semiconductor substrate, a semiconductor layer (SOI substrate) provided on the first insulating film, and the semiconductor layer (SOI substrate) , An insulating film embedded in the trench, and the semiconductor layer (SOI substrate)
An impurity region having a conductivity type opposite to that of the semiconductor substrate provided on the semiconductor substrate below; and a MIS field-effect transistor provided on the semiconductor layer (SOI substrate). The semiconductor device according to claim 1, wherein the impurity region is connected to a source region of the MIS field-effect transistor via a provided opening.
2. The semiconductor device according to claim 1, wherein said semiconductor layer (SOI substrate) comprises an upper layer portion of said semiconductor substrate which is insulated and separated by a first insulating film provided inside said semiconductor substrate. 2. The semiconductor device according to 1.
3. The SOI substrate comprises an upper layer of the semiconductor layer which is insulated and separated by a first insulating film provided inside the semiconductor layer, and an impurity region comprises a lower layer of the semiconductor layer. The semiconductor layer having a structure in which a lower layer portion of the semiconductor layer is connected to a source region of a MIS field-effect transistor provided on the SOI substrate through an opening provided in a part of the insulating film of the first aspect. 2. The semiconductor device according to claim 1, wherein said semiconductor device is provided on a semiconductor substrate via a third insulating film.
4. The semiconductor device according to claim 1, wherein the MIS field-effect transistor is an SOI transistor.
A metal source / drain region formed of a metal layer provided partially in contact with the I substrate; a source / drain region formed of an impurity diffusion layer provided on the SOI substrate; In a MIS field-effect transistor of one conductivity type, which is formed by a gate electrode buried with a gate oxide film interposed therebetween, an opposite conductivity type impurity region provided in the one conductivity type semiconductor substrate immediately below is used as a back channel gate electrode. , Connected to the metal source region, a source voltage is applied, and the opposite conductivity type M
2. The semiconductor device according to claim 1, wherein a constant voltage is applied to the IS field effect transistor using a one conductivity type semiconductor substrate as a back channel gate electrode.
5. A step of forming an SOI substrate on a semiconductor substrate with an insulating film interposed therebetween, a step of insulatingly separating the SOI substrate into islands, and forming an impurity region of an opposite conductivity type in the semiconductor substrate below the SOI substrate. Forming step and forming M on the SOI substrate.
A semiconductor comprising a step of forming an IS field effect transistor and a step of opening a part of the insulating film to connect a source region and the impurity region of the MIS field effect transistor. Device manufacturing method.
JP2000197634A 2000-06-30 2000-06-30 Semiconductor device Expired - Fee Related JP4828682B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9240354B2 (en) 2012-11-14 2016-01-19 Globalfoundries Inc. Semiconductor device having diffusion barrier to reduce back channel leakage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0832040A (en) * 1994-07-14 1996-02-02 Nec Corp Semiconductor device
JPH09326492A (en) * 1996-06-06 1997-12-16 Nippon Telegr & Teleph Corp <Ntt> Lateral insulated gate field-effect transistor and semiconductor substrate therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0832040A (en) * 1994-07-14 1996-02-02 Nec Corp Semiconductor device
JPH09326492A (en) * 1996-06-06 1997-12-16 Nippon Telegr & Teleph Corp <Ntt> Lateral insulated gate field-effect transistor and semiconductor substrate therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9240354B2 (en) 2012-11-14 2016-01-19 Globalfoundries Inc. Semiconductor device having diffusion barrier to reduce back channel leakage
US9406569B2 (en) 2012-11-14 2016-08-02 Globalfoundries Inc. Semiconductor device having diffusion barrier to reduce back channel leakage

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