JPH10135348A - Field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the usable operating voltage of a field effect semiconductor device in which a gate electrode and a well area are electrically connected to each other, by connecting a resistor between the gate electrode and the well area. SOLUTION: In a field effect semiconductor device, a field effect semiconductor element is provided in a well area 2 provided on a semiconductor substrate 1, and a resistor 4 is connected between a gate electrode 5 of the semiconductor element and the well area 2. The resistor 4 is constituted of, for example, the same polycrystalline silicon layer as that of the gate electrode 5. In addition, TiN is used for a connecting conductor layer 6 which connects the resistor 4 to a well contact area 3, and Al is used for a connecting wiring layer 7 which connects the electrode 5 to the resistor 4. Consequently, the forward bias voltage applied across a source and the well area 2 can be controlled against the gate voltage in a self-correcting way. Therefore, the usable operating voltage of a field effect semiconductor device can be raised, because the forward bias current can be reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect type semiconductor device, and more particularly to a MOS type semiconductor device which biases a well region in a self-correcting manner with respect to a gate voltage.

[0002]

2. Description of the Related Art Conventionally, MOSFETs have been widely used as basic elements of large-capacity semiconductor memory devices and digital integrated circuit devices.
_th ) and a reduction in power consumption.

A CMOS structure is used to meet such a demand for low power consumption. However, in addition to the CMOS structure, in order to control an off-leak current and realize a low threshold voltage, a gate electrode is used. And a well region are connected, and a forward bias is applied between the source and the well region together with the gate voltage.

For example, by connecting a contact portion of a polycrystalline silicon gate electrode and a well contact region provided in a well region with a connection wiring layer via a W plug or the like, a gate voltage and a source-well region are sequentially formed. A bias can be applied.

In such a driving method, the off-leak current when no gate voltage is applied is the same as the normal case, but the threshold voltage (V _th ) decreases due to the substrate bias effect as the gate voltage increases, There is an advantage that a large gate-source voltage is applied to the MOSFET to increase the driving capability.

Referring to FIG. 5, for example, the concentration (N _sub ) of the p-type well region is 1 × 10 ¹⁸
cm ⁻³ , channel length 0.15 μm n-channel type M
In the case of OSFET, the MOSF of the conventional normal structure shown by ●
As compared with ET, the drain current I _{d of the} MOSFET in which the gate electrode and the well region shown by a black square and a broken line are short-circuited to the well region
Becomes larger, and the saturation current when the gate voltage Vg is set to 1 V is increased by about one digit.

[0007]

However, in the case of such a driving method, the pn junction between the source and well regions is forward-biased during operation, so that it is used only in an extremely low voltage region of about 0.5 V or less. However, there is a problem that the saturation current is too small except for a special purpose and is not general purpose.

Referring to FIG. 5 again, the current flows through the pn junction between the source and the well region in this case.
Forward bias current I _fowardIs the black square and
R indicated by broken line_c= 0Ω, the gate voltage V_gTo
In the case of 1.0V, about 6 × 10^-FourA / μm current, immediate
That is, about 6 × 10 per 1 μm gate width of the gate electrode.^-FourA
Cannot be used because the current flows.

Accordingly, an object of the present invention is to further increase the usable voltage of a field effect type semiconductor device in which a gate voltage is electrically connected to a well region.

[0010]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. FIG.
1A is a diagram showing a schematic plan structure of a field-effect semiconductor device, and FIG. 1B is a cross-sectional view taken along a dashed line in FIG. 1A.

1 (a) and 1 (b) (1) In the field effect type semiconductor device, a field effect type semiconductor element is provided in a well region 2 provided in a semiconductor substrate 1 and a field effect type semiconductor device is provided. Device gate electrode 5
And a well 4 in which a resistor 4 is inserted.

As described above, by inserting the resistor 4, the forward bias voltage applied between the source and the well region 2 with respect to the gate voltage is controlled in a self-correcting manner, that is, the forward bias voltage is self-aligned depending on the magnitude of the current. The forward bias voltage can be adjusted so that the forward bias current I
_{Since the forward} can be greatly reduced, the usable operating voltage can be higher.

(2) The present invention is characterized in that, in the above (1), the gate voltage applied to the gate electrode 5 of the field effect type semiconductor device is 0.5 V or more.

[0014] As described above, the source-
By controlling the forward bias voltage applied between the well regions 2 in a self-correcting manner, it is possible to use the device in a more realistic voltage region where the gate voltage is 0.5 V or higher than before.

(3) Further, the present invention is characterized in that in the above (1) or (2), the resistor 4 is constituted by the same polycrystalline silicon layer as the gate electrode 5.

As described above, the resistor 4 is formed by the same polycrystalline silicon layer as the gate electrode 5, that is, by using a part of the polycrystalline silicon layer deposited for forming the gate electrode 5. Thereby, the manufacturing process can be simplified.

(4) The present invention is characterized in that in any one of the above (1) to (3), TiN is used as the connection conductor layer 6 for connecting the resistor 4 and the gate electrode 5. .

As described above, by using TiN having excellent heat resistance as the connection conductor layer 6, the heat treatment conditions in the subsequent steps are relaxed.

(5) The present invention is characterized in that in any one of the above (1) to (4), the semiconductor substrate 1 in which a single crystal semiconductor layer is provided on an insulator is used as the semiconductor substrate 1. And

As described above, the semiconductor substrate 1 in which the single crystal semiconductor layer is provided on the insulator, ie, the SOI
(Silicon on Insulator) By using the substrate, it is possible to suppress an increase in well capacity due to a change in well potential which changes in synchronization with a change in gate voltage, thereby suppressing a delay in operation speed. it can.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process according to a first embodiment of the present invention will be described with reference to FIGS. (A) of each drawing is a diagram showing a schematic plan structure of the field-effect semiconductor device, and (b) of each drawing is a cross-sectional view taken along a dashed line of (a) of each drawing. . Referring to FIGS. 2A and 2B, first, a shallow trench having a depth of about 0.4 μm for forming an element isolation region in a predetermined region of a p-type silicon substrate 11 having an impurity concentration of 1.0 × 10 ¹⁵ cm ^-3 Form a trench, Si
The shallow trench is buried with the buried oxide film 12 by depositing an O ₂ layer.

Next, boron (B) is, for example, 300 k
3 × 10 with eV acceleration energy ¹³cm^-2Dose
And then heat-treated at 950 ° C. for 30 minutes.
By doing so, a depth of 0.08 to 0.12 μm
Pure substance concentration is 1.0 × 10¹⁸cm^-3P-type well region 13
And a p-type well contact region 14 is formed.

Next, a gate oxide film 15 having a thickness of, for example, 4 nm is formed by thermal oxidation, and a polycrystalline silicon film having a thickness of, for example, 160 nm is deposited on the entire surface by CVD. Using a pattern (not shown) as a mask, 4 × 10 ¹⁵ cm ⁻² phosphorus (P) is selectively ion-implanted into the polycrystalline silicon layer in a region where a gate electrode is to be formed, for example, at an acceleration energy of 20 keV. On the other hand, a predetermined amount of phosphorus is selectively ion-implanted into the polycrystalline silicon layer in a region where a resistor is to be formed, according to a required resistance value.

Next, the polysilicon gate electrode 16 and the polysilicon resistor 17 are formed simultaneously by patterning the polysilicon layer by reactive ion etching (RIE).

3 (a) and 3 (b). Next, a photoresist pattern (not shown)
Using the monocrystalline silicon gate electrode 16 as a mask, for example, 1
At an acceleration energy of 0 keV, 1 × 10¹⁴cm ^-2Arsenic in
By ion-implanting (As), n^-Type LDD area
Area (Lightly Doped Drain) 18
Form.

Next, the thickness is formed on the entire surface by the CVD method.
For example, after depositing a 60 nm SiO ₂ film, the SiO ₂ film is anisotropically etched by reactive ion etching to form a side wall 19, and using the side wall 19 as a mask, for example, 40 k
The n ⁺ -type source / drain region 20 is formed by ion-implanting 2 × 10 ¹⁵ cm ⁻² of arsenic with an acceleration energy of eV.

Next, by using a photoresist pattern (not shown) as a mask, boron of 2 × 10 ¹⁵ cm ⁻² is ion-implanted into the surface of the p-type well contact region 14 at an acceleration energy of, for example, 10 keV. ⁺
A mold contact layer 21 is formed.

4 (a) and 4 (b). Next, a thickness of, for example, 10
By depositing and patterning a 0 nm TiN film, a TiN connection electrode 22 for connecting the p ⁺ -type contact layer 21 and the polycrystalline silicon resistor 17 is connected.

Next, for example, a thickness of 0.2 μm
After depositing the BPSG film as the interlayer insulating film 23,
Via hole 2 for n ⁺ type source / drain region 20
4, and a via hole 25 for the polycrystalline silicon gate electrode 16 and the polycrystalline silicon resistor 17 is formed, and then tungsten (W) is deposited on the entire surface, followed by etching back or CMP (chemical mechanical polishing). As a result, the via holes 24 and 25 are filled with the W plug 26.

Next, a connection wiring layer 27 for connecting the polysilicon gate electrode 16 and the polysilicon resistor 17 is formed by depositing and patterning Al on the entire surface. In this case, the wiring layer connected to the W plug 26 connected to the n ⁺ type source / drain region 20 is also patterned, but is omitted in the figure.

Thus, between the p-type well region 13 and the polycrystalline silicon gate electrode 16, the p-type silicon substrate 11, the p-type well contact region 14, the p ⁺ -type contact layer 21, the TiN connection electrode 22 , W plug, and connection wiring layer 27, and polycrystalline silicon resistor 17 is inserted.

FIG. 5 shows that the p-type well region 13 has an impurity concentration of 1.0 × 1.
0 ¹⁸ and cm ^-3, a gate electrode length, i.e., the n-channel type MOSFET in which the channel length to 0.15 [mu] m, the drain current I _d and the source - pn between the well region
FIG. 9 is a diagram showing the dependence of the _forward bias current I _forward flowing through the junction on the resistance value of the polysilicon resistor 17.

[0033] In this case, as is apparent from the figure, the drain current I _d, the resistance shown by the black squares and dashed line 0 .OMEGA (R _c
= 0), the resistance indicated by Δ and the solid line is 5 × 10 ³ Ω
In the case of (R _c = 5E3), the resistance indicated by the black inverted triangle and the solid line is 5 × 10 ⁵ Ω (R _c = 5E5), and the resistance indicated by the black triangle and the dotted line is 5 × 10 ⁷ Ω (R _c = 5E7). )in the case of,
And the resistance indicated by ○ and the solid line is 5 × 10 ⁹ Ω (R _c = 5
Decreases in the order toward the case of E9ohm), but the drain current is increasing the gate voltage V _g as compared to the MOSFET of an ordinary structure which does not short-circuited with the gate electrode of the wells in the range up to 1.0 V.

On the other hand, the pn junction between the source and the well region
Flowing forward bias current I_forwardIs a black square and a dashed line
The indicated resistance is 0Ω (R_c= 0), indicated by ◆ and solid line
5 × 10 resistance^ThreeΩ (R_c= 5E3), black inverted triangle
And the resistance indicated by the solid line is 5 × 10^FiveΩ (R_c= 5E5)
In this case, the resistance indicated by the black triangle and the dotted line is 5 × 10⁷Ω (R _c
= 5E7), and the resistance indicated by ○ and the solid line is 5 ×
10⁹Ω (R_c= 5E9 ohm)
Lower, for example, 5 × 10⁹When a Ω resistor is inserted
Is R_c= 6 digits of forward bias current I
_forwardCan be reduced.
The forward bias current I_forwardIncrease is suppressed
Can understand.

That is, although the saturation current decreases with an increase in the resistance value of the insertion resistor, if a resistor of 5 × 10 ⁹ Ω is inserted, the MOS transistor having the normal structure at 1 V is used.
Since approximately 2 times the drain current I _d of the FET, it is possible to increase the driving ability, and, forward bias current I
0.5V because _forward can be reduced by 6 digits
It is possible to use the above-mentioned practical gate voltage, for example, around 1V.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows a p-channel MOSFET constituting a CMOS.
5 is a schematic cross-sectional view showing a cross section at a position similar to that of FIG.

The basic structure and manufacturing steps in this case are the same as those of the first embodiment except that the conductivity type of the impurity to be implanted is reversed. The biggest difference is that the n-type well region 28 and the When forming the n-type well contact region 29, an impurity is implanted deeply to form the n-type well region 28 and the n-type well region 28.
The point is that the mold well contact region 29 is electrically connected through the buried oxide film 12.

In this case as well, the effect of suppressing the forward bias current and the effect of increasing the saturation current are the same as in the first embodiment. However, in the case of CMOS, the power supply voltage and the gate voltage are generally the same. Therefore, in the case of a CMOS semiconductor device, the power supply voltage is 0.5 V or more, for example, about 1 V, that is,
Low-voltage driving in a practical range can be performed.

Although the embodiments have been described above, the subject of the present invention is not limited to the MOS type semiconductor device, and the MESFET or the MI using a compound semiconductor may be used.
It is intended for a field effect type semiconductor device such as an S type semiconductor device.

In each of the above embodiments, the polycrystalline silicon resistor 17 and the well contact regions 14 and 2 are used.
Although TiN is used as a connection electrode connecting 9 in consideration of heat resistance and easiness of etching, the present invention is not limited to TiN, and another high melting point metal may be used. If a high-temperature heat treatment step is not involved, a metal such as Al may be used.

In each of the above embodiments, the insertion resistance is formed using the same polycrystalline silicon layer as the gate electrode in consideration of simplification of the manufacturing process. It does not need to be a polycrystalline silicon layer, and a resistor having another metallic composition may be used. In these cases, the resistance is high in the high impurity concentration contact layer 21 on the surface of the well contact regions 14 and 29. Patterning may be performed so as to be directly connected to the P. 32, and the TiN connection electrode is not required.

In each of the above embodiments, a p-type silicon substrate is used as the substrate. However, an n-type silicon substrate may be used.
(Silicon on Sapphire) substrate, bonded substrate, SIMOX (Separation b)
y Implanted Oxygen) SO such as a substrate
An I (Silicon on Insulator) substrate may be used.

When such an SOI substrate is used, the well capacitance formed by the junction between the well region and the substrate can be eliminated, so that the well potential changes in synchronization with the change in the gate voltage. An increase in the well capacity due to the fluctuation can be suppressed.

In the description of each of the above embodiments, the shallow trench element isolation structure and the LDD structure are employed on the premise of miniaturization. However, such isolation structures and element structures are not necessarily employed. It is not necessary to employ a normal LOCOS (selective oxidation) element isolation structure and a single source / drain structure.

[0045]

According to the present invention, the saturation current is increased by electrically connecting the gate electrode and the well region, and the forward bias current is greatly suppressed by inserting a resistor. Low-voltage driving within a practical range of about 1 V is possible, which greatly contributes to miniaturization and high performance of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention up to the middle of FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of the first embodiment of the present invention after FIG. 3;

FIG. 5 is an explanatory diagram of an effect of the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 well region 3 well contact region 4 resistor 5 gate electrode 6 connection conductor layer 7 connection wiring layer 11 p-type silicon substrate 12 buried oxide film 13 p-type well region 14 p-type well contact region 15 gate oxide film 16 Polycrystalline silicon gate electrode 17 Polycrystalline silicon resistor 18 n ⁻ type LDD region 19 sidewall 20 n ⁺ type source / drain region 21 p ⁺ type contact layer 22 TiN connection electrode 23 interlayer insulating film 24 via hole 25 via hole 26 W plug 27 connection Wiring layer 28 n-type well region 29 n-type well contact region 30 p ^- type LDD region 31 p ⁺ type source / drain region 32 n ⁺ type contact region

Claims (5)

[Claims] 1. A field effect type semiconductor device comprising: a field effect type semiconductor device provided in a well region provided in a semiconductor substrate; and a resistor inserted between a gate electrode of the field effect type semiconductor device and the well region. Type semiconductor device. 2. The field-effect semiconductor device according to claim 1, wherein a gate voltage applied to a gate electrode of said field-effect semiconductor element is 0.5 V or more. 3. The field-effect semiconductor device according to claim 1, wherein said resistor is constituted by a polycrystalline silicon layer of the same layer as said gate electrode. 4. The field-effect semiconductor device according to claim 1, wherein TiN is used as a connection conductor layer for connecting the resistor and the gate electrode. 5. The field-effect semiconductor device according to claim 1, wherein a semiconductor substrate having a single crystal semiconductor layer provided on an insulator is used as the semiconductor substrate.