JPH07202211A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device of smaller capacitance and higher operational speed by etching laminated structure that are formed in sequence of a conductive layer to be one side gate, one side gate insulating layer, a semiconductor layer to be a channel, other side gate insulating layer and a conductive layer to be other side gate simultaneously with a mask formed at one time. CONSTITUTION:A laminated part is formed by reactive ion etching of a polysilicon layer 7, a gate oxide film 6, a silicon layer 1, a gate oxide film 2 and a polysilicon layer 3 with a mask of a resist film. A side wall region 8 of SiO2 at the edge of the polysilicon layer 3 and the gate oxide film 2 is formed and on the surface of which a side wall region 9 of the polysilicon that is doped with n type impurity is formed. Tungsten is selectively grown on the exposed side wall region 9 of the polysilicon and an electrode leader line part 11 is formed. With this parasitic capacitance of a double gate MOSFET is decreased and high operational speed is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET (hereinafter simply referred to as a double gate MOSFET) having a silicon thin film (SOI) formed on an insulating surface as a channel region and having gate electrodes above and below the channel region.

MOSFET having SOI as a channel region
(Hereinafter referred to as SOI-MOSFET) has a small source / drain capacitance, can increase the drain current, and is excellent in radiation resistance characteristics and withstand voltage characteristics. In particular, the double-gate MOSFET can pass a drain current more than twice as much as the SOI-MOSFET having a gate electrode only on one side of the channel region (hereinafter, simply referred to as a single-gate MOSFET), and the transconductance is improved. Is known to do.

[0003]

2. Description of the Related Art FIG. 9 shows a conventional double gate MOSFE.
The structure of T is shown. The single crystal silicon layer 5 is formed on the surface of the insulating layer 51.
0 is formed. In the silicon layer 50, a central channel region 50c, and source and drain regions 50a and 50b doped with impurities are formed on both sides of the channel region 50c.

A back gate 53 having an insulated gate structure is formed immediately below the channel region 50c in the insulating layer 51. Further, the front gate 54 having an insulated gate structure is also formed on the channel region 50c. The front gate 54 is covered with an insulating layer 52.

To manufacture the double-gate MOSFET having the above structure, first, the back gate 53 having an insulated gate structure is formed on the surface of the silicon substrate. Next, SiO ₂
An insulating film such as is deposited and the surface is polished, and a support substrate having a SiO ₂ film formed on the surface (not shown) is bonded.

The silicon substrate is then polished from the back, leaving a silicon layer 50 of the desired thickness. The front gate 54 is formed on the polished surface by a usual method. Impurities are diffused or ion-implanted into the silicon layer 50 using the front gate 54 as a mask to form a source region 50a and a drain region 50b. Finally, the front gate 54 is covered with the insulating film 52.

[0007]

When the double gate MOSFET is manufactured by the above procedure, the source region 50a, the drain region 50b and the front gate 54 are self-aligned. However, the back gate 53 cannot be manufactured by self-alignment. The positioning accuracy depends on the accuracy of mask alignment between the back gate 53 and the front gate 54 when the front gate 54 is formed on the silicon layer 50.

The position of the back gate 53 is the channel region 5
When it deviates from 0c, no channel is formed on the back gate side. In order to prevent this, the back gate 5
3 is formed slightly longer than the front gate 54 in the channel direction.

Therefore, the back gate 53 overlaps the source region 50a and the drain region 50b.
The overlap increases the source-back gate capacitance and the drain-back gate capacitance, which hinders speeding up.

FIG. 8 shows the result of a simulation in which the delay time of a ring oscillator composed of complementary SOI-MOSFETs when the load capacitance is changed is obtained. The horizontal axis represents the load capacity in units of fF, and the vertical axis represents the delay time in units of ps. The conditions of the SOI-MOSFET are as follows: effective channel length Leff = 0.1 μm, n-channel SOI
-MOSFET gate width Wn = 1 μm, p-channel S
The gate width Wp of the OI-MOSFET is 1.8 μm.

Straight lines p1, p2, and p3 indicate delay times when the overlap amount ΔL is 0 nm, 50 nm, and 100 nm, respectively. Here, the overlap amount ΔL is as shown in FIG.
As shown in, the back gate 53 represents the length of each overlap when it is assumed that the lengths of the back gate 53 and the source region 50a and the drain region 50b overlap each other. The dotted line q indicates the delay time of the single gate MOSFET.

As the overlap amount ΔL increases, the delay time also increases. Therefore, in order to increase the speed, it is necessary to reduce the overlap amount. However, as described above, in the conventional method, it is necessary to secure a certain amount of overlap amount. The delay time when the overlap amount is 0 is almost half the delay time of the single-gate MOSFET, and the speed can be increased.

An object of the present invention is to provide a manufacturing technique of a double gate MOSFET having a small parasitic capacitance and capable of operating at high speed.

[0014]

According to a method of manufacturing a semiconductor device of the present invention, at least a first conductive layer, a first insulating layer, a single crystal semiconductor layer, and a second insulating layer are formed on a supporting substrate having an insulating surface. And a second conductive layer are stacked in this order to form a stacked structure, and a mask layer formed in a predetermined pattern is used as a mask to be substantially vertical and substantially parallel to the surface of the supporting substrate. A step of anisotropically etching the laminated structure so as to form a set of side surfaces, and at least the first side of the set of side surfaces.
An insulating region forming step of forming an insulating region covering the end face of the conductive layer and exposing the end faces of the single crystal semiconductor layer and the second conductive layer, and at least the single crystal among the pair of side faces. And a conductive region forming step of forming a conductive region covering the end face of the semiconductor layer and exposing the end face of the second conductive layer.

[0015]

A laminated structure in which a conductive layer to be one gate, one gate insulating layer, a semiconductor layer to be a channel, the other gate insulating layer, and a conductive layer to be the other gate are formed in this order is formed once. The end faces of the respective layers can be easily aligned by etching at the same time when forming the mask. By covering the end surface of the lower conductive layer with an insulator and forming the conductor thereon, the conductor can be electrically connected to the semiconductor layer through the end surface of the semiconductor layer. This conductor
Due to the structure of the semiconductor-conductor, the source electrode and the drain electrode can be taken out from the channel region.

In this way, it is possible to construct a double gate MOSFET in which the channel length is equal to the gate lengths formed above and below it, and there is almost no overlap between the gate and the source and drain regions.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an n-channel double gate MOSFE will be described.
An example of the present invention will be described by taking T as an example. In addition,
The same manufacturing method is used for p-channel double gate MOSFE.
It is also applicable to T.

A first embodiment will be described with reference to FIGS. As shown in FIG. 1A, a silicon substrate 1
A gate oxide film 2 having a thickness of 10 nm is formed on the surface at an oxidation temperature of 800 ° C. On the gate oxide film 2, a 100 nm-thickness polysilicon layer 3 to be a back gate is formed by CVD. For example, temperature 1000 ° C, pressure 1.3Pa
When silane is used to deposit a polysilicon layer under the conditions described above, the deposition rate is 10 nm / min. The polysilicon layer 3 is doped with a predetermined concentration of phosphorus (P).

As shown in FIG. 1B, the surface has a thickness of 1 μm.
A silicon supporting substrate 5 having an oxide film 4 of m is prepared. Polysilicon layer 3 on silicon substrate 1 and support substrate 5
The upper oxide film 4 is closely adhered and bonded. Note that FIG.
(B) is vertically inverted from FIG. 1 (A). After the bonding, the silicon substrate 1 is polished to leave the silicon layer 1 having a thickness of 105 nm.

In the polishing step, for example, an alkaline solution type NALCO based on colloidal silica as a polishing agent is used.
2360 (made by Rhoder Nitta) can be used at a polishing pressure of 100 g / cm ² . Further, as the polishing cloth, for example, a polyurethane pad can be used.

As shown in FIG. 1C, the silicon layer 1
Is thermally oxidized at an oxidation temperature of 800 ° C. to form a gate oxide film 6 having a thickness of 10 nm. As shown in FIG. 1D, a thickness 100, which will be a front gate later, is formed on the gate oxide film 6.
A polysilicon layer 7 of nm thickness is formed by CVD. The polysilicon layer 7 is doped with a predetermined concentration of phosphorus.

As shown in FIG. 2A, a resist film (not shown) is applied to the surface of the polysilicon layer 7 to form a predetermined pattern. Using this resist film as a mask, the polysilicon layer 7, gate oxide film 6, silicon layer 1, gate oxide film 2 and polysilicon layer 3 are subjected to reactive ion etching. By this etching, the laminated portion 20 which is long in the direction perpendicular to the paper surface is formed.

Carbon tetrafluoride (CF ₄ ) and hydrogen (H ₂ ) are used as reaction gases for etching. This etching gas etches both the silicon layer and the SiO ₂ layer. Since the SiO ₂ film 4 is also etched by this etching gas, the etching is stopped by controlling the time when the surface of the SiO ₂ film 4 is exposed.

As shown in FIG. 2B, the polysilicon layer
3 and the end surface of the gate oxide film 2 have SiO ₂The sidewall region 8 of
To achieve. The sidewall region 8 is formed by CVD with SiO 2.₂Membrane thickness
100 nm deposition followed by CF_FourAnd H₂Using RIE
By performing 310 nm anisotropic etching by
Is made. The oxide film 4 was exposed during the etching.
Although the part is also etched, the thickness of the oxide film 4 is 1 μm.
There is no problem because it is thicker than the etching depth.

As shown in FIG. 2C, a polysilicon side wall region 9 doped with an n-type impurity is formed on the end face of the silicon layer 1 and the surface of the SiO ₂ side wall region 8. Side wall area 9
Is formed by depositing 100 nm of polysilicon by CVD, subsequently setting the substrate temperature to 0 ° C. or lower, and performing 210 nm anisotropic etching by magnetron RIE using chlorine gas. The side wall region 9 is in ohmic contact with the end face of the silicon layer 1, and one side is a source region and the other side is a drain region.

As shown in FIG. 2D, SOG (spin on glass) is spin-coated and annealed at a temperature of 650 ° C. for 30 minutes in a wet oxygen atmosphere. As a result, the surface of the applied SOG is flattened, and the exposed surface of the oxide film 4 and the polysilicon sidewall region 9 and the gate oxide film 6 are formed.
An insulating layer 10 is formed to cover the end surface of the polysilicon layer 7. At this time, the height of the upper surface of the insulating layer 10 can be made substantially equal to the upper surface of the polysilicon layer 7 by appropriately controlling the coating amount of SOG.

As shown in FIG. 2 (E), contact holes for drawing out the source and drain electrodes are formed in the insulating layer 10 by lithography to expose a part of the surface of the polysilicon side wall region 9. Tungsten (W) is selectively grown on the exposed polysilicon sidewall region 9 to form an electrode lead portion 11. Incidentally, in order to prevent tungsten from growing on the surface of the polysilicon layer 7 during the selective growth, it is covered with a SiO ₂ film or the like. For example, tungsten hexafluoride (WF ₆ ) and silane (SiH ₄ ) are used as reaction gases, and tungsten can be selectively grown at a substrate temperature of 360 ° C.

In this way, the front gate 7 and the back gate 3 having the insulated gate structure can be formed on the upper side and the lower side of the silicon layer 1 to be the channel region. From the channel region 1, the polysilicon side wall region 9 and the electrode lead-out portion 11 connected to the end faces on both sides thereof.
The source electrode and the drain electrode can be led out through the.

In this method, both end faces of the front gate 7, the back gate 3 and the channel region 1 on the source / drain region side are simultaneously formed by one anisotropic etching. Therefore, accurate alignment can be performed without providing an overlap between the front gate or the back gate and the source / drain regions.

In FIGS. 2A to 2E, description has been made focusing on the cross section along the drain current direction of the double gate MOSFET. Next, description will be made focusing on the cross section perpendicular to the drain current direction. To do.

FIG. 3A shows a cross section perpendicular to the direction of the drain current after forming the polysilicon side wall region shown in FIG. 2C. A laminated portion is formed long in the lateral direction of FIG.

As shown in FIG. 3B, the polysilicon layer 7, the gate oxide film 6, the silicon layer 1, the gate oxide film 2 and the polysilicon are formed by the same method as the etching process described in FIG. 2A. Etching layer 3 in a predetermined pattern,
An island-shaped laminated portion is formed.

As shown in FIG. 3C, the polysilicon layer 7, the gate oxide film 6, the silicon layer 1 and the gate oxide film 2 are formed.
One end is etched to expose a part of the surface of the polysilicon layer 3. Next, the step of FIG. 2D is performed to form the insulating layer 10.

As shown in FIG. 3D, a contact hole for drawing out an electrode is opened in the insulating layer 10 to expose a part of the surface of the polysilicon layer 3. Tungsten is selectively grown on the exposed polysilicon layer 3 to form the electrode lead-out portion 12. Note that this step can be performed at the same time as the step in FIG.

In this way, the electrode can be pulled out from the back gate 3. Figure 4 shows a double gate MOS
The top view of FET is shown. The central portion of the figure is a laminated portion in which the channel region 1, the front gate 7, the back gate 3 and the like are formed. Electrode extraction portions 11 shown in FIG. 2 (E) are formed on both sides of the laminated portion. A source electrode S is formed on one electrode lead-out portion 11, and a drain electrode D is formed on the other electrode lead-out portion 11 and extend in the left and right directions in the figure, respectively.

An electrode lead-out portion 12 from the back gate is formed on the lower side of the laminated portion, and a back gate electrode BG is formed on the electrode lead-out portion 12 and extends downward in the drawing.
A front gate electrode FG is formed on the front gate 7 and extends upward in the drawing.

Next, a second embodiment of the present invention will be described. The silicon substrate is heated to 650 ° C., and oxygen ions are accelerated at an energy of 80 keV and a dose of 3.0 × 10 ¹⁷ cm.
^-2 , followed by acceleration energy of 10 keV and dose of 3.0 ×
Ion implantation is performed so as to ^obtain 10 ¹⁵ cm ^-2 . When ion implantation was performed with acceleration energy of 80 keV and 10 keV, the oxygen ion concentration was 0.19 from the substrate surface, respectively.
It becomes maximum at a depth of μm and 0.02 μm.

Next, an argon atmosphere containing 0.5% oxygen.
Inside, high temperature treatment is performed at a temperature of 1320 ° C. for 6 hours. to this
From the substrate surface, depths of 0.19 μm and 0.02 μm
At the position of₂A layer is formed. Also a silicon substrate
The surface is oxidized and SiO ₂A layer is formed.

In this way, Si is formed on the surface of the silicon substrate.
A 5-layer structure in which O ₂ layers and silicon layers are alternately stacked can be formed. This is shown in FIG. 1 in the first embodiment.
It has the same structure as that of (C). In this embodiment, a single crystal silicon layer is formed instead of the polysilicon layer 3. Single crystals have advantages such as higher carrier mobility than polycrystals. However, since the silicon layer 3 will later become a back gate, there is not much difference in function between single crystal and polycrystal.

After forming the laminated structure shown in FIG.
A double-gate MOSFET can be manufactured by the same process as in the above-mentioned embodiment. Note that after performing the first oxygen ion implantation with constant energy, silicon or another material may be vapor-deposited on the substrate surface and the second oxygen ion implantation may be performed. During the second ion implantation, a thin film of silicon or another material is formed on the surface of the silicon substrate. Therefore, even if the second ion implantation is performed with the same acceleration energy as that of the first ion implantation, the depth of the ion implantation based on the original silicon substrate surface becomes shallow.

After the first ion implantation, the surface of the silicon substrate may be etched to a predetermined thickness and the second ion implantation may be performed. In this case, the depth at which oxygen is implanted by the second ion implantation becomes deeper than the depth of the first implantation.

In this way, the acceleration energies of the first and second ion implantations can be made equal to form the ion implantation layers having different depths. It is not always necessary to make the acceleration energy of the second ion implantation equal to the acceleration energy of the first ion implantation. Also, nitrogen may be ion-implanted instead of oxygen. A layered structure of a silicon layer and a SiN layer can be formed by implanting nitrogen ions. A double gate MOSFET using a SiN film as a gate insulating film can be manufactured.

Next, a third embodiment of the present invention will be described with reference to FIG. First, the laminated portion shown in FIG. 2A is formed by the same process as in the first embodiment. As shown in FIG. 5A, SOG is applied by spin coating so as to have a thickness of 100 nm, and then annealed in wet oxygen at a temperature of 650 ° C. for 30 minutes. As a result, the surface of the applied insulating layer is flattened, and the insulating layer 13 slightly thicker than the thickness of the polysilicon layer 3 is formed.

As shown in FIG. 5B, a polysilicon side wall region 14 covering the end face of the silicon layer 1 is formed. It has a thickness of 10 by CVD of polysilicon on the surface of the substrate.
It can be formed by depositing 0 nm and performing anisotropic etching with a thickness of 210 nm by RIE. After the polysilicon sidewall region 14 is formed, the same steps as those in FIGS. 3A to 3C in the first embodiment are performed, and the polysilicon is formed in a stepwise shape in a cross section perpendicular to the paper surface. Part of the surface of layer 3 is exposed.

As shown in FIG. 5C, the exposed surface of the insulating layer 13 and the polysilicon sidewall region 14 and the end surfaces of the gate oxide film 6 and the polysilicon layer 7 are covered, and the height of the surface is the polysilicon layer. An insulating layer 15 is formed that substantially matches the upper surface of 7. This can be formed by a method similar to the method of forming the insulating layer 10 shown in FIG. 2D of the first embodiment.

As shown in FIG. 5D, a contact hole for leading out an electrode is formed in the insulating layer 13, and tungsten is selectively grown. This is shown in FIG. 2 in the first embodiment.
It can be grown by a method similar to the method of forming the electrode lead-out portion 11 shown in (E). At the same time, similar to the formation of the electrode lead-out portion 12 shown in FIG. 3D of the first embodiment,
An electrode lead-out portion (not shown) is also formed from the back gate 3.

In this embodiment, the insulating layer 13 is used to insulate the back gate 3 from the polysilicon sidewall region 14 for leading out the source electrode and the drain electrode. In this respect, the same function as the SiO ₂ sidewall region 8 (see FIG.
(E)), which is different from the first embodiment.

Also in this embodiment, similar to the first embodiment, it is possible to prevent the front gate or back gate from overlapping the source / drain regions.
Next, a fourth embodiment will be described with reference to FIG.

FIG. 6A shows the third embodiment of FIG. 5A.
It is a silicon substrate having a laminated portion manufactured by the same process as that shown in FIG. As shown in FIG. 6B, low melting point metal aluminum (Al) is evaporated to a thickness of 100 nm and annealed at a temperature of 850 ° C. Since the melting point of aluminum is 660 ° C., the aluminum vapor-deposited on the end surface and the upper surface of the polysilicon layer 7 melts and flows. In this way, the end face of the silicon layer 1 and the gate oxide film 6 are
An aluminum layer 18 is formed to cover the lower part of the end surface of the. The annealing temperature may be equal to or higher than the melting point of aluminum and may be equal to or lower than the lowest melting point among the melting points of the layers of the laminated portion 30.

As shown in FIG. 6C, a 100 nm-thick PSG (phosphorus silicate glass) is deposited by CVD to form an insulating layer 19. As shown in FIG. 6 (D),
A contact hole is formed in the insulating layer 19, and tungsten is selectively grown on the aluminum layer 18 to form the electrode lead-out portion 2.
Form 0.

As described above, a double gate MOSFET having the same effect can be obtained even if a low melting point metal layer such as aluminum is used in place of the polysilicon side wall regions serving as the source / drain regions in the first to third embodiments. Obtainable. Further, the insulating layer 17 formed of SOG (see FIG.
Instead of (A)), the SiO ₂ side wall region 8 (FIG. 2B) in the first embodiment may be formed and the steps after FIG. 6B may be performed.

The laminated portion 3 is used instead of aluminum.
Other metals having even lower melting points than the lowest melting point of each layer of 0 may be used. FIG. 7 shows a cross section of the double-gate MOSFET when the SiO ₂ sidewall region 17a is formed instead of the insulating layer 17. Thus, even if the aluminum layer 18 and the back gate 3 are insulated from each other in the SiO ₂ side wall region 17a, the same effect as that of the double gate MOSFET shown in FIG. 6D can be obtained.

As described above, as the method of forming the laminated structure of silicon and SiO ₂ , the substrate bonding method is used in the first embodiment and the SIMOX method is used in the second embodiment, but other methods are described. You may form a laminated structure by. For example, an electron beam annealing method, a laser annealing method or a solid phase growth method may be used.

The electron beam annealing method is a method of depositing polysilicon on the surface of SiO ₂ and irradiating it with an electron beam for recrystallization. For example, acceleration voltage 10 kV, current 10
Recrystallization can be performed by irradiating with an electron beam of 0 mA and a beam diameter of 200 μm.

The laser annealing method is a method of recrystallizing with a laser instead of an electron beam. For example, a 20 W continuous wave argon laser is used to irradiate the substrate surface with a beam diameter of 20 μm and a scanning speed of 20 cm / s.

The solid phase growth method is applied to, for example, 10
A SiO ₂ film of 0 nm is deposited, and 1 μm square openings are provided every 2 μm. Disilane is caused to flow under the conditions of a substrate temperature of 490 ° C. and a pressure of 6 Torr to deposit a silicon layer. Under this condition, the growth rate is about 100 nm / min.
Then, by annealing at 600 ° C., the deposited silicon layer gradually solid-phase grows from the surface of the underlying silicon substrate. The solid phase growth rate is about 3 × 10 ⁻⁸ cm / s.

If the laminated structure shown in FIG. 1D can be formed by the above method, the same steps as those of the first to fourth embodiments are performed thereafter to form the front gate or the back gate and the source or A double gate MOSFET that does not overlap with the drain region can be manufactured.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0059]

As described above, according to the present invention,
It is possible to reduce the parasitic capacitance of the double-gate MOSFET and enable high-speed operation.

[Brief description of drawings]

FIG. 1 is a double gate MO according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate for explaining the method of manufacturing the SFET.

FIG. 2 is a double gate MO according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate for explaining the method of manufacturing the SFET.

FIG. 3 is a double gate MO according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate for explaining the method of manufacturing the SFET.

FIG. 4 is a double gate MO according to a first embodiment of the present invention.
It is a top view of SFET.

FIG. 5 is a double gate MO according to a third embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate for explaining the method of manufacturing the SFET.

FIG. 6 is a double gate MO according to a fourth embodiment of the present invention.
FIG. 9 is a cross-sectional view of the substrate for explaining the method of manufacturing the SFET.

FIG. 7 is a sectional view of a double gate MOSFET according to a modification of the fourth embodiment of the present invention.

FIG. 8 is a graph showing changes in delay time with respect to load capacitance of a ring oscillator formed of a single-gate MOSFET or a double-gate MOSFET.

FIG. 9 is a cross-sectional view of a conventional double gate MOSFET.

[Explanation of symbols]

1 Silicon Layer 2, 4, 6 SiO ₂ Film 3 Polysilicon Layer (Back Gate) 5 Support Substrate 7 Polysilicon Layer (Front Gate) 8 SiO ₂ Sidewall Region 9 Polysilicon Sidewall Region 10 Insulating Layers 11, 12 Electrode Leads 13 Insulation layer 14 Polysilicon side wall region 15 Insulation layer 16 Electrode extraction part 17 Insulation layer 17a SiO ₂ Side wall region 18 Metal layer 19 Insulation layer 20 Electrode extraction part 30 Laminated part 50 Silicon layer 50a Source region 50b Drain region 50c Channel region 51, 52 Insulation layer 53 Back gate 54 Front gate

Claims (11)

[Claims] 1. On a supporting substrate (5) having an insulating surface,
At least a first conductive layer (3), a first insulating layer (2),
Laminating step of forming a laminated structure in which the single crystal semiconductor layer (1), the second insulating layer (6) and the second conductive layer (7) are laminated in this order, and a mask formed in a predetermined pattern Layer as a mask,
An etching step of anisotropically etching the laminated structure so as to form a pair of side surfaces that are substantially perpendicular to the surface of the support substrate and substantially parallel to each other; An insulating region forming step of covering an end face of a conductive layer and forming an insulating region exposing the end faces of the single crystal semiconductor layer and the second conductive layer; and at least the single crystal semiconductor among the pair of side faces. And a conductive region forming step of forming a conductive region covering the end face of the layer and exposing the end face of the second conductive layer. 2. The step of forming a stack comprises: forming the first insulating layer on a surface of a single crystal semiconductor substrate; forming the first conductive layer on the first insulating layer; Bonding the insulating surface of the support substrate and the surface of the first conductive layer, removing a part of the single crystal semiconductor substrate from the back surface, and leaving the single crystal semiconductor layer, and on the single crystal semiconductor layer The method for manufacturing a semiconductor device according to claim 1, further comprising: a step of forming the second insulating layer on the first insulating layer; and a step of forming the second conductive layer on the second insulating layer. 3. The step of forming a stack comprises the step of implanting oxygen or nitrogen into a single crystal semiconductor substrate at a first acceleration voltage, and a second acceleration voltage different from the first acceleration voltage in the single crystal semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: ion-implanting oxygen or nitrogen in step 1; and heat treating the single crystal semiconductor substrate in an oxidizing atmosphere. 4. The step of forming a stack comprises the steps of: implanting oxygen or nitrogen into a single crystal semiconductor substrate at a first acceleration voltage; forming a predetermined thin film on the single crystal semiconductor substrate; The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of implanting oxygen or nitrogen into the crystal semiconductor substrate at a second acceleration voltage; and a step of heat-treating the single crystal semiconductor substrate in an oxidizing atmosphere. 5. The step of forming a stack comprises the steps of: implanting oxygen or nitrogen into a single crystal semiconductor substrate at a first acceleration voltage; etching the single crystal semiconductor substrate to a predetermined thickness; The method of manufacturing a semiconductor device according to claim 1, further comprising: a step of implanting oxygen or nitrogen into the semiconductor substrate at a second acceleration voltage; and a step of heat-treating the single crystal semiconductor substrate in an oxidizing atmosphere. 6. The insulating region forming step comprises the step of isotropically forming an insulating layer on the surface of the substrate on which the laminated structure is formed, and a part of the insulating layer is anisotropically etched. 6. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of removing the insulating side wall region to cover at least an end face of the first conductive layer. 7. In the insulating region forming step, a third surface covering at least an end face of the first conductive layer is formed by applying an insulating material to the surface of the substrate having the laminated structure by a spin-on-glass method and heat-treating the same. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is formed. 8. The conductive region forming step is a step of isotropically forming a conductive layer on the surface of the substrate on which the insulating region is formed, and a part of the conductive layer is anisotropically etched. And a conductive sidewall region that covers at least the end face of the single crystal semiconductor layer is removed by the method of claim 1, and the method of manufacturing a semiconductor device according to claim 1. 9. The conductive region forming step comprises forming a first conductive layer, a first insulating layer, a single crystal semiconductor layer, a second insulating layer, and a second insulating layer on the surface of the substrate on which the insulating region is formed. A step of forming a conductor layer having a lower melting point than the lowest melting point of the conductive layer and the insulating region, at a temperature not higher than the lowest melting point and higher than the melting point of the conductor layer. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment to form a third conductive layer that covers at least an end face of the single crystal semiconductor layer. 10. A step of forming a fourth insulating layer, the height of the surface of which is substantially equal to the height of the upper surface of the second conductive layer after the step of forming the conductive region, and the fourth insulating layer. 10. The method according to claim 1, further comprising: a step of forming a contact hole in the layer to expose a part of the surface of the conductive region; and a step of selectively growing a conductor on the exposed fourth insulating layer. A method for manufacturing a semiconductor device as described above. 11. A supporting substrate (5) having a physical supporting force.
And a back gate electrode (3) formed on the support substrate (5) and having a pair of substantially parallel sides, and a pair of back gate electrodes (3) formed on the back gate electrode (3) and aligned with the pair of sides. A first insulating layer (2) having sides, a single crystal semiconductor channel layer (1) formed on the first insulating layer (2) and having a pair of sides matching the pair of sides, A second insulating layer (6) formed on the channel layer and having a pair of sides aligned with the pair of sides; and a pair of sides formed on the second insulating layer and aligned with the pair of sides. A semiconductor device comprising: a front gate electrode (7) having: and a current drawing region (8) in contact with the pair of sides of the channel layer (1).