JP2001313395A - Misfet and method of manufacturing the same - Google Patents

Misfet and method of manufacturing the same

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Publication number
JP2001313395A
JP2001313395A JP2000129099A JP2000129099A JP2001313395A JP 2001313395 A JP2001313395 A JP 2001313395A JP 2000129099 A JP2000129099 A JP 2000129099A JP 2000129099 A JP2000129099 A JP 2000129099A JP 2001313395 A JP2001313395 A JP 2001313395A
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Prior art keywords
insulating film
semiconductor substrate
gate
trench
substrate
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JP2000129099A
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Japanese (ja)
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JP4750245B2 (en
Inventor
Takehide Shirato
白土猛英
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Takehide Shirato
白土 猛英
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Abstract

PROBLEM TO BE SOLVED: To manufacture a high-speed and highly reliable SOI-type MISFET. SOLUTION: The SOI-type MISFET has a damascene double-gate type metal source drain structure, in which a pair of conductive films (metal sources/drain regions) 5 for formed in contact with two opposite side faces of a second semiconductor substrate (SOI substrate) 3, which is laminated on a first semiconductor substrate through an oxide film 2 and is made thin and is insularly insulated and separated in an island form. In the parts of the SOI substrate 3, which are in contact with the metal source drain regions 5, a pair of heavily-doped and lightly-doped source drain regions (12, 13) are formed. Being insulated and separated from the metal source drain regions 5, a first gate electrode 8 is embedded flat on the lower surface of the SOI substrate 3 via a first gate oxide film 6 and a second gate electrode 11 is embedded flat on the upper surface of the SOI substrate 3 via a second gate oxide film 9, with the first and second gate electrode (8, 11) being connected to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having an SOI structure, and more particularly to a short-channel MIS field-effect transistor having an SOI structure having high speed, high reliability and high integration. Conventionally, as for a short channel MIS field effect transistor having an SOI structure, a short channel MIS field effect transistor having an LDD structure using a sidewall is formed on an SOI substrate whose periphery is separated by an insulating film. Higher speed and lower power have been achieved by reducing the depletion layer capacitance and threshold voltage. On the other hand, the contact resistance of the source / drain region increases due to the thin film SOI substrate, and the resistance of each element increases. Although high-speed has not been achieved despite miniaturization due to the fact that SOI has not been reduced.
When a voltage different from the voltage applied to the gate electrode is applied to the conductor (semiconductor substrate or lower wiring) under the substrate, S
There was a drawback that high reliability was not achieved because a minute back channel leak generated at the bottom of the OI substrate could not be prevented. Therefore, there is a means capable of forming a short-channel MIS field-effect transistor having an SOI structure capable of further miniaturization, reducing the resistance of each element including the contact resistance, achieving higher speed, and preventing back channel leakage. Requested.

[0002]

2. Description of the Related Art FIG. 13 is a schematic side sectional view of a conventional MIS field-effect transistor, showing a part of a semiconductor integrated circuit including an SOI type N-channel MIS field-effect transistor formed using a bonded SOI wafer. Shows,
51 is a p-type first silicon (Si) substrate, 52 is a bonding oxide film, 53 is a p-type second silicon substrate (SOI substrate), 54 is a trench for forming an isolation region and a buried oxide film, 55 is an n-type source / drain region, 56 is an n + -type source / drain region, 57 is a gate oxide film (SiO 2 ), 58 is a gate electrode, 59 is a base oxide film, 60 is a sidewall, and 61 is an oxide film for impurity blocking. , 62 are PSG films, 63 is barrier metal (Ti / TiN), 64 is plug (W), 65 is barrier metal (Ti / TiN), 66 is AlCu wiring, 67 is barrier metal (Ti / TiN).
TiN). In the figure, a p-type thin film is bonded on a p-type first silicon substrate 51 via an oxide film 52 and is insulated and isolated in an island shape by a trench for forming an isolation region and a buried oxide film 54. A second silicon substrate (SOI substrate) 53 is formed, and an MIS field effect transistor having an N-channel LDD structure is formed on the p-type second silicon substrate (SOI substrate) 53. Therefore, a reduction in junction capacitance due to formation of a source / drain region surrounded by an insulating film, a reduction in depletion layer capacitance due to complete depletion of the SOI substrate, and a reduction in threshold voltage due to improvement in sub-threshold characteristics are usually achieved. As compared with a semiconductor integrated circuit including MIS field-effect transistors formed on a bulk wafer, speeding up and lowering of power are possible. However, in order to completely deplete the SOI substrate, it is necessary to considerably reduce the thickness (about 0.1 μm). When etching the PSG at the time of opening the electrode contact window, the SOI substrate forming the source / drain region is over-etched. In addition, the speed is not increased in spite of the short channel due to the increase in the contact resistance of the source / drain region and the inability to reduce the resistance of the source / drain region. When only a field-effect transistor is formed, applying an off-voltage to the first silicon substrate can prevent a channel from being formed at the bottom of the SOI substrate and can prevent back channel leakage.
(On and off are reversed in an N-channel MIS field-effect transistor and a P-channel MIS field-effect transistor), or when only a single conductivity type MIS field-effect transistor is formed. If there is a lower wiring to which a voltage different from
There is a drawback that back channel leak occurring at the bottom of the I substrate cannot be prevented.

[0003]

The problem to be solved by the present invention is that, as shown in the prior art, in order to obtain a MIS field-effect transistor with improved high-speed performance, a fully depleted thin film SOI substrate is required. Is required. In order to form a source / drain region on the thinned SOI substrate,
When etching the interlayer insulating film at the time of opening the electrode contact window, it is inevitable that the SOI substrate forming the source / drain region is over-etched, and the contact with the wiring body can be obtained, but the contact resistance of the source / drain region can be obtained. Increases, and the capacity can be reduced, but the resistance of the thin source / drain region cannot be reduced. For this reason, high speed cannot be achieved despite miniaturization, and a C-MOS is formed. Case or SO
When there is a lower wiring to which a voltage different from the voltage applied to the gate electrode is applied under the I-substrate, the SOI structure having high speed, high integration, and high reliability can be obtained because back channel leak cannot be completely prevented. That is, a short channel MIS field effect transistor could not be formed.

[0004]

The above object is achieved by providing a first semiconductor substrate, a first insulating film provided on the first semiconductor substrate, and a first insulating film provided on the first insulating film with a space therebetween. Between the pair of conductive films (metal source / drain regions) and the pair of conductive films (metal source / drain regions) in contact with two opposing side surfaces of the pair of conductive films (metal source / drain regions). Provided second semiconductor substrate (SOI
The second semiconductor substrate (SOI substrate) at a contact portion between the substrate and the pair of conductive films (metal source / drain regions)
A pair of impurity regions (part of the source / drain region), a first gate insulating film provided at least on the lower surface of the second semiconductor substrate (SOI substrate), and the pair of conductive films (metal A first gate electrode buried under at least the second semiconductor substrate (SOI substrate) with the first gate insulating film interposed therebetween, and at least the second semiconductor substrate (SO
A second gate insulating film provided on the upper surface of the first semiconductor substrate and the pair of conductive films (metal source / drain regions), and at least the second semiconductor via the second gate insulating film. The second embedded on the substrate (SOI substrate)
Gate electrode, a pair of conductive films (metal source / drain regions), a second semiconductor substrate (SOI substrate), and a second peripheral portion provided on the remaining side surfaces of the first and second gate insulating films. The problem is solved by the MIS field-effect transistor of the present invention, comprising an insulating film and a wiring body for applying the same voltage to the first and second gate electrodes.

[0005]

In a MIS field-effect transistor of the present invention, a pair of metal source / drain regions (W) are provided on an oxide film provided on a p-type first silicon substrate. A p-type second silicon substrate (SOI substrate) is provided in contact with a part of the metal source / drain region between the regions, and a pair of n + Type and n-type source / drain regions are provided, and a first gate oxide film (SiO 2 / Ta 2 O 5 ) is provided on the lower surface of the p-type SOI substrate and the lower side surface of the opposing metal source / drain region. A first gate electrode (W) having a barrier metal (TiN) is buried flat through the first gate oxide film, and a p-type SOI
A second gate oxide film (SiO 2 / Ta 2 O 5 ) is provided on the upper surface of the substrate, and a side wall insulating film (SiO 2 ) is provided on the upper side surface of the opposing metal source / drain region. Barrier metal (Ti) through gate oxide film and buried insulating film
A second gate electrode (W) having N) is buried flat. The first and second gate electrodes (connected to the same potential) are connected to an AlCu wiring having a barrier metal (Ti / TiN) above and below via a barrier metal (Ti / TiN) and a plug (W), A gate voltage is applied, and a barrier metal (Ti / TiN
) And a plug (W) to raise and lower barrier metal (Ti
/ TiN), a source voltage and a drain voltage are applied respectively, and the periphery is completely isolated by a trench for forming an element isolation region and a buried oxide film (SiO 2 ). An MIS field effect transistor is formed. Therefore, SO
Since only the channel region, the low-concentration source / drain region and the extremely minute high-concentration source / drain region are formed on the I-substrate, and most of the source / drain region can be formed not of the impurity region but of a conductive film, the junction capacitance is reduced. (Almost zero) and the resistance of the source / drain region can be reduced. Further, since the connection with the wiring body can be established in the thick metal source / drain region (W), the contact resistance can be reduced. Furthermore, since Ta 2 O 5 having a high dielectric constant can be used as the gate oxide film, the thickness of the gate oxide film can be increased, and minute current leakage between the gate electrode and the SOI substrate can be improved and the gate capacitance can be reduced. It is. Besides, SOI
Above and below the substrate (on both sides due to slight structural deformation)
Because the gate electrode can be formed, back channel leakage (and side channel leakage when a gate electrode can be formed on both sides) can be completely prevented, and the back channel can be interlocked with the voltage applied to the second gate electrode. In this case, a sufficient drive current can be supplied (also to the side channel) and high reliability and high speed can be achieved. Also, since the gate structure is formed on a thin SOI substrate,
Since the SOI substrate can be completely depleted, the capacitance of the depletion layer between the inversion layer below the gate oxide film and the substrate can be removed, and the voltage applied to the gate electrode is reduced only between the gate electrode and the inversion layer. , And the sub-threshold characteristic can be improved, so that the threshold voltage can be reduced. Further, except for the lead-out portion for connecting the first and second gate electrodes, the first gate electrode formed through the first gate oxide film is self-aligned with the element isolation region in which the oxide film is embedded. Each element (metal source / drain region, SOI substrate, second gate electrode via the second gate oxide film and side wall insulating film, low-concentration and high-concentration impurity source / drain regions) can be formed by matching. . In addition, since the upper surfaces of the second insulating film, the metal source / drain region, and the second gate electrode of the element isolation region can be formed on a continuous flat surface without any step, an extremely reliable interlayer insulating film and wiring body are formed. You can also. That is,
An SOI MIS field-effect transistor having a damascene double-gate metal source / drain structure capable of forming a semiconductor integrated circuit with extremely high speed, low power, high reliability, high performance, and high integration can be obtained.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will tell. FIG. 1 shows a MIS field-effect transistor according to the present invention.
FIG. 2 is a schematic plan view of the first embodiment in FIG.
Schematic side of the first embodiment in the S field effect transistor
FIG. 3 is a cross-sectional view (cross-sectional view taken along the line pp in FIG. 1) of the present invention.
Schematic of the first embodiment in the IS field effect transistor
FIG. 4 is a side sectional view (a sectional view taken along line qq in FIG. 1) of the present invention.
Example of the second embodiment in the MIS field-effect transistor
FIG. 5 is a plan view showing the MIS field effect transistor according to the present invention.
FIG. 4 is a schematic side sectional view of the second embodiment (qq arrow in FIG. 4).
FIG. 6 is a MIS field-effect transistor of the present invention.
7 to 12 are schematic side sectional views of a third embodiment of the present invention.
Is a method of manufacturing the MIS field-effect transistor of the present invention.
FIG. 4 is a process cross-sectional view of one embodiment of the method. Same object throughout all figures
Objects are indicated by the same reference numerals. 1 to 3 show the MIS electric field of the present invention.
FIG. 1 schematically shows a first embodiment of an effect transistor.
FIG. 2 is a schematic side cross-sectional view (cross-sectional view taken along the line pp in FIG. 1).
Figure, channel length direction of MIS field-effect transistor)
FIG. 3 is a schematic side sectional view (a sectional view taken along the line qq in FIG. 1,
In the channel width direction of the field effect transistor)
SOI structure short-circuit formed by using the SOI technology
N-channel MIS field-effect transistor
The figure shows a part of a semiconductor integrated circuit includingFifteencm-3
The first p-type silicon substrate has a thickness of about 0.5 μm.
Oxide film for bonding (SiOTwo) 3 is about 0.1μm thick
A p-type second silicon substrate (SOI substrate), 4 is an element
Trench for forming isolated regions and buried oxide film (SiOTwo), 5
Is a metal source / drain region with a thickness of about 0.5μm
(W), 6 is a first gate oxide film (SiOTwo/ Ta
TwoOFive ), 7 is a barrier metal (TiN) of about 20 nm, 8 is
The first gate electrode (W) with a gate length of about 0.2 μm, 9 is 15n
m second gate oxide film (SiOTwo/ TaTwoOFive), 10 is 20nm
About barrier metal (TiN), 11 is about 0.2 μm gate length
Second gate electrode (W), 12 is 1017cm-3About n-type
Source drain region, 13 is 1020cm-3Degree n+ Type source
The drain region 14 has a sidewall insulating film (SiOTwo), 15
Is a phosphosilicate glass (PSG) film of about 0.8 μm, 16 is about 50 nm
Degree of barrier metal (Ti / TiN), 17 is plug (W), 18
Is about 50 nm barrier metal (Ti / TiN), 19 is about 0.8 μm
Degree AlCu wiring, 20 is about 50 nm barrier metal (Ti / TiN
 ). In the figure, a first p-type
On the oxide film 2 provided on the control board 1, a pair of metal
Source drain region (W) 5 is provided.
One of the metal source / drain regions 5
A second p-type silicon substrate (SOI substrate) 3
Is provided in the opposed metal source / drain region 5.
Each of them comes into contact with the p-type SOI substrate 3+ Type source drain
A region 13 is provided. + Source / drain region 13
, An n-type source / drain region 12 is provided,
Also, the lower surface of the p-type SOI substrate 3 and the opposing metal saw
A first gate oxide film is formed on the lower side surface of the drain region 5.
(SiOTwo/ TaTwoOFive 6) is provided, and the first gate oxidation
A first gate having a barrier metal (TiN) 7 through a film 6
The gate electrode (W) 8 is buried flat and the p-type
A second gate oxide film (SiO 2) is formed on the upper surface of the SOI substrate 3 of FIG.Two/
TaTwoOFive 9) provided, opposed metal source / drain
On the upper side surface of the region 5, a sidewall insulating film (SiOTwo) 14 provided
Through the second gate oxide film 9 and the side wall insulating film 14.
Gate electrode having barrier metal (TiN) 10
(W) 11 is buried flat. The first and second
Gate electrodes (8, 11) are barrier metal (Ti / TiN) 16
And barrier metal (Ti /
TiN) (18, 20) connected to AlCu wiring 19
Voltage is applied to the pair of metal source / drain regions 5.
Barrier metal (Ti / TiN) 16 and plug (W) 17
With barrier metal (Ti / TiN) (18, 20) above and below
To the source voltage and the source voltage, respectively.
Rain voltage is applied, and element isolation region is formed around
Trench and buried oxide film (SiOTwo) 4 complete
MIS field-effect tiger having a structure insulated and isolated
Transistors are formed. Therefore, the SOI substrate
Is the channel region, low concentration source / drain region and extremely
To form only high-concentration source / drain regions
The part of the source / drain region is not an impurity region but a conductive film
, So that the junction capacitance can be reduced (almost zero) and
The resistance of the source / drain region can be reduced. Also thick
Connection with wiring body at metal source drain region (W) of film
Therefore, the contact resistance can be reduced. Sa
Ta with a higher dielectric constantTwoOFive Used as gate oxide film
The gate oxide film can be made thicker,
Improvement of small current leakage between gate and SOI substrate and gate
The capacity can be reduced. And above and below the SOI substrate
Back channel when off because gate electrode can be formed
Not only can leakage be completely prevented, but also the second gate
When turned on, the front
As much as possible in the back channel as well as the channel
High drive current and high reliability and high speed
Can be achieved. Also, a gate structure is formed on a thin SOI substrate.
The SOI substrate can be completely depleted.
The depletion layer capacitance between the inversion layer under the gate oxide film and the substrate
Can be removed, and the voltage applied to the gate electrode can be reduced.
Can be applied only between the gate electrode and the inversion layer.
The threshold voltage
Can also be reduced. Further, first and second gates
Except for the lead-out part for connecting the electrodes, the oxide film is embedded
Align the first gate oxide film with the element isolation region
Each element is self-aligned with the first gate electrode formed through
(Metal source drain region, SOI substrate, second gate
The second gate electrode via the oxide film and the sidewall insulating film;
Concentration and high concentration impurity source / drain regions)
You can also. In addition, the second isolation of the element isolation region
Of the film, the metal source drain region and the second gate electrode
The upper surface can be formed as a continuous flat surface with no steps.
To form an extremely reliable interlayer insulating film and wiring body.
You can also. As a result, high speed, low power, high reliability,
Damascene double-gate metal with high performance and high integration
SOI MIS field-effect transistor with source / drain structure
You can get a Vista.

FIGS. 4 and 5 show a second embodiment of the MIS field effect transistor of the present invention. FIG. 4 is a schematic plan view, and FIG. 5 is a schematic side sectional view (a sectional view taken along the line qq in FIG. 4). M
3 shows a channel width direction of an IS field effect transistor. 4 is the same as FIG. 2 in the direction of the channel length of the MIS field-effect transistor in the direction of the arrow pp in FIG. 4), and is a short-channel N-channel MIS field-effect transistor having an SOI structure formed by using a bonded SOI technique. Are shown, and 1 to 20 show the same thing as FIGS. 1 to 3. In the figure, a wiring body for connecting the first and second gate electrodes at both ends of the first and second gate electrodes is provided, and this wiring body (strictly, a plug via a barrier metal) is connected to the side. An MIS field-effect transistor having the same structure as that of the first embodiment is formed except that a gate electrode (a gate oxide film is a thick oxide film for forming an element isolation region). In the present embodiment, in addition to the effects of the first embodiment, it is possible to prevent side channel leak at the time of off.

FIG. 6 is a schematic side sectional view of a third embodiment of the MIS field effect transistor of the present invention (the schematic plan view is the same as that of FIG. 4 shows the channel width direction of FIG.
The cross-sectional view taken in the direction of the arrow is the same as that of FIG. 2 in the channel length direction of the MIS field-effect transistor). A part is shown, and 1 to 20 show the same thing as FIGS. 1 to 3. In the figure, a wiring body for connecting the first and second gate electrodes at both ends of the first and second gate electrodes is provided, the second gate electrode is formed in a concave structure, and the first gate is formed. An MIS field-effect transistor having the same structure as that of the first embodiment is formed except that a gate electrode is formed so as to cover the SOI substrate via the first and second gate oxide films together with the electrodes. In the present embodiment, in addition to the effect of the first embodiment, not only the side channel leakage at the time of off is prevented, but also the front channel at the time of on is linked with the voltage applied to the second gate electrode. In addition, as much drive current as possible can flow through the back channel and the side channel, and higher reliability and higher speed can be achieved. The present invention is not limited to the above description. For example, the metal source / drain region may be formed by using two or more metal layers including a barrier metal, and the gate electrode may be formed by a general polycide gate (polySi / WSi). The present invention can be applied to the formation of the source / drain region made of impurities even if the source / drain region made of only the high concentration without the low concentration region is formed.

Next, an embodiment of a method of manufacturing a MIS field-effect transistor according to the present invention will be described with reference to FIGS. 7 to 12 and FIG. However, here, M of the present invention
Only the manufacturing method relating to the formation of the IS field effect transistor will be described, and description of the manufacturing method relating to the formation of various elements (other transistors, resistors, capacitors, etc.) mounted on a general semiconductor integrated circuit will be omitted. FIG. 7 A first trench is formed by selectively anisotropically dry-etching the p-type second silicon substrate 3 using a resist (not shown) as a mask layer by using ordinary photolithography technology. (The alignment pattern is also the first
Of the trench. Next, the resist (not shown) is removed. Next, a chemical vapor deposition oxide film (SiO 2 ) is grown and anisotropically dry-etched to form a buried element isolation region 4 in the first trench. Next, using a normal photolithography technique, using a resist (not shown) as a mask layer, a part of the oxide film (lead portion for connecting a first gate electrode to be formed later) of the element isolation region 4 is formed. Perform anisotropic dry etching of about 0.2 μm. Continuously, the p-type second silicon substrate 3 is
A second trench is formed by anisotropic dry etching to a degree. Next, the resist (not shown) is removed. Next, a first gate oxide film 6 (SiO 2 / Ta 2 O 5 ) of about 15 nm is grown. Next, a barrier metal (TiN) 7 of about 20 nm and a W film 8 of about 0.2 μm as a first gate electrode are grown by continuous sputtering. Then chemical mechanical polishing (C h
emical M ech-anical P olish
(hereinafter, abbreviated as CMP) to fill the second trench for the first gate electrode to form a buried gate electrode structure including the first gate oxide film 6, the barrier metal 7, and the first gate electrode 8. At this time, the first unnecessary part
The gate electrode 8, the barrier metal 7 and the first gate oxide film 6 are also removed. Then, using the oxide film 4, the first gate oxide film 6, the barrier metal 7, and the first gate electrode 8 as a mask layer, the remaining p-type second silicon
A third trench is formed by anisotropic dry etching of about μm. Next, a tungsten film (W) is grown by chemical vapor deposition, and a third film is formed by chemical mechanical polishing (CMP).
And a metal source / drain region (W) 5 is formed. Next, the p-type second silicon substrate 3 on which the element isolation region 4, the metal source / drain region 5, the first gate electrode 8, and the like are formed is bonded by chemical vapor deposition to a thickness of about 0.5 μm. Oxide film (SiO 2 ) 2 is grown. Next, the p-type second silicon substrate 3 is stacked with the side on which the oxide film (SiO 2 ) 2 for bonding is formed on the p-type first silicon substrate 1 facing down, and annealed at about 1000 ° C. In addition, the p-type second silicon substrate 3 is converted to the p-type first silicon substrate.
On the silicon substrate 1 of FIG. Then the p-type second
The silicon substrate 3 is subjected to mechanical grinding (approx. End point is to expose a buried oxide film in the element isolation region 4) to about several μm, and then to chemical mechanical polishing (CMP) until the buried metal source / drain region 5 is exposed. Then, a flat p-type second silicon substrate (SOI substrate) 3 having a thickness of about 0.3 μm is formed. The alignment pattern formed by the first trench in which the oxide film is buried is thus formed on the lower surface of the p-type second silicon substrate 3 (the upper surface up to FIG. 8). Can be formed. Thereafter, each element can be formed on the upper surface of the p-type second silicon substrate 3 using this alignment pattern. Next, using an ordinary photolithography technique, using a resist (not shown) and the metal source / drain region 5 as a mask layer, a part of an oxide film of the element isolation region 4 (connection of a second gate electrode to be formed later). Drawer part) 0.2
Perform anisotropic dry etching of about μm. Subsequently, the p-type second silicon substrate 3 is anisotropically dry-etched by about 0.2 μm to form a fourth trench. Next, the resist (not shown) is removed. Next, a second gate oxide film 9 (SiO 2 / Ta 2 O 5 ) of about 15 nm is grown. Then 20nm
Barrier metal (TiN) of about 10 and the second of about 0.2 μm
Is grown by continuous sputtering. Next, the trench is buried in the fourth trench for the second gate electrode by chemical mechanical polishing (CMP) to form a buried gate electrode structure including the second gate oxide film 9, the barrier metal 10, and the second gate electrode 11. . At this time, the unnecessary portions of the second gate electrode 11, the barrier metal 10, and the second gate oxide film 9 are also removed. Next, using a resist (not shown) and the metal source / drain region 5 as a mask layer, the second gate oxide film 9 formed on the side surface of the metal source / drain region 5 is anisotropically dry-etched by using ordinary photolithography technology. Then, a fifth trench is formed. Next, phosphorus is ion-implanted into the p-type second silicon substrate (SOI substrate) 3 exposed under the fifth trench. Next, the resist (not shown) is removed. Then 950 °
The n-type source / drain region 12 is formed by performing lateral diffusion by applying N 2 annealing of about C. Next, using a normal photolithography technique, using a resist (not shown) and the metal source / drain region 5 as a mask layer, the arsenic is added to the p-type second silicon substrate (SOI substrate) 3 exposed under the fifth trench. Is ion-implanted. Next, the resist (not shown) is removed. Followed by the addition of N 2 annealing at about 900 ° C, to form an n + -type source and drain regions 13 including a slight lateral diffusion. Next, a chemical vapor deposition oxide film (SiO 2 ) 14 is grown. Then, the fifth trench is buried by chemical mechanical polishing (CMP). Next, a phosphosilicate glass (PSG) film 15 of about 0.8 μm is grown by chemical vapor deposition. Next, the PSG film 15 is anisotropically dry-etched using a resist (not shown) as a mask layer to selectively open an electrode contact window using a normal photolithography technique. An electrode for connecting the first and second gate electrodes (8, 11) using a resist (not shown) as a mask layer (mask layer of two resists) continuously using a normal photolithography technique. Only the contact window was opened (see FIG. 3), the second gate electrode 11, the barrier metal 10,
The second gate oxide film 9, the oxide film 4, and the first gate oxide film 6 are sequentially subjected to anisotropic dry etching. Next, the resist (not shown) is removed. Next, Ti and TiN 16 serving as barrier metals are sequentially grown by sputtering. Next, a W film is grown on the entire surface by a blanket method of chemical vapor deposition, and anisotropically dry-etched to form a buried plug (W).
Form 17. At this time, the W film 17 and the barrier metal of the unnecessary part
16 is also etched away. FIG. 2 Next, Ti and TiN serving as barrier metals are sequentially grown by sputtering. Next, by sputtering, Al
(Including several% of Cu) is grown to about 0.8 μm. Next, Ti and TiN serving as barrier metals are sequentially grown by sputtering. Next, the AlCu wiring 19 is formed by anisotropic dry etching of the barrier metal, Al (including several% of Cu) and the barrier metal using a resist (not shown) as a mask layer by using a normal photolithography technique. To complete the MIS field effect transistor. In the above manufacturing method, the buried layer is formed by anisotropic dry etching in some steps. However, all of these steps may be performed by chemical mechanical polishing (CMP). In determining the threshold voltage of the effect transistor, the p-type SOI substrate is used as it is, but the concentration of the SOI substrate may be controlled by boron ion implantation. In the above manufacturing method, the thickness of the SOI substrate is controlled by etching both the upper surface and the lower surface of the p-type second silicon substrate. Using a thin oxide film and a nitride film (Si 3 N 4 ) of about 0.2 μm formed on the lower surface (the bottom surface in the final drawing), a first gate oxide film and a second gate oxide film are formed on a step formed by etching the nitride film and the oxide film. By forming the first gate electrode so as to be embedded, it is possible to control the thin SOI substrate by etching only the lower surface (the upper surface in the final drawing) of the p-type second silicon substrate. In the above manufacturing method, the source / drain region is formed by the impurity after the formation of the second gate electrode. However, the gate electrode is used as a dummy electrode. After the oxide film is removed by etching, a second gate oxide film and a lower-resistance second gate electrode (such as Al) made of a low melting point metal may be formed. In this case, the number of manufacturing steps is slightly increased, and the first gate electrode (W and the like) and the second gate electrode (Al and the like) are different. However, it is particularly effective when the gate electrode wiring is to be a word line in a memory or the like. .

In the case of manufacturing the MIS field effect transistor of the third embodiment, when forming the fourth trench in FIG. 10, the element isolation region is formed until the lead-out portion for connecting the first gate electrode is exposed. The formed oxide film and the first gate oxide film are anisotropically dry-etched, and a p-type second silicon substrate (SOI substrate) is continuously formed to a thickness of 0.2 μm.
A fourth trench is formed by performing anisotropic dry etching to a degree, and after removing the resist, the fourth trench is buried with a second gate electrode via a second gate oxide film. The structure can be formed so as to be covered with the first and second gate electrodes via the first and second gate oxide films. Thereafter, if the same steps as those described above are performed, the MIS field-effect transistor of the third embodiment can be manufactured.

[0011]

As described above, according to the present invention, the first
Of a second substrate bonded on a semiconductor substrate through an insulating film.
In a MIS field-effect transistor formed on an SOI substrate made of a semiconductor substrate, most of the source / drain regions are formed of a metal layer, and a channel region, a low-concentration and a high-concentration source are formed on a second semiconductor substrate (SOI substrate). Forming a drain region and forming a second region between the metal source / drain region;
An SOI having a structure in which a low-resistance high-melting-point metal gate electrode is buried flatly above and below a semiconductor substrate (SOI substrate) via a gate oxide film having a high dielectric constant in a self-aligned manner, and the upper and lower gate electrodes are connected. MIS field-effect transistor. Accordingly, in the SOI structure, the resistance of the source / drain region is reduced by forming the metal source / drain region, the junction capacitance and the contact resistance are reduced, and the gate electrode and the SOI substrate are formed by using a gate oxide film of Ta 2 O 5 having a high dielectric constant. Improve small current leakage between the gate electrodes and reduce gate capacitance, prevent back channel leak at the time of off by forming gate electrodes above and below the SOI substrate (prevent side channel leak when a side gate electrode is provided), and use back channel at the time of on Increase in drive current (increase in drive current due to side channel if side gate electrode is provided), removal of depletion layer capacitance by using a fully depleted SOI substrate, reduction of threshold voltage by improvement of subthreshold characteristics, MIS field effect transistor Fine formation by self-alignment of each element of It is a function. That is, an SOI MIS field-effect transistor having a damascene double-gate metal source / drain structure capable of forming an extremely high-speed, low-power, high-reliability, high-performance, and highly integrated semiconductor integrated circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a first embodiment of a MIS field-effect transistor according to the present invention.

FIG. 2 is a schematic side sectional view of a first embodiment of the MIS field-effect transistor of the present invention (a sectional view taken along the line pp in FIG. 1).

FIG. 3 is a schematic side sectional view of the first embodiment of the MIS field-effect transistor of the present invention (a sectional view taken along the line qq in FIG. 1).

FIG. 4 is a schematic plan view of a second embodiment of the MIS field-effect transistor of the present invention.

FIG. 5 is a schematic side sectional view of a second embodiment of the MIS field-effect transistor of the present invention (a sectional view taken along the line qq in FIG. 4).

FIG. 6 is a schematic side sectional view of a third embodiment of the MIS field-effect transistor of the present invention.

FIG. 7 is a process sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 8 is a process sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 9 is a process sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 10 is a process sectional view of an embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 11 is a process cross-sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 12 is a process cross-sectional view of one embodiment of a method for manufacturing a MIS field-effect transistor of the present invention.

FIG. 13 is a schematic side sectional view of a conventional MIS field-effect transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type first silicon substrate 2 bonding oxide film (SiO 2 ) 3 p-type second silicon substrate (SOI substrate) 4 trench for forming element isolation region and buried oxide film (SiO 2 ) 5 metal source Drain region (W) 6 First gate oxide film (SiO 2 / Ta 2 O 5 ) 7 Barrier metal (TiN) 8 First gate electrode (W) 9 Second gate oxide film (SiO 2 / Ta 2 O) 5 ) 10 Barrier metal (TiN) 11 Second gate electrode (W) 12 n-type source / drain region 13 n + type source / drain region 14 Side wall insulating film (SiO 2 ) 15 Phosphosilicate glass (PSG) film 16 Barrier metal ( Ti / TiN) 17 Plug (W) 18 Barrier metal (Ti / TiN) 19 AlCu wiring 20 Barrier metal (Ti / TiN)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 617J 627D F-term (Reference) 4M104 BB01 BB18 BB30 CC05 DD37 DD43 DD65 DD66 DD99 EE03 EE09 EE12 EE14 FF01 FF18 FF26 GG09 5F033 GG03 HH09 HH18 HH33 JJ18 JJ19 JJ33 KK09 KK19 MM01 MM08 MM13 NN06 NN07 NN39 PP09 PP15 QQ09 QQ16 QQ37 QQ48 RR04 RR14 SS11 VV06 5F110 AA03 AA02 EE05 FF01 GG HK04 HK34 HL06 HL14 HL23 HM04 HM15 NN02 NN04 NN25 NN35 NN62 NN65 QQ11 QQ16 QQ19

Claims (5)

    [Claims]
  1. A first semiconductor substrate, a first insulating film provided on the first semiconductor substrate, and a pair of conductive films (metals) provided separately on the first insulating film. A second semiconductor substrate provided between the pair of conductive films (metal source / drain regions) and a part of two opposing side surfaces of the pair of conductive films (metal source / drain regions). A pair of impurity regions (part of the source / drain region) provided on the second semiconductor substrate (SOI substrate) at a contact portion between the (SOI substrate) and the pair of conductive films (metal source / drain regions); At least a first substrate provided on a lower surface of the second semiconductor substrate (SOI substrate)
    The gate insulating film is insulated and separated from the pair of conductive films (metal source / drain regions), and is buried at least below the second semiconductor substrate (SOI substrate) via the first gate insulating film. One gate electrode, at least a second gate insulating film provided on the upper surface of the second semiconductor substrate (SOI substrate), and the pair of conductive films (metal source / drain regions). At least the second semiconductor substrate (SOI)
    A second gate electrode embedded on the substrate, the pair of conductive films (metal source / drain regions), the second semiconductor substrate (SOI substrate), and the remaining portions of the first and second gate insulating films. A MIS field-effect transistor, comprising: a second insulating film provided on the side surface; and a wiring body for applying the same voltage to the first and second gate electrodes.
  2. 2. A wiring body for applying the same voltage to the first and second gate electrodes is provided on both side surfaces of the second semiconductor substrate (SOI substrate) in a channel width direction via the second insulating film. 2. The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is provided as a side gate electrode.
  3. 3. The first and second gate electrodes are covered via the first and second gate insulating films covered around the second semiconductor substrate (SOI substrate). 2. The MIS field-effect transistor according to claim 1, wherein:
  4. 4. A pair of conductive films (metal source / drain regions), a second semiconductor substrate (SOI substrate), and a pair of impurity regions (of source / drain regions) self-aligned with the first gate electrode. 2. The MIS field-effect transistor according to claim 1, wherein said MIS field-effect transistor is provided with (a part of) said second gate electrode.
  5. 5. A step of selectively forming a first trench on a lower surface of a second semiconductor substrate, and forming a second trench in the first trench.
    Embedding an insulating film, selectively forming the second trench in a part of the second insulating film and a lower surface of the second semiconductor substrate, and bottom and side surfaces of the second trench Forming a first gate insulating film on the semiconductor substrate, embedding a first gate electrode in the second trench via the first gate insulating film, selectively forming a first gate insulating film on the lower surface of the second semiconductor substrate. Forming a third trench deeper than the second trench, burying a conductive film in the third trench, and forming a first insulating film under the second semiconductor substrate. Bonding a first semiconductor substrate under the second semiconductor substrate with the first insulating film interposed therebetween, and thinning an upper surface of the second semiconductor substrate to be flat;
    Exposing the second insulating film and the conductive film, and forming a fourth trench that does not reach the first gate insulating film on a part of the second insulating film and an upper surface of the second semiconductor substrate. Selectively forming, forming a second gate insulating film on the bottom and side surfaces of the fourth trench, and forming a second gate in the fourth trench via the second gate insulating film. Embedding an electrode; removing the second gate insulating film on the side surface of the fourth trench; and selectively forming a fifth trench; and forming the second semiconductor under the fifth trench. Forming an impurity region in the substrate, embedding a third insulating film in the fifth trench, and connecting the first and second gate electrodes with a wiring body. Method for manufacturing MIS field-effect transistor
JP2000129099A 2000-04-28 2000-04-28 MIS field effect transistor and manufacturing method thereof Expired - Fee Related JP4750245B2 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343686A (en) * 1992-06-04 1993-12-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0621455A (en) * 1992-06-30 1994-01-28 Sanyo Electric Co Ltd Thin-film transistor
JPH07169848A (en) * 1993-12-15 1995-07-04 Hitachi Ltd Semiconductor device and manufacture of it
JPH07202211A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Manufacture of semiconductor device
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0864827A (en) * 1994-08-23 1996-03-08 Hitachi Ltd Semiconductor device and method of fabrication thereof
JPH11103057A (en) * 1997-03-17 1999-04-13 Toshiba Corp Semiconductor device
JP2000068517A (en) * 1998-08-24 2000-03-03 Nec Corp Manufacture of semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05343686A (en) * 1992-06-04 1993-12-24 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0621455A (en) * 1992-06-30 1994-01-28 Sanyo Electric Co Ltd Thin-film transistor
JPH07169848A (en) * 1993-12-15 1995-07-04 Hitachi Ltd Semiconductor device and manufacture of it
JPH07202211A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Manufacture of semiconductor device
JPH07321324A (en) * 1994-05-19 1995-12-08 Hitachi Ltd Semiconductor device and its manufacturing method
JPH0864827A (en) * 1994-08-23 1996-03-08 Hitachi Ltd Semiconductor device and method of fabrication thereof
JPH11103057A (en) * 1997-03-17 1999-04-13 Toshiba Corp Semiconductor device
JP2000068517A (en) * 1998-08-24 2000-03-03 Nec Corp Manufacture of semiconductor device

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