JPH07321218A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, which has two kinds of gate oxide films different in width capable of being formed easily, by etching an oxide film made at the same time with a field oxide film thereby forming a thick gate oxide film. CONSTITUTION:After application of resist 11 on the topside of a field oxide film 9, the resist 11 is patterned, using a photomask where holes are bored only in the regions where a p-channel MOSFET and the gate electrode of an n-channel are to be formed in a region where a high voltage drive CMOS is to be formed, and the field oxide film 9 is wet-etched to form a residual film which becomes a thick gate oxide film 91 later. Then, a thin gate oxide film is formed, and further through a specified process, a CMOS IC, which has two kinds of gate oxide films different in thickness, is made. Hereby, the formation process of a gate oxide film can be simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, such as an IC for driving a liquid crystal display, in which a low voltage driving CMOS portion and a high voltage driving CMOS portion are integrated.

[0002]

2. Description of the Related Art For a driving IC for a liquid crystal flat panel display (hereinafter referred to as an LCD panel), there are many demands for the purpose of improving its display characteristics. For example, a driving IC for the purpose of improving the contrast characteristics as the LCD panel becomes larger and colorized.
There is a demand for higher withstand voltage, and with the increase in the amount of information displayed, there is a demand for higher speed operation in the logic circuit section. Here, in addition to the improvement of the operation speed of the logic circuit unit, the miniaturization of its components and the miniaturization of the chip are required for the purpose of cost reduction. Although the LCD panel driving IC is a CMOS IC, it is a low voltage driving CM that is driven by a low voltage of 5V or less
OS part and high voltage drive C driven by high voltage of several tens of V or more
The MOS part is integrated, and the thickness of the gate oxide film is as thin as 25 nm in the low voltage driving CMOS part and as thick as 150 nm in the high voltage driving CMOS part. In order to form such gate oxide films having different thicknesses, a method known in Japanese Patent Laid-Open No. 5-308128 is
After forming a thick oxide film for a gate oxide film of a high voltage drive CMOS, a gate electrode is formed from a polycrystalline silicon layer laminated on the oxide film, and a substrate surface exposed by etching using the gate electrode as a mask Low voltage drive on top
A thin oxide film for a MOS gate oxide film is formed, and a gate electrode is formed from a polycrystalline silicon layer laminated thereon. In this way, any gate oxide film is covered with the polycrystalline silicon layer in a clean state immediately after formation, and the resist does not directly contact the gate oxide film, so that the gate oxide film is not contaminated by the resist.

[0003]

However, although the above-mentioned known method can form a gate oxide film of good quality, two polycrystalline silicon depositions are required to form a gate oxide film having two different thicknesses. However, there is a drawback that the process becomes complicated and the cost becomes high. An object of the present invention is to provide a method for manufacturing a semiconductor device having two types of gate insulating films having different thicknesses, which can eliminate such drawbacks and can be easily formed.

[0004]

In order to achieve the above object, the present invention provides a MISFET having a relatively thick gate insulating film and a MISFET having a relatively thin gate insulating film on the surface side of the same semiconductor substrate. Is formed, MISF
In a method of manufacturing a semiconductor device in which a field insulating film thicker than any gate insulating film is formed on a substrate surface for separation between ETs, an insulating film formed by forming a thick gate insulating film at the same time as a field insulating film is etched. To be formed. A step of forming an insulating film in which a relatively thin gate insulating film is formed simultaneously with a field insulating film on the surface of a semiconductor substrate, and a relatively thick gate insulating film by selectively etching the insulating film formed simultaneously with the field insulating film. It is effective to include a step of leaving the film, a step of commonly covering both gate insulating films with a conductive layer, and a step of patterning this conductive layer to form a gate electrode of each MISFET. In that case, the conductive layer is preferably made of polycrystalline silicon. Also, a step of forming an insulating film formed on the surface of the semiconductor substrate at the same time as a relatively thin gate insulating film and a field insulating film, and forming a gate electrode made of a first conductive layer on the relatively thin gate insulating film. And a step of forming an interlayer insulating film covering the insulating film formed simultaneously with the first gate electrode and the field insulating film,
Etching the interlayer insulating film to open contact holes reaching the first gate electrode and the surface of the semiconductor substrate,
A step of etching an insulating film formed simultaneously with the interlayer insulating film and the field insulating film to leave a relatively thick gate insulating film, and forming a second conductive layer filling each contact hole and covering the thick gate insulating film It is effective to include a step and a step of forming a wiring and a gate electrode on the gate insulating film that is relatively thicker than the second conductive layer.
In that case, the first conductive layer is preferably made of polycrystalline silicon, and the second conductive layer is preferably made of metal.

[0005]

By forming a thick gate insulating film for a high voltage drive circuit by etching a thicker insulating film formed at the same time as the field insulating film, the thick gate insulating film forming step can be eliminated. In addition, by simultaneously forming the gate electrodes of both the low-voltage driving circuit and the high-voltage driving circuit from the polycrystalline silicon layer, or by forming the gate electrode of the high-voltage driving circuit with a metal, the method disclosed in the above publication is disclosed. By comparison, the polycrystalline silicon layer deposition process is performed only once, and only one conductivity type polycrystalline silicon layer is provided, so that the wiring and the like are simplified. Furthermore, if the etching process for the thick insulating film is performed after the etching process for forming the contact hole in the interlayer insulating film, it is not necessary to add a new process.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a manufacturing process of an LCD panel driving IC according to an embodiment of the present invention described in claim 2, and FIGS. 1 (a) to 1 (d) are the latter half of the manufacturing process, and FIG. ) ~
(d) is the first half of the manufacturing process.

In this manufacturing process, a p-type single crystal silicon substrate 1 is provided with a low voltage drive circuit section driven by a drive voltage of 5 V or less and a high voltage drive circuit driven by a drive voltage of several tens of V or more as a logic circuit. To manufacture an IC for driving an LCD panel in which the parts are integrated. FIG. 2A: A single crystal silicon substrate 1 prepared by the CZ method with a p-type and a resistivity of 10 Ω · cm is prepared, and C of the low voltage drive circuit section is prepared.
P-channel MOSFET in the MOS formation region 10
In the formation region 30 and the p-channel MOSFET formation region 50 in the CMOS formation planned region 20 of the high voltage drive circuit portion, the surface impurity concentration is 2 to 3 × 10 ¹⁶ cm ⁻³ and the diffusion depth is 4 to 5 μm.
m n wells 21 and 22 are formed.

FIG. 2B: Next, the n-channel MOSFET formation region 40 of the low voltage drive CMOS formation planned region 10
And a surface impurity concentration of 1 × 10 in the n-channel MOSFET formation region 60 of the high voltage drive CMOS formation planned region 20.
P-well diffusion layer 3 with a diffusion depth of 2-3 μm at about ¹⁷ cm ⁻³
At the same time as forming 1 and 32, the base oxide film 4 having a thickness of about 40 nm is formed.

FIG. 2C: A p-offset diffusion layer 5 having a surface impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of about 1.5 μm is formed on the surface layer of the n-well 22 on the surface layer of the p-well 32. Surface impurity concentration of 1 × 10 ¹⁷ cm ^-3 and diffusion depth of 1.5μ
The n offset diffusion layers 6 of about m are formed. FIG. 2 (d): n ⁺ guard ring 7 and p ⁺ guard ring 8 are formed for element isolation of high voltage driven CMOS 20, and then selective oxidation is performed using a silicon nitride film as a mask to form low voltage driven CMOS. A field oxide film 9 is formed to a thickness of about 600 nm except for the active region of the planned region 10, that is, a part where a thin gate oxide film will be formed later and the part of the high voltage driving CMOS formation planned region 20 where the source and drain contacts are formed. To do. Although not shown in the figure, a p-field diffusion layer is simultaneously formed in a desired portion under the field oxide film for element isolation of the low voltage drive CMOS 10.

FIG. 1 (a): This step is the point of the present invention. After the resist 11 is applied on the upper surface to a thickness of 400Å, the p-channel MOSFET and the n-channel MOSFET in the high voltage drive CMOS formation planned region 20 are formed. Photomask with a window opened only in the area where the gate electrode is to be formed
The resist 11 is patterned using a (reticle), and wet etching is performed using a 10 times diluted hydrofluoric acid aqueous solution so that the residual film 91 of the field oxide film 9 has a thickness of about 200 nm. The resist 11 is removed. This residual film 91 will be used later in the high voltage drive CMOS 20.
Is used as a gate oxide film.

FIG. 1B: Next, the exposed oxide film is etched with an aqueous solution of hydrofluoric acid to remove the thin base oxide film 4. The residual film 91 of the field oxide film having a thickness of 200 nm in the step of FIG. 1A is etched by about 50 nm to have a thickness of about 150 nm. After that, low voltage drive C
Thin gate oxide film 1 with a thickness of about 25 nm for MOS10
2 is formed, and a polycrystalline silicon layer 13 highly doped with n-type at a high concentration of about 400 nm is formed thereon by using the low pressure CVD method.
Deposited to a thickness of.

FIG. 1C: The polycrystalline silicon layer 13 is patterned to leave the gate electrodes 41, 42, 43 and 44 of the low voltage driving CMOS 10 and the high voltage driving CMOS 20. Figure 1 (d): Low-voltage driven and high-voltage driven CMOS
N ⁺ source / drain diffusion layers 45 and 46 are formed in the n-channel MOS portions 40 and 60, and p ⁺ source / drain diffusion layers 47 and 48 are formed in the p-channel MOS portions 30 and 50, respectively.

The subsequent steps are the same as in a normal CMOS process, and the wafer process is completed through an interlayer insulating film forming step, a contact hole forming step, a metal wiring step and a protective film forming step. 3 and 4 show a manufacturing process of an LCD panel driving IC according to another embodiment of the present invention described in claim 4, the first half of which is the same as that of FIG.
(a)-(c), FIG. 4 (a), (b) continue.

FIG. 3A: Same as the state of FIG. 2D, the formation process up to the field oxide film 9 having a thickness of 600 nm is completed. FIG. 3B: The base oxide film 4 is removed using a hydrofluoric acid aqueous solution. At this time, the field oxide film 9 is etched by about 50 nm, and the remaining film has a thickness of about 550 nm. After that, a thin gate oxide film 12 having a thickness of about 25 nm for the low voltage drive CMOS 10 is formed, and an n-type high concentration polycrystalline silicon layer 13 is deposited to a thickness of about 400 nm by a low pressure CVD method.

FIG. 3C: The polycrystalline silicon layer 13 is etched so as to leave the respective portions which will become the gate electrodes 41 and 42 of the low voltage drive CMOS 10. FIG. 4A: n ⁺ source / drain diffusion layers 45 and 46 are formed for the n-channel MOSFET sections 40 and 60 of the low voltage drive CMOS 10 and the high voltage drive CMOS 20, and for the p channel MOSFET sections 30 and 50. Is p
⁺ Source / drain diffusion layers 47 and 48 are formed. Next, after the interlayer insulating film 14 such as PSG having a thickness of 1 μm is formed by the CVD method, the contact hole forming step which is the point of the present invention is performed.

Photomasks (reticles) for forming contact holes are composed of source / drain diffusion layers 45, 46, 4
7, 48 and the gate electrode 4 of the low voltage driving CMOS 10
In addition to the parts connected to 1, 42, high voltage drive CMOS2
A pattern is also formed on the 0 gate portion. A resist pattern is formed using this mask. First, the interlayer insulating film 14 and the gate oxide film 12 are etched with an aqueous solution of hydrofluoric acid to taper the upper part of the contact hole, and then anisotropic dry etching is performed to form a substantially vertical cut. The lower part of the contact hole is formed. At this time, the contact holes 15 form the source / drain diffusion layers 45, 46, 47, 48.
Of the polycrystalline silicon, and contact holes (not shown) reach the gate electrodes 41 and 42 of polycrystalline silicon. In the gate portion of the high voltage drive CMOS 20, the interlayer insulating film 14 is formed by wet etching and anisotropic dry etching.
Is penetrated, and the anisotropic dry etching is terminated at the time when the residual film 91 having a thickness of about 150 nm of the field oxide film 9 is left to form the contact hole 16.

In the anisotropic dry etching, if the selection ratio of oxide film to silicon is 10 times or more, the interlayer insulating film 14 is formed.
The field oxide film 9 has about 40
The depth at which the surface silicon of the source / drain diffusion layers 45, 46, 47, 48 and the polycrystalline silicon on the surface of the gate electrodes 41, 42 are over-etched is about 40 nm during the 0 nm etching. No problem.
FIG. 4A shows a state in which the resist has been removed after the etching process is completed.

FIG. 4 (b): Metal wiring 17 contacting the source / drain diffusion layers 45, 46, 47 and 48 at the contact hole 15 by forming and patterning an Al layer,
Using the residual film 91 of the field oxide film as a gate oxide film, a metal wiring process is performed to form the gate electrodes 43 and 44 located in the contact holes 16 of the wet etching. That is, in this embodiment, the low voltage drive CMOS1
0 has a polycrystalline silicon gate and is a high voltage drive CMOS
20 has an Al gate. After that, the wafer process is completed through the protective film forming step.

[0019]

According to the present invention, a thick gate insulating film for a high voltage driving circuit or the like can be formed simultaneously with a field insulating film by etching to form a thick insulating film. To be simplified. Furthermore, by continuing the etching process of the thick insulating film with the etching process of the interlayer insulating film for forming the contact hole, it is possible to reduce the manufacturing cost because no additional process is required. When the gate electrode is made of polycrystalline silicon, a polycrystalline silicon layer of one conductivity type is formed, so that the wiring to the gate electrode is simplified and the chip area can be greatly reduced. With these, low voltage drive CMO
It has become possible to supply an LCD panel driving IC that integrates the S section and the high voltage driving CMOS section at a low price.

[Brief description of drawings]

FIG. 1 is a sectional view showing an essential part of the latter half of a manufacturing process of an LCD panel driving IC according to an embodiment of the present invention in the order of (a) to (d).

FIG. 2 is a cross-sectional view showing steps before the manufacturing step shown in FIG. 1 in the order of (a) to (d).

FIG. 3 is an LCD panel driving IC according to another embodiment of the present invention.
The first half of the process following the process shown in Fig. 2 of the manufacturing process
Sectional drawing which shows in order of (a), (b), (c)

FIG. 4 shows a step (a) following the manufacturing step shown in FIG.
Sectional view shown in order of (b)

[Explanation of symbols]

1 p-type silicon substrate 21, 22 n-well 31, 32 p-well 4 base oxide film 5 p-type offset diffusion layer 6 n-type offset diffusion layer 9 field oxide film 91 field oxide film residual film (gate oxide film) 12 gate oxide film 13 Polycrystalline Silicon Layer 14 Interlayer Insulating Film 15, 16 Contact Hole 17 Metal Wiring 41, 42, 43, 44 Gate Electrode 45, 46 n ⁺ Source / Drain Diffusion Layer 47, 48 p ⁺ Source / Drain Diffusion Layer 10 Low Voltage Driving Circuit part 20 High voltage drive circuit part 30, 50 p-channel MOSFET 40, 60 n-channel MOSFET

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/78 H01L 29/78 301 H

Claims (5)

[Claims] 1. A MISFET having a relatively thick gate insulating film and a MISFET having a relatively thin gate insulating film are formed on the surface side of the same semiconductor substrate.
In a method for manufacturing a semiconductor device in which a field insulating film thicker than any gate insulating film is formed on a substrate surface for mutual isolation, an insulating film formed by forming a thick gate insulating film at the same time as a field insulating film is etched. A method of manufacturing a semiconductor device, comprising: 2. A step of forming an insulating film in which a relatively thin gate insulating film is formed at the same time as a field insulating film on a surface of a semiconductor substrate, and a step of selectively etching the insulating film formed at the same time as the field insulating film to form a relative insulating film. A thick gate insulating film, a step of covering both gate insulating films with a conductive layer in common, and patterning of the conductive layer to form each MISF.
The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a gate electrode of ET. 3. The conductive layer is made of polycrystalline silicon.
A method for manufacturing a semiconductor device as described above. 4. A step of forming an insulating film formed on a surface of a semiconductor substrate at the same time as a relatively thin gate insulating film and a field insulating film, and a gate formed of a first conductive layer on the relatively thin gate insulating film. A step of forming an electrode, a step of forming an interlayer insulating film covering an insulating film formed simultaneously with the first gate electrode and the field insulating film, and a step of etching the interlayer insulating film to reach the surface of the first gate electrode and the semiconductor substrate A step of opening the contact holes and etching the insulating film formed at the same time as the interlayer insulating film and the field insulating film to leave a relatively thick gate insulating film, and filling each contact hole and covering the thick gate insulating film. Forming a conductive layer of the second conductive layer and a step of forming a gate electrode on the wiring and a relatively thick gate insulating film as compared with the second conductive layer. The method of manufacturing a semiconductor device Motomeko 1 wherein. 5. The first conductive layer is made of polycrystalline silicon,
The method of manufacturing a semiconductor device according to claim 4, wherein the second conductive layer is made of metal.