JPS6048904B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and particularly to a method of forming multilayer wiring.

In semiconductor integrated circuit devices, there is a great need to improve the degree of integration, and one way to meet this demand is to use multilayer wiring.

Although wiring usually has a two-layer structure of a polycrystalline silicon layer and an aluminum layer, multilayer wiring can be realized by forming one or more polycrystalline silicon layers between these two layers. FIG. 1 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device with multilayer wiring.

After providing a field oxide film 2 on a P-type silicon substrate 1,
A hole is opened and a gate oxide film 3 is provided.

After a first polycrystalline silicon layer 4 is provided on the oxide films 2 and 3, a region to become an active region is opened and phosphorus is diffused to form an N-type region 5. A silicon oxide film 6 is formed by oxidation again, and a second polycrystalline silicon layer is provided thereon.
Selective etching is performed using photolithography to form a pattern for the second polycrystalline silicon layer 7. Since a hydrofluoric acid-nitric acid solution is normally used for this selective etching, the silicon oxide film 6 is also attacked at the same time, and the silicon oxide film below the edge of the second polycrystalline silicon film 7 is removed. If manufacturing is continued with such an undercut, the aluminum wiring may break due to the step, the dielectric strength voltage between the silicon substrate 1 and the polycrystalline silicon 7 may decrease at the undercut, or there may be a significant In this case, there was a drawback that dielectric breakdown occurred at this point, resulting in a short circuit. In addition, the field silicon oxide film 2 is also attacked, and the so-called leakage current flows between the adjacent diffusion layers 5 due to the reduction of the original field oxide film 2 due to the reduction of the original field oxide film 2 to the aluminum and nium 9 wired on it. There was a drawback that a parasitic MOS type field effect transistor was generated. For this purpose, a method may be considered in which a silicon oxide film is disposed in the peripheral area, but in this case, a recess is formed under the end of the silicon nitride film, and there is a risk of disconnection of the multilayer wiring. Moreover, an extra patterning step is required to provide this silicon nitride film in the peripheral area. 5. An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing a semiconductor integrated circuit device with multilayer interconnection without disconnection due to steps.

A feature of the present invention is that in a method for manufacturing a semiconductor integrated circuit device with multilayer wiring formed by laminating a lower wiring layer via an insulating material layer, a silicon oxide film and a silicon nitride film are laminated on the lower wiring layer, An upper wiring layer is formed on the silicon nitride film, and by introducing phosphorus into the exposed portion of the silicon nitride film, the exposed portion of the film is transformed into phosphorus glass. The present invention relates to a method of manufacturing a semiconductor integrated circuit device in which glass is heat-treated to form silicon oxide.

In the present invention, since no undesired recesses are formed in any part of the insulating layer such as a silicon oxide film, the wiring layout can be freely defined.

In addition, the manufacturing process can be short-circuited because the selective etching process for silicon oxide films and the like can be omitted. Furthermore, the parts where the multilayer wiring intersects each other are at regular intervals, and no unevenness occurs, resulting in a preferable multilayer structure. Also, since each part is at regular intervals, the capacitors between each wiring can be reduced. becomes a constant value, which makes it easier for the IC to set the predetermined value. Next, the present invention will be explained by examples. FIGS. 2 through 6 are cross-sectional views of a process in which the method of the present invention is applied to a three-layer N-channel silicon gate MOS type integrated circuit device.

After forming an oxide film with a thickness of approximately 1 μm on the surface of the P-type silicon substrate 11, the field oxide film 12 is left in areas other than the active regions of transistors etc. by ordinary photolithography.
figure).

Subsequently, after forming a gate oxide film 13 with a thickness of about 1000 Λ, a first polycrystalline silicon layer with a thickness of about 5000 Λ is formed by vapor phase growth, etc., leaving the gate electrode part, wiring part 14, etc. of the transistor. The first polycrystalline silicon layer is etched as shown in FIG.

Subsequently, after removing the gate oxide film 13 in the portion of the substrate 11 where the diffusion layer is to be formed by etching, phosphorus is diffused into the substrate 11 and the first polycrystalline silicon layer 14 at 1000° C. to inject N into the substrate 11. While forming the type region 15, the polycrystalline silicon layer 14 is changed to N type, and the field oxide film 12 is changed to phosphorous glass.

A silicon oxide film 16 is again formed to a thickness of about 5,000 Å by thermal oxidation, and a silicon nitride oxide film 17 of several hundred Å thick is deposited thereon as a protection (FIG. 4). Next, the thickness is about 50
A second polycrystalline silicon layer 18 of 0.00 is formed, and a pattern is formed by etching this layer 18 with a hydrofluoric acid-nitric acid solution using photolithography.

Since the silicon nitride film 17 is not attacked by the hydrofluoric acid-nitric acid based etching solution, it protects the underlying silicon oxide film 16. Therefore, an undercut as shown in FIG. 1 does not occur. Subsequently, phosphorus is diffused into the second polycrystalline silicon layer 18 and the silicon nitride oxide film 17. The exposed portion of the silicon nitride film 17 changes into phosphorus glass 9 due to phosphorus diffusion.
Therefore, the step of removing the silicon nitride oxide film 17 is not necessary (FIG. 5). Silicon oxide film 2 is formed by thermal oxidation again.
? will be established.

Since the silicon nitride film is altered in quality by introducing impurities in this way, it becomes possible to form thermally oxidized silicon. That is, if the silicon nitride film remains as it is, the silicon oxide film 20 will not be formed by thermal oxidation because it is an oxidation-resistant film, and a predetermined thick insulating layer will not be obtained. However, since the silicon nitride film is changed into phosphorus glass, and this phosphorus glass is not an oxidation-resistant film, a silicon oxide film 20 is formed by thermal oxidation, thereby obtaining a predetermined thick insulating layer. Become. A three-layer N-channel MOS is created by opening holes using photolithography and providing aluminum wiring 21.
The integrated circuit device is completed (Fig. 6). The above embodiment has been explained using polycrystalline silicon as the metal wiring layer and silicon nitride as the protective film, but the method of the present invention is applicable not only to silicon and silicon nitride but also to various metals. can also be applied.

For example, when tantalum is used as the metal, the method of the present invention can be carried out using silicon nitride as the protective film. According to the present invention, disconnections and short circuits due to steps, or parasitic MO
The effect is great because a semiconductor integrated circuit device with multilayer wiring without the occurrence of SFET can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device with multilayer interconnection, and FIGS. 2 to 6 show steps in the case where the method of the present invention is applied to a three-layer N-channel silicon gate MOS integrated circuit device. FIG. 1, 11... P-type silicon substrate, 2, 12...
...Field oxide film, 3,13...Gate oxide film, 4,14...First polycrystalline silicon film, 5,15...N type region , 6, 16...
...Silicon oxide film, 7...Second polycrystalline silicon film, 8...Silicon oxide film, 9, 21.
...Aluminum wiring, 17...Silicon nitride film, 18...Second polycrystalline silicon 9.
...phosphorus glass, 20 ... silicon oxide film.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device with multilayer wiring formed by laminating a lower wiring layer and an upper wiring layer via an insulating material layer, a silicon oxide film and a silicon nitride film are laminated on the lower wiring layer, An upper wiring layer is formed on the silicon nitride film, and by introducing phosphorus into the exposed portion of the silicon nitride film, the exposed portion of the film is transformed into phosphorus glass. 1. A method for manufacturing a semiconductor integrated circuit device, which comprises converting silicon into silicon oxide by thermal oxidation.