JPH06334118A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To eliminate the bias dependence of a capacitor on a depletion layer by a method wherein a capacitor lower-part electrode is constituted of two layers by a lower layer composed of polysilicon and by an upper layer composed of a high-melting-point metal or its silicide and a capacitor upper-part electrode is constituted of one layer by a high-melting-point metal or its silicide. CONSTITUTION:By the thermal oxidation of a semiconductor substrate 1, a gate oxide film 3 is formed in an element formation region. An N<+> polysilicon layer and a high-melting-point metal silicide layer are formed on it, and they are patterned. Thereby, a gate electrode 6 which is composed of the N<+> polysilicon layer 4 and the high-melting-point metal silicide layer 5 is formed in the element formation region, and, at the same time, a capacitor lower-part electrode 7 which is composed of an N<+> polysilicon layer 4' and a high-melting- point metal silicide layer 5' is formed in a capacitor formation region. Then, ions are implanted, a shallow diffused layer 8 is formed, an oxide-film sidewall 9 is then formed, ions are implanted, and a deep diffused layer 10 is formed. Then, a high-melting-point metal silicide layer is formed, it is patterned, and an upper-part electrode 12 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high precision capacitor suitable for analog circuits and a method for manufacturing the same.

Conventionally, as a semiconductor device as a high-precision capacitor suitable for an analog circuit, there is a semiconductor device in which a lower electrode and an upper electrode are each made of a single layer of metal (see JP-A-2-43761 and JP-A2-11911).
70) has recently used a refractory metal silicide. In other words, in MOS transistor technology,
In order to reduce the layer resistance of the gate electrode, refractory metal silicide is added to the polysilicon layer. In this case, if the refractory metal silicide is directly added on the thin gate oxide film, the breakdown voltage will be deteriorated by the high temperature heat treatment in the subsequent step.
A refractory silicide layer is formed on the polysilicon layer. Utilizing this, there is a structure in which the capacitor lower electrode is made of polysilicon and the capacitor upper electrode is made of a two-layer structure of refractory metal silicide / polysilicon. This will be described with reference to FIGS. 4, 5 and 6.

First, referring to FIG. 4A, an oxide film 2'is formed on a semiconductor substrate 1 made of, for example, P ^- type single crystal silicon, and a heat-resistant insulating film formed thereon, for example, a silicon nitride film. A field oxide film 2 for element isolation is formed by thermal oxidation using (not shown) as a mask. Further thereon, an N ⁺ polysilicon layer 2 as a capacitor lower electrode is formed.
0 is formed by the CVD method and patterned.

Next, referring to FIG. 4B, a capacitor insulating film 21 is formed. This capacitor insulating film 21
Is a three-layer structure ONO (Oxide / Nitri)
de / Oxide) film. That is, the N ⁺ polysilicon layer 20 is thermally oxidized to form an oxide film, and the CVD film is formed on the oxide film.
A nitride film is formed by the method, and the nitride film is further oxidized by thermal oxidation to form an oxide film thereon. Next, the capacitor insulating film 21 other than the capacitor formation region on the element isolation field oxide film 2 is removed by photolithography.

Next, referring to FIG. 4C, the capacitor formation region is covered with the photoresist layer 22 by a photolithography method, and the oxide film 2'which is no longer needed in the element formation region is removed by wet etching. .

Next, referring to FIG. 5D, the gate oxide film 3 is formed by thermally oxidizing the semiconductor substrate 1.

Next, referring to FIG. 5E, an N ⁺ polysilicon layer and a refractory metal silicide layer are formed on the N ⁺ polysilicon layer and patterned simultaneously by a photolithography method. Thus, the gate electrode 6 made of the N ⁺ polysilicon layer 4 and the refractory metal silicide layer 5 is formed in the element formation region, and at the same time, the N ⁺ polysilicon layer 4 "and the N ⁺ polysilicon layer 4" are formed in the capacitor formation region. A capacitor upper electrode 23 composed of the refractory metal silicide layer 5 ″ is formed.

Next, referring to FIG. 5F, a diffusion layer is formed. That is, first, a shallow N ^{− is formed} by ion implantation.
A diffusion layer 9 is formed, and then an oxide film side wall 8 is formed by etching back by anisotropic dry etching, and then a deep N ⁺ diffusion layer 10 is formed by ion implantation.

Finally, referring to FIG. 6G, an interlayer insulating film 14 is formed, and the interlayer insulating film 14 is provided with contact holes 15 to the diffusion layers 9 and 10 and a gate electrode 6. The contact hole 16, the contact hole 17 to the capacitor lower electrode 20, and the contact hole 18 to the capacitor upper electrode 23 are simultaneously opened, and the aluminum electrode 19 is formed on these contact holes.

Thus, a capacitor having a lower electrode composed of a polysilicon layer and an upper electrode composed of a two-layer structure of refractory metal silicide / polysilicon is obtained.

[0011]

However, as shown in FIG.
In the conventional capacitor manufactured as shown in FIG. 6,
Since the upper electrode having a two-layer structure is formed after the formation of the lower electrode of one layer, the manufacturing process becomes complicated.
There is a problem in that the number of photolithography steps is increased by three compared with the normal CMOS process, and therefore the manufacturing cost is increased. Further, since the lower electrode is made of polysilicon, when a bias is applied to the capacitor, the depletion layer extends in the polysilicon that is a semiconductor, and therefore the capacitance of the capacitor depends on the bias and a highly accurate capacitance can be obtained. As a result, there is also a problem that it is not suitable for a capacitor used in an analog circuit.

Therefore, it is an object of the present invention to provide a highly accurate capacitor which has a low manufacturing cost. Another object is to provide a method for manufacturing the above capacitor.

[0013]

In order to solve the above-mentioned problems, according to the present invention, the capacitor lower electrode is composed of two layers of a lower layer made of polysilicon and an upper layer made of a refractory metal or its silicide, The capacitor upper electrode is composed of a layer of refractory metal or its silicide.

[0014]

According to the above-mentioned means, since the lower electrode is made of a refractory metal or its silicide, the depletion layer does not extend even if a bias is applied, and therefore the capacitance of the capacitor does not depend on the bias.

[0015]

1 and 2 are views for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, referring to FIG. 1A, an oxide film (not shown) is formed on a semiconductor substrate 1 made of, for example, P ⁻ type single crystal silicon, and a heat resistant insulating film formed thereon ( For example, a field oxide film 2 for element isolation is formed by thermal oxidation using a silicon nitride film (not shown) as a mask. After that, the heat resistant insulating film and the oxide film are removed, and then the gate oxide film 3 is formed in the element formation region by thermal oxidation of the semiconductor substrate 1. An N ⁺ polysilicon layer having a thickness of 1000 to 3000 Å and a refractory metal silicide (for example, WSi) layer having a thickness of 1000 to 3000 Å are formed thereon, and simultaneously patterned by a photolithography method.
As a result, the N ⁺ polysilicon layer 4 is formed in the element formation region.
And the gate electrode 6 made of the refractory metal silicide layer 5 and at the same time, the capacitor lower electrode 7 made of the N ⁺ polysilicon layer 4'and the refractory metal silicide layer 5'is formed in the capacitor formation region. To do.

Next, referring to FIG. 1B, a diffusion layer is formed. That is, first, a shallow N ^{− is formed} by ion implantation.
The diffusion layer 9 is formed, then the oxide film side wall 9 is formed by back etching by anisotropic dry etching, and then the deep diffusion layer 10 is formed by ion implantation.

Next, referring to FIG. 1C, the capacitor insulating film 11 is formed. This capacitor insulating film 11
Is, for example, a three-layer structure. That is, an oxide film having a thickness of 100 to 300 Å is formed by the CVD method, and the CVD film is formed on the oxide film.
Then, a nitride film having a thickness of 100 to 300 Å is formed by the method, and an oxide film having a thickness of 100 to 300 Å is further formed thereon by the CVD method.

Next, referring to FIG. 2D, a refractory metal silicide layer is formed and patterned by photolithography to form a capacitor upper electrode 12. Next, referring to FIG. 2E, the capacitor insulating film 11 other than the capacitor formation region is removed by a photolithography method. In other words, if the nitride film remains in the element formation region, hydrogen does not pass through the nitride film during hydrogen alloying in the damage recovery process performed before the cover film is applied, and the element (transistor) damage occurs. It is impossible to recover.

Finally, referring to FIG. 2F, the interlayer insulating film 14 is formed, and the interlayer insulating film 14 is provided with the contact holes 15 to the diffusion layers 9 and 10 and the gate electrode 6. A contact hole 16, a contact hole 17 for the capacitor lower electrode 7, and a contact hole 18 for the capacitor upper electrode 13 are simultaneously opened, and an aluminum electrode 19 is formed on these contact holes.

In this way, the number of photolithography steps is reduced by 1 as compared with the conventional case, and the lower electrode is composed of a two-layer structure of refractory metal silicide / polysilicon and the upper electrode is composed of refractory metal silicide. The obtained capacitor is obtained.

FIG. 3 is a diagram for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention. In the second embodiment, the process shown in FIG. 3E is carried out through the process shown in FIGS. 1A to 1D, but in this case, the capacitor insulating film 11 is formed by the CVD method. Thickness 200-700
Å Single layer oxide film. Therefore, it is not necessary to remove the capacitor insulating film 11 other than the capacitor region, and therefore, as shown in FIG. 3F, the insulating film 11 also exists in the element formation region. In this way, according to the second embodiment of the present invention, the number of photolithography steps is reduced by one and the manufacturing process is reduced, as compared with the above-described first embodiment.

Although the N-channel MOS transistor is formed simultaneously with the formation of the capacitor in the above-mentioned embodiment, the present invention can be applied to the CMOS technology in which the P-channel MOS transistor is formed at the same time. Also,
Although the refractory metal silicide is used in the above-described embodiments, a refractory metal (for example, W) having the same degree of elongation of the depletion layer may be used.

[0024]

As described above, according to the present invention, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the upper and lower electrodes of the capacitor are made of refractory metal or silicide thereof. , There is no bias dependence of the depletion layer of the capacitor, and therefore a highly accurate capacitance can be obtained, which is suitable for analog circuits. For example, the bias dependence of the capacitance of a capacitor is conventionally 0.00
It was about 5% / V, but 0.01% in the present invention.
/ V or less.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 6 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type substrate 2 ... Field oxide film 3 ... Gate oxide film 4, 4 ', 4 "... N ⁺ polysilicon layer 5, 5', 5" ... Refractory metal silicide layer 6 ... Gate electrode 7 Capacitor lower electrode 8 Oxide film side wall 9 N ^- diffusion layer 10 N ⁺ diffusion layer 11 Capacitor insulating film 12 Refractory metal silicide layer 13 Photoresist layer 14 Interlayer insulating film 15, 16, 17, 18 Contact hole 19 Aluminum layer 20 N ⁺ polysilicon layer (capacitor lower electrode) 21 Capacitor insulating film (ONO film) 22 Photoresist layer 23 Capacitor upper electrode

Claims (5)

[Claims] 1. A lower layer (4 ') made of polysilicon and an upper layer (5') made of refractory metal or its silicide.
A capacitor lower electrode (7) including: a capacitor lower electrode (12) made of a refractory metal or a silicide thereof; and a capacitor insulating layer (11, 11 ′) provided between the lower electrode and the upper electrode. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the capacitor insulating layer comprises three layers of an oxide film, a nitride film and an oxide film. 3. The semiconductor device according to claim 1, wherein the capacitor insulating layer is made of a single-layer oxide film. 4. A capacitor lower electrode (7) including a lower layer (4 ′) made of polysilicon and an upper layer (5 ′) made of a refractory metal or its silicide, and a lower layer made of polysilicon on a semiconductor substrate (1). 4) and a transistor gate electrode (6) including an upper layer (5) made of a refractory metal or its silicide, and a capacitor insulating layer (11,
11 ') and a step of forming a capacitor lower electrode (12) made of a refractory metal or its silicide on the capacitor insulating layer. 5. A step of forming a field insulating layer (2) in a field region of a semiconductor substrate (1), and a gate insulating layer (3) in an active region of the semiconductor substrate. And forming a capacitor lower electrode (7) including a lower layer (4 ') made of polysilicon and an upper layer (5') made of refractory metal or its silicide on the field insulating layer. A transistor gate electrode (6) including a lower layer (4) made of polysilicon and an upper layer (5) made of a refractory metal or its silicide on the insulating layer.
Forming a capacitor insulating layer (11,
11 ') and a step of forming a capacitor lower electrode (12) made of a refractory metal or its silicide on the capacitor insulating layer.