JPS5946108B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5946108B2 JPS5946108B2 JP51058667A JP5866776A JPS5946108B2 JP S5946108 B2 JPS5946108 B2 JP S5946108B2 JP 51058667 A JP51058667 A JP 51058667A JP 5866776 A JP5866776 A JP 5866776A JP S5946108 B2 JPS5946108 B2 JP S5946108B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer film
- layer
- manufacturing
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特に食刻時のオーバー
ハングの防止に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to prevention of overhang during etching.
従来の電界効果型(以下MOS型と略す)半導体装置の
製造方法を第1図a−gにしたがつて説明する。一導電
型例えばP型半導体基板1上に一様に熱酸化法により約
7000λのフィールド酸化硅素膜2を形成し(同図a
)通常の写真食刻技術で選択的に前記基板3を露出させ
る(同図b)、該露出基板3上に1000〜1500入
のゲート酸化硅素膜4を熱酸化法により形成し(同図c
)、さらに約4000Λの多結晶硅素膜5を全面に一様
に形成する(同図d)、通常の写真食刻技術により該多
結晶硅素膜5を選択的に除去しゲート電極6を形成する
(同図e)。A conventional method for manufacturing a field effect type (hereinafter abbreviated as MOS type) semiconductor device will be explained with reference to FIGS. 1a to 1g. A field silicon oxide film 2 having a thickness of about 7000λ is uniformly formed on a semiconductor substrate 1 of one conductivity type, for example, a P-type, by thermal oxidation method (Fig.
) The substrate 3 is selectively exposed by ordinary photolithography (b in the same figure), and a gate silicon oxide film 4 of 1,000 to 1,500 layers is formed on the exposed substrate 3 by a thermal oxidation method (c in the figure).
), and then a polycrystalline silicon film 5 of about 4000 Λ is uniformly formed over the entire surface (d in the same figure), and the polycrystalline silicon film 5 is selectively removed by ordinary photolithography to form a gate electrode 6. (Figure e).
該多結晶硅素膜6をマスクとして、前記ゲート酸化硅素
膜4を緩衝弗酸溶液で選択的に除去し、前記基板を露出
する。しかる後、基板1と反対導電型の不純物層Tを形
成しソースまたはドレイン領域とする(同図f)。その
後、熱酸化法および(CVD法により 酸化硅素膜10
を形成した後、基板1および多結晶硅素膜6とにコンタ
クトホールを形成し、アルミニウム等の導電体層11で
配線してMOS型半導体装置を得る。(同図g)。かか
る製造方法においては同図fに示すように、ゲート酸化
膜4を、多結晶硅素膜5をマスクとして食刻する際に、
フィールド酸化膜2も同時に食刻されるので、フィール
ド酸化膜2上の多結晶硅素膜5はオーバーハング状態9
になる。Using the polycrystalline silicon film 6 as a mask, the gate silicon oxide film 4 is selectively removed with a buffered hydrofluoric acid solution to expose the substrate. Thereafter, an impurity layer T having a conductivity type opposite to that of the substrate 1 is formed to serve as a source or drain region (f in the same figure). After that, a silicon oxide film 10 is formed by thermal oxidation method and (CVD method).
After forming, contact holes are formed in the substrate 1 and the polycrystalline silicon film 6, and wiring is performed using a conductor layer 11 such as aluminum to obtain a MOS type semiconductor device. (Figure g). In this manufacturing method, as shown in FIG.
Since the field oxide film 2 is also etched at the same time, the polycrystalline silicon film 5 on the field oxide film 2 is in an overhang state 9.
become.
オーバーハング9のサイドエツチング量は第2図に示す
ように、ゲート酸化膜4上の多結晶硅素膜6のオーバー
ハング8のサイドエツチング量とほとんど同じaである
が、深さ方向はゲート酸化膜4の部分ではシリコン基板
1が食刻に対するストツパ一となり、ゲート酸化膜4の
厚さb以上に食刻されないが、フイールド酸化膜2の部
分は、ゲート酸化膜4の厚さより厚くB2まで食刻され
る。その後第1図gのように熱酸化すると、ゲート酸化
膜4の部分ではシリコン基板1と多結晶硅素膜6の両方
からほぼ同一速度で成長し、b/2の酸化膜厚42以上
でオーバーハング8はなくなる。As shown in FIG. 2, the side etching amount of the overhang 9 is almost the same as the side etching amount a of the overhang 8 of the polycrystalline silicon film 6 on the gate oxide film 4, but in the depth direction, the gate oxide film In the part 4, the silicon substrate 1 acts as a stopper against etching and is not etched to a thickness greater than the thickness b of the gate oxide film 4, but in the part of the field oxide film 2, it is etched to a thickness B2 which is thicker than the thickness of the gate oxide film 4. be done. After that, when thermal oxidation is performed as shown in FIG. 8 will disappear.
しかし、フイールド酸化膜2の部分では成長速度は遅い
ので、酸化膜グの成長厚さ1が薄く、オーバーハング9
′は存在し、かつ、段差cはゲート酸化膜上での段差よ
り大きくなる。次に、CVD法でSlO2膜を被膜して
もこの段差はほとんど減少しないので、金層層の被着時
にこの段差部でいわゆる段切れ現象を起すことが多い。However, since the growth rate is slow in the field oxide film 2, the growth thickness 1 of the oxide film 2 is small and the overhang 9
' exists, and the step c is larger than the step on the gate oxide film. Next, even if a SlO2 film is coated by the CVD method, this step difference is hardly reduced, so that a so-called step breakage phenomenon often occurs at this step portion when a gold layer is deposited.
また第3図に示すように、第2図の9′で示すオーバー
ハングに対応するオーバーハング11が存在する部分に
、アルミニウム等の金属層12を蒸着法等により厚く形
成すれば段切れは生じない場合でも、食刻液がオーバー
ハング11の部分に浸透し、金属層にはオーバーハング
11側から食刻がおこり、パターン幅の細部12′や断
線を生じるという不都合が起る。Furthermore, as shown in FIG. 3, if a thick metal layer 12 of aluminum or the like is formed by vapor deposition or the like in the area where the overhang 11 corresponding to the overhang 9' in FIG. Even if there is no etching liquid, the etching liquid will penetrate into the overhang 11, and the metal layer will be etched from the overhang 11 side, causing problems such as pattern width details 12' and wire breakage.
また第1図cの工程で全面、すなわちゲート酸化膜4お
よびフイールド酸化膜2全面に窒化硅素膜を形成するこ
とによりオーバーエツチングを防止した製造方法も公知
であるが、ゲート酸化膜4上の窒化硅素膜厚の制御が困
難なことと複合絶縁膜ゲートに基因する半導体装置の特
性への悪影響などの点で好ましくない。There is also a known manufacturing method in which overetching is prevented by forming a silicon nitride film on the entire surface of the gate oxide film 4 and the field oxide film 2 in the step shown in FIG. This is undesirable because it is difficult to control the silicon film thickness and there is an adverse effect on the characteristics of the semiconductor device due to the composite insulating film gate.
例えば、MOS型トランジスタの製造時に、ゲート酸化
膜上に窒化硅素膜を形成すると、ゲート領域では反転層
ができにくいことがある。本発明は上記の従来例の欠点
に着目し、食刻時のオーバーハングを防止して、食刻後
の電極等の形成が段切れや断線が無く行なわれるように
した半導体装置の製造方法を提供するものである。For example, when a silicon nitride film is formed on a gate oxide film when manufacturing a MOS transistor, an inversion layer may be difficult to form in the gate region. The present invention focuses on the above-mentioned drawbacks of the conventional example, and provides a method for manufacturing a semiconductor device in which overhang during etching is prevented and electrodes, etc., are formed after etching without breakage or disconnection. This is what we provide.
以下本発明実施例にしたがつて説明する。第4図a−g
は本発明の一実施例を示す工程図であり、基板、例えば
P型半導体基板21上に熱酸化法により一様に第一層膜
の厚い部分、例えば二酸化硅素膜即ちフイールド酸化硅
素膜22を例えば6000人形成した後(同図a)、通
常の食刻技術で所定のパターンを形成する(同図b)。Embodiments of the present invention will be explained below. Figure 4 a-g
1 is a process diagram showing an embodiment of the present invention, in which a thick portion of the first layer film, for example, a silicon dioxide film, that is, a field silicon oxide film 22 is uniformly formed on a substrate, for example, a P-type semiconductor substrate 21, by a thermal oxidation method. For example, after forming 6,000 patterns (FIG. 1A), a predetermined pattern is formed using a normal etching technique (FIG. 2B).
前記食刻により露出した基板24に第一層膜の薄い部分
例えば約1000人の二酸化硅素膜即ちゲート酸化硅素
膜25を形成する(同図c)。次に第二層膜例えば多結
晶硅素膜26を全面に一様に約4000λ形成する(同
図d)。通常の写真食刻技術により、多結晶硅素膜26
を所定のパターン27に形成し、ゲート電極とする。On the substrate 24 exposed by the etching, a thin portion of the first layer, for example, about 1,000 silicon dioxide films, ie, a gate silicon oxide film 25, is formed (FIG. 3(c)). Next, a second layer film, for example a polycrystalline silicon film 26, is formed uniformly over the entire surface with a thickness of about 4000 λ (FIG. 4(d)). A polycrystalline silicon film 26 is formed using ordinary photolithography technology.
is formed into a predetermined pattern 27 and used as a gate electrode.
次に、前記第一層膜の厚い部分、即ちフイールド酸化硅
素膜上に端部を有する第二層膜、即ち多結晶硅素膜27
の一部あるいは全面と、前記多結晶硅素膜27の端部と
接するフイールド酸化硅素膜22の一部あるいは全面の
両者にまたがつて、第一層膜の食刻マスクとなる第三層
膜、例えばフオトレジスト膜28を形成する。(同図e
)。しかる後、前記多結晶硅素膜27と、フオトレジス
ト膜28の両者を食刻マスクとして、前記ゲート酸化硅
素膜25を食刻し、前記半導体基板29を露出する。こ
のときフイールド酸化硅素膜22も同時に食刻されるが
、従来法と異なり、フイールド酸化硅素膜22はフオト
レジスト膜28でマスクされているので、多結晶硅素膜
の端部30はオーバーハング状態にならない。フイール
ド酸化膜22上の多結晶硅素膜27の段差30はゲート
酸化膜25を食刻後も変化せず、前記フオトレジスト膜
の端部31でフイールド酸化硅素膜22に段差が生じる
のみである。ところで、前記段差部31では前記フオト
レジスト膜28はオーバーハング状態になる場合がある
が、前記フオトレジスト膜28は除去するので、本発明
の効果に何ら影響を及ぼさない(同図f)。Next, a second layer film, that is, a polycrystalline silicon film 27 having an end portion on the thick portion of the first layer film, that is, the field silicon oxide film.
and a third layer film serving as an etching mask for the first layer film, spanning both a part or the entire surface of the field silicon oxide film 22 that is in contact with the end of the polycrystalline silicon film 27; For example, a photoresist film 28 is formed. (Figure e
). Thereafter, using both the polycrystalline silicon film 27 and the photoresist film 28 as etching masks, the gate silicon oxide film 25 is etched to expose the semiconductor substrate 29. At this time, the field silicon oxide film 22 is also etched at the same time, but unlike the conventional method, the field silicon oxide film 22 is masked with a photoresist film 28, so the end portion 30 of the polycrystalline silicon film is in an overhang state. No. The step 30 of the polycrystalline silicon film 27 on the field oxide film 22 does not change even after etching the gate oxide film 25, and only a step is formed in the field silicon oxide film 22 at the end portion 31 of the photoresist film. By the way, although the photoresist film 28 may be in an overhang state at the stepped portion 31, since the photoresist film 28 is removed, this does not affect the effects of the present invention in any way (f in the same figure).
次に前記フオトレジスト膜を除去し、基板露出部29に
基板と反対導電型不純物層を形成したのち、熱酸化法あ
るいはCVD法により、露出半導体基板29および多結
晶硅素膜27あるいは全面に、二酸化硅素膜32を約3
000λ形成する。さらに電極コンタクトのための孔を
選択的に形成しアルミニウム等の金属配線33を行なう
。(同図g)本実施例によればフイールド酸化膜22上
での多結晶硅素膜27の端部でアンダーカツトが生じな
いので、不純物層形成後の熱酸化膜32は薄くてもよく
、かつ金属配線33の厚さが多結晶硅素膜27の厚さよ
り薄くても断線を生じない。Next, the photoresist film is removed and an impurity layer of a conductivity type opposite to that of the substrate is formed in the exposed portion 29 of the substrate. Then, by thermal oxidation or CVD, the exposed semiconductor substrate 29 and the polycrystalline silicon film 27 or the entire surface are coated with dioxide. The silicon film 32 is approximately 3
000λ is formed. Furthermore, holes for electrode contacts are selectively formed and metal wiring 33 made of aluminum or the like is formed. (G in the same figure) According to this embodiment, no undercut occurs at the end of the polycrystalline silicon film 27 on the field oxide film 22, so the thermal oxide film 32 after forming the impurity layer may be thin, and Even if the thickness of the metal wiring 33 is thinner than the thickness of the polycrystalline silicon film 27, disconnection will not occur.
また、多結晶硅素膜27をゲート電極として用いたMO
S型電界効果トランジスタ、いわゆるシリコンゲートM
OSの特徴である多結晶硅素膜27をマスクとしてのソ
ース、ドレイン領域の形成方法は何ら損なわれず、従来
法と同様にセルフアラインで形成することができる。上
記実施例で、第三層膜としてSi3N4膜を用いても、
また、第二層膜としてMO等の金属膜を用いてもよいこ
とはいうまでもない。Moreover, an MO using the polycrystalline silicon film 27 as a gate electrode
S-type field effect transistor, so-called silicon gate M
The method of forming the source and drain regions using the polycrystalline silicon film 27 as a mask, which is a feature of the OS, is not impaired in any way, and can be formed in a self-aligned manner as in the conventional method. In the above embodiment, even if a Si3N4 film is used as the third layer film,
Furthermore, it goes without saying that a metal film such as MO may be used as the second layer film.
本発明は上記実施例に限らず、例えば、基板に多結晶硅
素膜、第一層膜に気相成長二酸化硅素膜あるいはSl3
N4膜、第二層膜にそれぞれSl3N4膜あるいは気相
成長二酸化硅素膜、第三層膜にフオトレジストを用いて
もよいことはいうまでもない。The present invention is not limited to the above-mentioned embodiments. For example, the substrate is a polycrystalline silicon film, the first layer film is a vapor-grown silicon dioxide film or
Needless to say, an Sl3N4 film or a vapor-grown silicon dioxide film may be used for the N4 film and the second layer film, and a photoresist may be used for the third layer film.
以上説明したように本発明の半導体装置の製造方法は、
第一層膜の食刻時には第一層膜の厚脱領域と同領域上の
第二層膜とにわたつて、第二層膜の端部を覆うように第
三層膜が形成されているため、この部分で第一層膜のオ
ーバーエツチングが行なわれず、従来の様に同部分に食
刻液が浸透しない。As explained above, the method for manufacturing a semiconductor device of the present invention includes:
When the first layer film is etched, a third layer film is formed so as to cover the edge of the second layer film, spanning the thickened area of the first layer film and the second layer film on the same area. Therefore, over-etching of the first layer film is not performed in this portion, and the etching liquid does not penetrate into the same portion as in the conventional method.
従つて、その後の電極等の形成は段切れや食刻液による
細部が生じて断線が起ることはない。また、オーバーエ
ツチングが行なわれないため、第一層膜と第二層膜との
段差は急峻にはならず、その後に形成する電極等の厚さ
は、従来のように厚くなくても、第二層膜の厚さより薄
くても段切れは起らない。さらに本発明は、公知技術の
ようにオーバーエツチングを防止するための窒化硅素膜
を用いる必要はないため、MOS型トランジスタの製造
に際してはゲート絶縁膜が複合型にならず、特性の向上
が図れるものである。Therefore, during the subsequent formation of electrodes, etc., there will be no disconnection due to step breaks or details caused by the etching solution. In addition, since over-etching is not performed, the difference in level between the first layer film and the second layer film does not become steep, and the thickness of the electrodes etc. formed subsequently does not have to be as thick as in the past. Even if it is thinner than the thickness of the two-layer film, no breakage will occur. Furthermore, since the present invention does not require the use of a silicon nitride film to prevent overetching as in the known technology, the gate insulating film does not become a composite type when manufacturing a MOS transistor, and the characteristics can be improved. It is.
すなわち、本発明は種々の半導体装置の製造において、
周知の製造技術を何等複雑にすることなく、その半導体
装置の信頼性を高め、製造時における歩留りを向上させ
るものであつて。That is, the present invention is applicable to manufacturing various semiconductor devices.
The present invention is intended to enhance the reliability of the semiconductor device and improve the yield during manufacturing without complicating the well-known manufacturing technology.
実用性、工業性の価値の十分大なるものである。It has sufficient practical and industrial value.
第1図a−g1第2図、第3図は従来の半導体装置の製
造方法を説明するための断面図、第4図a−gは本発明
の一実施例を説明するための工程断面図である。
21・・・・・・基板、22,25・・・・・・第一層
膜(二酸化硅素膜)、27・・・・・・第二層膜(多結
晶硅素膜)、28・・・・・・第三層膜(フオトレジス
ト膜)、32・・・・・・二酸化硅素膜、33・・・・
・・金属配線。Figures 1a-g1 Figures 2 and 3 are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device, and Figures 4a-g are process cross-sectional views for explaining an embodiment of the present invention. It is. 21... Substrate, 22, 25... First layer film (silicon dioxide film), 27... Second layer film (polycrystalline silicon film), 28... ...Third layer film (photoresist film), 32...Silicon dioxide film, 33...
・Metal wiring.
Claims (1)
体基板上に形成する工程と、前記第一層膜の前記膜厚の
異なるそれぞれの領域上に前記第一層膜に対する食刻マ
スクとなる第二層膜を選択的に形成する工程と、前記第
二層膜の端部を覆うように前記第一層膜の膜厚の厚い領
域上から前記第一層膜の膜厚の厚い領域上に形成された
前記第二層膜上にわたつて、前記第一層膜に対する食刻
マスクとなる第三層膜を形成する工程と、前記第二層膜
および前記第三層膜をマスクとして前記第一層膜を食刻
することにより、前記膜厚の薄い領域を除去して前記半
導体基板を露出する工程とを含むことを特徴とする半導
体装置の製造方法。 2 第一層膜が絶縁膜よりなり、第二層膜が導電体膜よ
りなることを特徴とする特許請求の範囲第1項に記載の
半導体装置の製造方法。 3 第三層膜がフォトレジスタ膜よりなることを特徴と
する特許請求の範囲第1項または第2項に記載の半導体
装置の製造方法。[Scope of Claims] 1. A step of forming a first layer film having regions having different thicknesses on a semiconductor substrate; a step of selectively forming a second layer film serving as an etching mask for the layer film; forming a third layer film serving as an etching mask for the first layer film over the second layer film formed on the thick region of the film; A method for manufacturing a semiconductor device, comprising the step of etching the first layer film using a third layer film as a mask to remove the thin film region and expose the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first layer film is an insulating film, and the second layer film is a conductive film. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the third layer film is a photoresist film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51058667A JPS5946108B2 (en) | 1976-05-20 | 1976-05-20 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51058667A JPS5946108B2 (en) | 1976-05-20 | 1976-05-20 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52141582A JPS52141582A (en) | 1977-11-25 |
JPS5946108B2 true JPS5946108B2 (en) | 1984-11-10 |
Family
ID=13090928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51058667A Expired JPS5946108B2 (en) | 1976-05-20 | 1976-05-20 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5946108B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61139601U (en) * | 1985-02-20 | 1986-08-29 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5278380A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Production of mos field effect semiconductor device |
-
1976
- 1976-05-20 JP JP51058667A patent/JPS5946108B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5278380A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Production of mos field effect semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61139601U (en) * | 1985-02-20 | 1986-08-29 |
Also Published As
Publication number | Publication date |
---|---|
JPS52141582A (en) | 1977-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5753546A (en) | Method for fabricating metal oxide field effect transistors | |
JPH10256511A (en) | Manufacture method of semiconductor device | |
JPH10303291A (en) | Semiconductor device and its manufacture | |
JPH06163578A (en) | Method for forming contact hole | |
US5696022A (en) | Method for forming field oxide isolation film | |
US5403770A (en) | Method for forming a field oxide film in a semiconductor device | |
JPH04275436A (en) | Soimos transistor | |
JPS5946108B2 (en) | Manufacturing method of semiconductor device | |
KR0138065B1 (en) | Method of fabricating contact in semconductor device | |
JPH08306797A (en) | Fabrication of semiconductor device | |
JP2950620B2 (en) | Semiconductor device | |
JP3132847B2 (en) | Method for manufacturing semiconductor device | |
JP3468920B2 (en) | Element isolation method for semiconductor device | |
JPS5823745B2 (en) | MOS | |
JPH10261722A (en) | Manufacture of semiconductor device | |
KR960009978B1 (en) | Forming method of field oxide film for semiconductor device | |
KR0167260B1 (en) | Manufacture of semiconductor device | |
JPS5943832B2 (en) | Manufacturing method of semiconductor device | |
JPS5994437A (en) | Semiconductor device | |
JPH05175345A (en) | Method for making contact hole in semiconductor substrate | |
JPS62242335A (en) | Formation of element isolating region of semiconductor integrated circuit | |
JPH05335333A (en) | Semiconductor device and manufacture thereof | |
JPS59139644A (en) | Manufacture of semiconductor device | |
JPH07249594A (en) | Manufacture of semiconductor device | |
JPS5829620B2 (en) | hand tai souchi no seizou houhou |