JPH08306797A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

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Publication number
JPH08306797A
JPH08306797A JP7137259A JP13725995A JPH08306797A JP H08306797 A JPH08306797 A JP H08306797A JP 7137259 A JP7137259 A JP 7137259A JP 13725995 A JP13725995 A JP 13725995A JP H08306797 A JPH08306797 A JP H08306797A
Authority
JP
Japan
Prior art keywords
film
semiconductor substrate
gate
region
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7137259A
Other languages
Japanese (ja)
Inventor
Yasushi Fukushima
康 福島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP7137259A priority Critical patent/JPH08306797A/en
Publication of JPH08306797A publication Critical patent/JPH08306797A/en
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To deposit a gate oxide having two kinds of thickness by forming an anti-oxidation layer covering only a semiconductor substrate in a first forming region and a gate electrode and forming a bird's beak between a second forming region and the gate electrode by wet oxidation. CONSTITUTION: Gate electrodes 12, 12' are formed in regions A, B. Insulating oxide layers 14, 14' are also formed around the gate electrodes 12, 12'. After depositing nitride 15 by about 100nm as an anti-oxidation layer, the nitride is removed selectively from the region B. Silicon oxide is then deposited on a semiconductor substrate 11 in the region B by wet oxidation. Consequently, the insulating oxide layer 14' becomes thick on the surface and side face of the gate electrode 12' but a bird's beak is formed between the gate electrode 12' and the semiconductor substrate 11 and thereby a gate oxide layer 16' has a thickness of 12-16nm. With such method, semiconductor elements having gate oxide layer of different thickness can be fabricated on a same semiconductor substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はゲート酸化膜を有する半
導体素子を含む半導体装置の製造方法に係り、特に同一
の半導体基板上に異なる膜厚のゲート酸化膜をもつ素子
を有する半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device including a semiconductor element having a gate oxide film, and more particularly to manufacturing a semiconductor device having an element having a gate oxide film having a different film thickness on the same semiconductor substrate. Regarding the method.

【0002】[0002]

【従来の技術】従来、この種の半導体の製造方法として
は、例えば特開平4−103162号公報あるいは特開
平3−55876号公報に開示されているようないくつ
かの方法がある。
2. Description of the Related Art Conventionally, as a method of manufacturing a semiconductor of this kind, there are some methods as disclosed in, for example, Japanese Patent Application Laid-Open No. 4-103162 or Japanese Patent Application Laid-Open No. 3-55876.

【0003】第1の方法は、特開平4−103162号
公報に従来技術(第4図)として記載されたものであ
り、図2に示すような工程で構成される。まず、図2
(a)に示すように、NまたはP型の半導体基板21の
主面を熱酸化させ、膜厚t1の絶縁膜(シリコン酸化
膜)22を全面(領域AおよびB)に形成する。次に、
図2(b)に示すように、絶縁膜22上にマスクとして
のレジスト23を選択的に領域Aにのみ形成した後、ウ
ェットエッチングを行い、レジスト23に覆われていな
い領域Bの絶縁膜22を除去する。次に、領域Aのレジ
スト23を除去した後、図2(c)に示すように、再び
熱酸化により膜厚t2の絶縁膜24を全面に形成する。
これにより、領域Aには膜厚(t1+t2)、領域Bに
は膜厚t2のゲート酸化膜が形成される。これ以降は通
常のMOS製造工程による。すなわち、図2(d)に示
すように、絶縁膜24上にポリシリコン(多結晶シリコ
ン)膜25を形成した後、このポリシリコン膜25をパ
ターニングしてゲート電極とし、このゲート電極と自己
整合的に半導体基板21表面近傍に不純物拡散領域を形
成してソース/ドレイン領域とする。
The first method is described in Japanese Patent Application Laid-Open No. 4-103162 as prior art (FIG. 4), and is constituted by the steps shown in FIG. First, FIG.
As shown in (a), the main surface of the N or P type semiconductor substrate 21 is thermally oxidized to form an insulating film (silicon oxide film) 22 having a film thickness t1 on the entire surface (regions A and B). next,
As shown in FIG. 2B, after the resist 23 as a mask is selectively formed on the insulating film 22 only in the region A, the insulating film 22 in the region B not covered with the resist 23 is wet-etched. To remove. Next, after removing the resist 23 in the region A, as shown in FIG. 2C, an insulating film 24 having a film thickness t2 is formed on the entire surface by thermal oxidation again.
As a result, a gate oxide film having a film thickness (t1 + t2) is formed in the region A and a film thickness t2 is formed in the region B. After this, the usual MOS manufacturing process is performed. That is, as shown in FIG. 2D, after forming a polysilicon (polycrystalline silicon) film 25 on the insulating film 24, the polysilicon film 25 is patterned to form a gate electrode, which is self-aligned with the gate electrode. Specifically, an impurity diffusion region is formed near the surface of the semiconductor substrate 21 to form a source / drain region.

【0004】第2の方法は、上記特開平4−10316
2号公報の第1図に示された方法である。すなわち、膜
厚t1のゲート酸化膜の上にゲート電極となるポリシリ
コン膜を形成し、マスクとしてのレジストを形成後、レ
ジストに覆われていないポリシリコン膜およびゲート酸
化膜を除去する。次に、熱酸化により膜厚t2のゲート
酸化膜を形成し、その上にポリシリコンを形成する。膜
厚t1のゲート酸化膜領域の上層のポリシリコンと酸化
膜とを除去する。これにより、膜厚t1とt2のゲート
酸化膜をもつMOSトランジスタが形成できる。
The second method is the above-mentioned Japanese Patent Laid-Open No. 10316/1992.
This is the method shown in FIG. That is, a polysilicon film to be a gate electrode is formed on the gate oxide film having a film thickness t1, a resist as a mask is formed, and then the polysilicon film and the gate oxide film not covered with the resist are removed. Next, a gate oxide film having a film thickness t2 is formed by thermal oxidation, and polysilicon is formed thereon. The polysilicon and oxide film in the upper layer of the gate oxide film region having the film thickness t1 are removed. As a result, a MOS transistor having a gate oxide film with a film thickness of t1 and t2 can be formed.

【0005】第3の方法は、特開平3−55876号公
報に示された方法である。すなわち、ゲート酸化を行う
前にトランジスタ形成領域の一部に窒化膜を形成してお
く。酸化により窒化膜と半導体基板との間に酸化膜のバ
ーズビークが入る。窒化膜の除去後、そのバーズビーク
状の酸化膜上にゲート酸化膜電極を形成すると、薄いゲ
ート酸化膜をもつMOSトランジスタが形成される。ま
た、窒化膜を形成しなかった領域にゲート酸化膜電極を
形成すると、厚いゲート酸化膜をもつMOSトランジス
タが形成される。
The third method is the method disclosed in Japanese Patent Laid-Open No. 3-55876. That is, a nitride film is formed in a part of the transistor formation region before gate oxidation is performed. Oxidation causes bird's beak of an oxide film between the nitride film and the semiconductor substrate. After removing the nitride film, a gate oxide film electrode is formed on the bird's beak oxide film, whereby a MOS transistor having a thin gate oxide film is formed. If the gate oxide film electrode is formed in the region where the nitride film is not formed, a MOS transistor having a thick gate oxide film is formed.

【0006】[0006]

【発明が解決しようとする課題】上記第1の方法では、
絶縁膜を選択的に除去する際に、この絶縁膜上にマスク
としてのレジストを直接形成している。しかし、レジス
トは一般にアルカリ金属や重金属等を多く含有している
ため、レジストが直接的に接する絶縁膜は、初期耐圧の
劣化という影響を与える。また、レジストの除去は、酸
素(O2 )プラズマを利用した灰化処理によって行わ
れ、絶縁膜がプラズマに直接曝されるので、この場合に
も初期耐圧の劣化という影響を受ける。したがって、長
期的にみた場合に、デバイスとしての信頼性が劣化する
という問題があった。
SUMMARY OF THE INVENTION In the first method,
When selectively removing the insulating film, a resist as a mask is directly formed on the insulating film. However, since the resist generally contains a large amount of alkali metals, heavy metals, etc., the insulating film with which the resist is in direct contact has the effect of deteriorating the initial breakdown voltage. Further, the removal of the resist is performed by an ashing process using oxygen (O 2 ) plasma, and the insulating film is directly exposed to the plasma, so that the initial breakdown voltage is also deteriorated in this case. Therefore, there is a problem that the reliability as a device deteriorates in the long term.

【0007】本発明はかかる問題点に鑑みてなされたも
ので、その目的は、ゲート酸化膜の初期耐圧劣化や長期
的信頼性の劣化等の不具合を伴うことなく、2種類の膜
厚のゲート酸化膜を有する半導体装置を製造できる半導
体装置の製造方法を提供することにある。
The present invention has been made in view of the above problems, and an object thereof is to obtain gates of two kinds of film thickness without causing problems such as deterioration of initial withstand voltage of the gate oxide film and deterioration of long-term reliability. It is an object of the present invention to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having an oxide film.

【0008】[0008]

【課題を解決するための手段】請求項1記載の半導体装
置の製造方法では、同一の半導体基板上に異なる膜厚の
ゲート酸化膜を有する半導体装置を製造する方法におい
て、半導体基板の全面に、ゲート酸化膜となる絶縁層を
形成する工程と、この絶縁層上の全面に、ゲート電極と
なる導電層を形成する工程と、この導電層をパターニン
グして、第1の形成領域および第2の形成領域にそれぞ
れゲート電極を形成する工程と、ドライ酸化によって、
第1および第2の形成領域のゲート電極ならびに半導体
基板を覆うように絶縁膜を形成する工程と、第1の形成
領域の半導体基板とゲート電極とを覆うように耐酸化性
膜を形成する工程と、全面に酸化絶縁膜を形成するため
のウェット酸化処理工程と、第1の形成領域の耐酸化性
膜を除去する工程とを含ませ、前記ウェット酸化処理工
程によって第2の形成領域のゲート電極と半導体基板と
の間にパーズビークを発生させ、この第2の形成領域の
ゲート酸化膜の膜厚を厚膜化させることで前記目的を達
成する。
A method of manufacturing a semiconductor device according to claim 1, wherein a semiconductor device having gate oxide films of different film thicknesses on the same semiconductor substrate is manufactured, A step of forming an insulating layer to be a gate oxide film, a step of forming a conductive layer to be a gate electrode over the entire surface of this insulating layer, and patterning this conductive layer to form a first formation region and a second formation region. By the step of forming the gate electrode in each formation region and the dry oxidation,
A step of forming an insulating film so as to cover the gate electrodes and the semiconductor substrate in the first and second formation regions, and a step of forming an oxidation resistant film so as to cover the semiconductor substrate and the gate electrode in the first formation region A wet oxidation treatment step for forming an oxide insulating film on the entire surface, and a step for removing the oxidation resistant film in the first formation region, the wet oxidation treatment step including the gate in the second formation region. The above-described object is achieved by generating a pars beak between the electrode and the semiconductor substrate and increasing the film thickness of the gate oxide film in the second formation region.

【0009】請求項2記載の半導体装置の製造方法で
は、前記耐酸化性膜を窒化膜で構成することで前記目的
を達成する。
In the method of manufacturing a semiconductor device according to the second aspect, the object is achieved by forming the oxidation resistant film with a nitride film.

【0010】[0010]

【作用】本発明に係る半導体装置の製造方法では、半導
体基板上に形成した絶縁膜上の第1および第2の形成領
域にそれぞれゲート電極を形成し、これらをすべて覆う
ように絶縁膜を形成すると共に、第1の形成領域の半導
体基板およびゲート電極のみを覆うように耐酸化性膜
(窒化膜)を形成し、さらにウェット酸化処理を行って
第2の形成領域のゲート電極と半導体基板との間にパー
ズビークを生じさせることにより、第2の形成領域のゲ
ート酸化膜の膜厚を厚膜化させることができる。一方、
第1の形成領域のゲート酸化膜は、窒化膜の存在により
元の膜厚が維持される。
In the method of manufacturing the semiconductor device according to the present invention, the gate electrode is formed in each of the first and second formation regions on the insulating film formed on the semiconductor substrate, and the insulating film is formed so as to cover all of them. In addition, an oxidation resistant film (nitride film) is formed so as to cover only the semiconductor substrate and the gate electrode in the first formation region, and wet oxidation treatment is further performed to form the gate electrode and the semiconductor substrate in the second formation region. By generating a purse beak between the two, the thickness of the gate oxide film in the second formation region can be increased. on the other hand,
The original film thickness of the gate oxide film in the first formation region is maintained due to the presence of the nitride film.

【0011】[0011]

【実施例】以下、本発明の好適な実施例を図1を参照し
て詳細に説明する。図1は、本発明の一実施例に係る半
導体装置の製造方法を表すものである。まず、図1
(a)に示すように、熱酸化処理によりNまたはP型の
半導体基板(シリコン基板)11上の全面(領域Aおよ
びB)に、膜厚が11nmのシリコン酸化膜を形成した
のち、その上にゲート電極となるポリシリコン膜をCV
D等によって膜厚350nm程度形成し、このポリシリ
コン膜にリン等の不純物をドープする。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to FIG. FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention. First, FIG.
As shown in (a), a silicon oxide film having a film thickness of 11 nm is formed on the entire surface (regions A and B) of an N or P type semiconductor substrate (silicon substrate) 11 by thermal oxidation, CV with the polysilicon film that becomes the gate electrode
A film thickness of about 350 nm is formed by D or the like, and the polysilicon film is doped with impurities such as phosphorus.

【0012】そして、ポリシリコン膜を写真製版によっ
てパターニングし、領域Aと領域Bにそれぞれゲート電
極12,12′を形成する。その後、ドライ酸化処理を
行い、半導体基板11上にゲート酸化膜厚と同じ膜厚1
1nmのシリコン酸化膜13,13′(絶縁酸化膜)を
形成する。このとき、ゲート電極12,12′の周り
(上面および側面)にもそれぞれ絶縁酸化膜14,14
が形成される。
Then, the polysilicon film is patterned by photolithography to form gate electrodes 12 and 12 'in regions A and B, respectively. After that, a dry oxidation process is performed to form a film having the same thickness as the gate oxide film 1 on the semiconductor substrate 11.
1 nm silicon oxide films 13 and 13 '(insulating oxide film) are formed. At this time, the insulating oxide films 14 and 14 are also formed around the gate electrodes 12 and 12 '(top and side surfaces), respectively.
Is formed.

【0013】次に、図1(b)に示すように、全面に、
耐酸化性膜としての窒化膜(例えばSi3 4)15を
100nm程度堆積した後、選択的に領域Bの窒化膜の
みを除去する。
Next, as shown in FIG. 1 (b),
After depositing a nitride film (for example, Si 3 N 4 ) 15 as an oxidation resistant film to a thickness of about 100 nm, only the nitride film in the region B is selectively removed.

【0014】次に、ウェット酸化処理により、領域Bの
半導体基板11上にさらに30nmのシリコン酸化膜を
形成する。このとき、領域Bでは、図1(c)に示すよ
うに、ウェット酸化処理によって、ゲート電極12′の
上および側面の絶縁酸化膜14′が厚膜化するが、ゲー
ト電極12′と半導体基板11との間にはバーズビーク
が生じるため、結局、半導体基板11とゲート電極1
2′とによって挟まれたゲート酸化膜16′の膜厚は1
2〜16nm程度となる。一方、領域Aの絶縁酸化膜1
3とゲート電極12とは耐酸化性膜である窒化膜15に
よって覆われているので、領域Aの半導体基板11とゲ
ート電極12とは酸化されず、窒化膜15上に酸化膜は
形成されない。もちろん、ゲート酸化膜16の膜厚は、
最初の工程で形成された11nmのままである。
Next, a 30 nm silicon oxide film is further formed on the semiconductor substrate 11 in the region B by wet oxidation. At this time, in the region B, as shown in FIG. 1C, the insulating oxide film 14 ′ on and above the gate electrode 12 ′ is thickened by the wet oxidation process, but the gate electrode 12 ′ and the semiconductor substrate are thickened. Since bird's beaks are generated between the semiconductor substrate 11 and the gate electrode 1,
The film thickness of the gate oxide film 16 'sandwiched by 2'is 1
It becomes about 2 to 16 nm. On the other hand, the insulating oxide film 1 in the region A
Since 3 and the gate electrode 12 are covered with the nitride film 15 which is an oxidation resistant film, the semiconductor substrate 11 and the gate electrode 12 in the region A are not oxidized and the oxide film is not formed on the nitride film 15. Of course, the thickness of the gate oxide film 16 is
It remains 11 nm formed in the first step.

【0015】次に、領域Aにおける窒化膜15を除去す
ることによって図1(c)に示す状態となる。それ以降
は、通常のMOSトランジスタの形成工程を行う。すな
わち、ゲート電極12,12′に接する半導体基板11
の表面近傍の所定範囲に、これらのゲート電極と自己整
合的に不純物拡散領域をドープしてソース/ドレイン領
域を形成し、さらに層間絶縁膜を形成後、コンタクト形
成、金属配線層の形成およびそのパターニング等の工程
を経てMOSトランジスタが完成する。なお、領域Bの
厚いゲート酸化膜をもつMOSトランジスタのゲート長
(すなわちソース/ドレイン間の距離)は0.8μm以
下であることが好適である。
Next, by removing the nitride film 15 in the region A, the state shown in FIG. 1C is obtained. After that, a normal MOS transistor forming process is performed. That is, the semiconductor substrate 11 in contact with the gate electrodes 12 and 12 '
The impurity diffusion region is doped in a predetermined range near the surface of the gate electrode in a self-aligning manner to form a source / drain region, an interlayer insulating film is further formed, and then a contact is formed, a metal wiring layer is formed, and A MOS transistor is completed through steps such as patterning. The gate length (that is, the distance between the source and the drain) of the MOS transistor having the thick gate oxide film in the region B is preferably 0.8 μm or less.

【0016】このように、本実施例の製造方法では、ゲ
ート酸化膜となるシリコン酸化膜に直接レジストを塗布
することがないので、レジスト中に含まれるアルカリ金
属や重金属等の影響を受けることなく、異なるゲート酸
化膜をもつMOSトランジスタを同一半導体基板上に形
成することが可能となる。
As described above, according to the manufacturing method of this embodiment, since the resist is not directly applied to the silicon oxide film to be the gate oxide film, it is not affected by the alkali metal or heavy metal contained in the resist. It becomes possible to form MOS transistors having different gate oxide films on the same semiconductor substrate.

【0017】[0017]

【発明の効果】以上説明したように、本発明に係る半導
体装置の製造方法によれば、半導体基板上に形成した絶
縁膜上の第1および第2の形成領域にそれぞれゲート電
極を形成し、これらをすべて覆うように絶縁膜を形成す
ると共に、第1の形成領域の半導体基板およびゲート電
極のみを覆うように耐酸化性膜(窒化膜)を形成し、さ
らにウェット酸化処理を行って第2の形成領域のゲート
電極と半導体基板との間にパーズビークを生じさせるよ
うにしたので、第2の形成領域のゲート酸化膜の膜厚の
みを厚膜化させることができる。これらの工程では、ゲ
ート酸化膜にレジストが直接接触することがないので、
レジスト中のアルカリ金属や重金属等の影響を受けるこ
とがなく、また、ゲート酸化膜がプラズマに直接曝され
ることもない。したがって、初期耐圧の劣化および長期
的にみたデバイスの信頼性の劣化という問題を排除しつ
つ、異なる膜厚のゲート酸化膜をもつ半導体素子を同一
半導体基板上に形成することが可能となる。
As described above, according to the method of manufacturing the semiconductor device of the present invention, the gate electrode is formed in each of the first and second formation regions on the insulating film formed on the semiconductor substrate, An insulating film is formed so as to cover all of them, an oxidation resistant film (nitride film) is formed so as to cover only the semiconductor substrate and the gate electrode in the first formation region, and wet oxidation treatment is further performed to form a second film. Since the parse beak is generated between the gate electrode in the formation region of the second region and the semiconductor substrate, only the film thickness of the gate oxide film in the second formation region can be increased. In these steps, the resist does not come into direct contact with the gate oxide film,
It is not affected by the alkali metal or heavy metal in the resist, and the gate oxide film is not directly exposed to plasma. Therefore, it becomes possible to form semiconductor elements having gate oxide films of different thicknesses on the same semiconductor substrate while eliminating the problems of deterioration of initial breakdown voltage and deterioration of device reliability in the long term.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る半導体装置の製造方法
を表す工程図である。
FIG. 1 is a process chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を表す工程図であ
る。
FIG. 2 is a process chart showing a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

11 半導体基板 12,12′ ゲート電極 13,13′ 絶縁酸化膜 14,14′ 絶縁酸化膜 15 窒化膜(耐酸化性膜) 16,16′ ゲート酸化膜 11 semiconductor substrate 12, 12 'gate electrode 13, 13' insulating oxide film 14, 14 'insulating oxide film 15 nitride film (oxidation resistant film) 16, 16' gate oxide film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 同一の半導体基板上に異なる膜厚のゲー
ト酸化膜を有する半導体装置を製造する方法であって、 半導体基板の全面に、ゲート酸化膜となる絶縁層を形成
する工程と、 この絶縁層上の全面に、ゲート電極となる導電層を形成
する工程と、 この導電層をパターニングして、第1の形成領域および
第2の形成領域にそれぞれゲート電極を形成する工程
と、 ドライ酸化によって、第1および第2の形成領域のゲー
ト電極ならびに半導体基板を覆うように絶縁膜を形成す
る工程と、 第1の形成領域の半導体基板とゲート電極とを覆うよう
に耐酸化性膜を形成する工程と、 全面に酸化絶縁膜を形成するためのウェット酸化処理工
程と、 第1の形成領域の耐酸化性膜を除去する工程とを含み、 前記ウェット酸化処理工程によって第2の形成領域のゲ
ート電極と半導体基板との間にパーズビークを発生させ
ることで、この第2の形成領域のゲート酸化膜の膜厚を
厚膜化したことを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device having gate oxide films of different thicknesses on the same semiconductor substrate, the method comprising: forming an insulating layer to be a gate oxide film on the entire surface of the semiconductor substrate; A step of forming a conductive layer to be a gate electrode on the entire surface of the insulating layer; a step of patterning this conductive layer to form a gate electrode in each of the first formation region and the second formation region; and dry oxidation. A step of forming an insulating film so as to cover the gate electrodes and the semiconductor substrate in the first and second formation regions, and forming an oxidation resistant film so as to cover the semiconductor substrate and the gate electrode in the first formation region And a wet oxidation treatment step for forming an oxide insulating film on the entire surface, and a step of removing the oxidation resistant film in the first formation region. By generating a Pazubiku between the gate electrode and the semiconductor substrate region, a method of manufacturing a semiconductor device, wherein a thickness of the gate oxide film of the second forming region is thickened.
【請求項2】 前記耐酸化性膜は窒化膜であることを特
徴とする請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxidation resistant film is a nitride film.
JP7137259A 1995-05-11 1995-05-11 Fabrication of semiconductor device Pending JPH08306797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7137259A JPH08306797A (en) 1995-05-11 1995-05-11 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7137259A JPH08306797A (en) 1995-05-11 1995-05-11 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH08306797A true JPH08306797A (en) 1996-11-22

Family

ID=15194493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7137259A Pending JPH08306797A (en) 1995-05-11 1995-05-11 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH08306797A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177332B1 (en) * 1998-09-14 2001-01-23 United Microelectronics Corp. Method of manufacturing shallow trench isolation
US6673705B2 (en) 2000-06-30 2004-01-06 Kabushiki Kaisha Toshiba Method of manufacturing a MISFET having post oxide films having at least two kinds of thickness
CN102299064A (en) * 2010-06-28 2011-12-28 中芯国际集成电路制造(上海)有限公司 Method for oxidizing grid structure
WO2012035684A1 (en) * 2010-09-14 2012-03-22 パナソニック株式会社 Semiconductor device and production method for same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177332B1 (en) * 1998-09-14 2001-01-23 United Microelectronics Corp. Method of manufacturing shallow trench isolation
US6673705B2 (en) 2000-06-30 2004-01-06 Kabushiki Kaisha Toshiba Method of manufacturing a MISFET having post oxide films having at least two kinds of thickness
KR100423248B1 (en) * 2000-06-30 2004-03-18 가부시끼가이샤 도시바 Method for manufacturing the semiconductor device
CN102299064A (en) * 2010-06-28 2011-12-28 中芯国际集成电路制造(上海)有限公司 Method for oxidizing grid structure
WO2012035684A1 (en) * 2010-09-14 2012-03-22 パナソニック株式会社 Semiconductor device and production method for same
JP2012064648A (en) * 2010-09-14 2012-03-29 Panasonic Corp Semiconductor device and method of manufacturing the same
US8796779B2 (en) 2010-09-14 2014-08-05 Panasonic Corporation Semiconductor device

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