JPS62242335A - Formation of element isolating region of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it feasible to form an element isolating region with less pattern conversion difference and stress concentration on transient regions by a method wherein both sides of a silicon oxide film is tapered and covered with thin silicon nitride film to be selectively oxidized. CONSTITUTION:A silicon nitride film 3 and a silicon oxide film 2 are successively etched at rslatively small selection ratio of etching speed between the silicon oxide film 2, the silicon nitride film 3 and a photoresist 4 to expose the surface of a single crystal substrate 1. Thus, the sides of silicon nitride film 3 and the silicon oxide film 2 are formed into a taper 5. Successively a channel cut regions 6 are formed. Next, after removing a photoresist 4, the second silicon nitride film 7 is formed to cover the surface of silicon single crystal substrate 1, the taper region 5 and the silicon nitride film 3. Finally, the second silicon nitride film 7 is anisotropically etched to be left only on a part of the taper part 5 mainly on the silicon oxide film 2 removing all of the other parts.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming an element isolation region in a semiconductor integrated circuit, and in particular, to a semiconductor integrated circuit in which pattern conversion differences are small and stress concentration in transition regions is small. The present invention relates to a method for forming an element isolation region.

[Conventional technology]

As a conventional method for forming an element isolation region of a semiconductor integrated circuit, there is a method shown in FIG. 2, for example. This formation method is
A second silicon nitride film 21 is formed on the side wall of the first silicon nitride film 21, which is an oxidation-resistant film.
For example, Japanese Journal of Applied Physics Vol. 20, Sublument 20-1, P P5
5-61. Published in 1981.

That is, as shown in FIG. 2, the first silicon nitride film 21 located on the silicon oxide film 2-1 selectively left on the silicon single crystal substrate 1 of a predetermined conductivity type, and the first silicon nitride film 21 on the sidewall thereof. 2
By performing selective oxidation using the silicon nitride film 22 as a mask, an oxide film 23 for an element isolation region is formed.

Figure 3 shows a silicon oxide film 2 formed on a silicon single crystal substrate 1 using a formation method widely known as the LOCO3 method.
is located thereon, and an oxide film 33 for an element isolation region is formed using the silicon nitride film 31 thereon as a mask.

According to the formation method shown in FIG. 2, since the sidewall of the first silicon nitride film 21 is completely covered with the second silicon nitride film 22, the amount of bird's beak corresponding to the pattern conversion difference formed during selective oxidation is reduced. becomes extremely small. Therefore, the distance p2 between the transition region between the oxidized region and the non-oxidized region can be shortened (as a result, the inclination angle θ2 becomes large).

In contrast, 1 in Figure 3. According to the OCOS method, part of the oxide film 33 is formed by digging into both ends of the silicon nitride film 31, so the distance 13 of the transition region is not shortened (
As a result, the inclination angle θ3 is small).

[Problems solved by the invention]

However, according to the method of forming the element isolation region of the semiconductor integrated circuit shown in FIG. 2, since the distance 12 of the transition region mentioned above is short (because the inclination angle θ2 is large), stress concentration in this region becomes significant. If a thick oxide film is formed, dislocations may occur due to external stress, which may increase leakage current.

[Means to solve the problem]

The present invention has been made in view of the above-mentioned problems, and aims to form an element isolation region with less difference in pattern conversion and less stress concentration on the transient region. Formation of an element isolation region for a semiconductor integrated circuit in which a silicon oxide layer is tapered at both ends where a silicon nitride film serving as a mask for selective oxidation is located, and this tapered surface is covered with a thin silicon nitride film to perform selective oxidation. The present invention provides a method.

Hereinafter, a method for forming an element isolation region of a semiconductor integrated circuit according to the present invention will be explained in detail.

〔Example〕

FIG. 1 fa) to FIG. 1 fe) show an embodiment of the present invention.

First, as shown in FIG. 1fa), a silicon oxide film 2 and a silicon nitride film 3 are formed on the surface of a silicon single crystal substrate 1, and subsequently a pattern of a photoresist 4 is formed.

The silicon oxide film 2 is 50 to 1,000 thick, and the silicon nitride film 3 is 100 to 2,000 thick.

Next, as shown in FIG. 2 (bl), the silicon nitride film is etched under the condition that the etching rate selectivity of the silicon oxide film 2 and the silicon nitride film 3 and the photoresist 4 is relatively small, for example, 0.5 to 3. 3 and the silicon oxide film 2 are sequentially etched to expose the surface of the silicon single crystal substrate 1. As mentioned above, the etching is performed under conditions where the selectivity is relatively low, that is, the etching rate of the photoresist is relatively high. As a result, a taper 5 is formed on the side surfaces of the silicon nitride film 3 and the silicon oxide film 2.Subsequently, channel cut ions are implanted by a known method to form a channel cut region 6.

Next, as shown in FIG. 1 (C1), after removing the photoresist 4, the second silicon nitride film 7 is deposited on the silicon single crystal substrate
, the tapered region 5 and the surface of the silicon nitride film 3. The thickness of this silicon nitride film 7 is set to be thinner than the silicon nitride film 3.

Next, as shown in FIG. 1 1dl, the second silicon nitride film 7
Anisotropic etching is applied to the silicon nitride film 7 to leave only a portion of the tapered region 5, mainly the silicon oxide film 2, and remove the other portions. In this way, in order to leave the silicon nitride film 7 only in a part of the tapered region,
The surface portion t of the silicon nitride film 3 having a thickness of 50 to 500 nm is etched away. This is achieved by performing overetching.

Finally, as shown in FIG. 1 (el), selective oxidation is performed using the silicon nitride films 3 and 7 as masks to form a silicon oxide film 9 for element isolation.

Note that after this, a gate electrode, a source and a drain, an electrode pattern, etc. are formed to form a MOS transistor.

The silicon oxide film 9 for element isolation formed through the following two steps is as shown in FIG.
Relationship with TeN, <j! , <n3, with a suitable value of the transition region distance l, so that (approximately the oblique angle θ, is θ
3<θ1 x θ2, stress concentration can be alleviated.

〔Effect of the invention〕

According to the method for forming an element isolation region of a semiconductor element according to the present invention, both ends of the silicon oxide layer where the silicon nitride film serving as a mask for selective oxidation is located are tapered, and this tapered surface is thinned. Since selective oxidation is performed by covering with a silicon nitride film, it is possible to form an element isolation region with less difference in pattern conversion and less stress concentration in the transition region.

[Brief explanation of drawings]

FIG. 1 ta+ to FIG. 1 te+ are sectional views showing one embodiment of the present invention. FIGS. 2 and 3 are cross-sectional views showing a conventional method of forming an element isolation region. Explanation of symbols

Claims (1)

[Scope of Claim] A method for forming an element isolation region of a semiconductor integrated circuit in which selective oxidation is performed using a nitride film on an oxide film on a surface of a semiconductor substrate as a mask, comprising: forming a tapered surface on a side surface of a laminated structure of the oxide film and the nitride film; forming another nitride film on the stacked structure surface; and removing the other nitride film leaving it on the side surface of the oxide film, A method for forming an element isolation region of a semiconductor integrated circuit, characterized in that the selective oxidation is performed using the other nitride film as a mask.