JPS6312380B2 - - Google Patents
Info
- Publication number
- JPS6312380B2 JPS6312380B2 JP57101101A JP10110182A JPS6312380B2 JP S6312380 B2 JPS6312380 B2 JP S6312380B2 JP 57101101 A JP57101101 A JP 57101101A JP 10110182 A JP10110182 A JP 10110182A JP S6312380 B2 JPS6312380 B2 JP S6312380B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- impurity
- nitride film
- region
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 35
- 239000010703 silicon Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 241000293849 Cordylanthus Species 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Description
【発明の詳細な説明】
この発明は、素子間分離絶縁領域を形成する工
程を有する半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, which includes a step of forming an isolation region between elements.
従来、この種の半導体装置の製造方法として
は、酸化シリコン膜を下敷膜とした薄い窒化シリ
コン膜をマスクとして用いてシリコン基板の高温
度・長時間の熱酸化を行ない、素子間分離絶縁領
域を形成する方法が知られている。すなわち、こ
の種の酸化膜形成方法は、シリコンを材料として
選択酸化法を応用するMOS型半導体装置のフイ
ールド領域の厚い酸化膜の形成やバイポーラ型半
導体装置の分離用の酸化膜の形成など、あらゆる
半導体装置の製造方法に一般的に用いられてい
る。しかしながら、この方法では、バーズビーク
と呼ばれる形状の酸化膜の尾状の領域が所要の酸
化膜の上部の両側から延びて形成されてしまう。
従つて、酸化膜本体の最小線幅が１ミクロンなら
両側にそれぞれ0.5ミクロンで計１ミクロンのバ
ーズビークが発生し、線幅２ミクロン以下の加工
が困難であつた。 Conventionally, the method for manufacturing this type of semiconductor device is to thermally oxidize the silicon substrate at high temperature and for a long time using a thin silicon nitride film with a silicon oxide film as an underlying film as a mask, thereby forming an isolation region between elements. Methods of forming are known. In other words, this type of oxide film formation method can be used for all kinds of applications, such as the formation of thick oxide films in the field region of MOS semiconductor devices using silicon as a material and the formation of isolation oxide films in bipolar semiconductor devices. It is generally used in the manufacturing method of semiconductor devices. However, in this method, a tail-like region of the oxide film having a shape called a bird's beak is formed extending from both sides of the upper part of the desired oxide film.
Therefore, if the minimum line width of the oxide film body is 1 micron, a bird's beak of 0.5 micron on each side, totaling 1 micron, will occur, making it difficult to process lines with a line width of 2 microns or less.
この発明は、上記の点に鑑みてなされたもので
あり、厚さが厚く幅の狭い素子間分離絶縁領域を
形成することのできる半導体装置の製造方法を提
供することを目的としたものである。 The present invention has been made in view of the above points, and aims to provide a method for manufacturing a semiconductor device that can form a thick and narrow inter-element isolation insulating region. .
この発明に係る半導体装置の製造方法は、シリ
コン基板に幅の狭い溝を形成し、シリコン基板を
直接に窒化した窒化シリコン膜をマスクにして、
シリコン基板のこの溝に面した部分を熱酸化させ
ることによつて、素子間分離絶縁領域を形成する
ようにしたものである。 A method for manufacturing a semiconductor device according to the present invention includes forming a narrow groove in a silicon substrate, using a silicon nitride film obtained by directly nitriding the silicon substrate as a mask, and
By thermally oxidizing the portion of the silicon substrate facing this groove, an inter-element isolation insulating region is formed.
以下、実施例に基づいてこの発明を説明する。 The present invention will be explained below based on examples.
第１図ａ〜ｄはこの発明による半導体装置の製
造方法の一実施例の素子間分離絶縁領域の形成方
法の主要段階を示す断面図である。 FIGS. 1A to 1D are cross-sectional views showing the main steps of a method for forming an inter-element isolation region in an embodiment of the method for manufacturing a semiconductor device according to the present invention.
まず、第１図ａに示すように、シリコン基板１
の表面にフオトレジスト、金属などからなり所要
の開口部２ａを有するマスク２を形成する。次
に、第１図ｂに示すように、マスク２をマスクと
して、反応性イオン・エツチング（RIE）などの
方法によつて、シリコン基板１の開口部２ａ直下
の部分をエツチング除去して溝３を形成する。つ
づいて、第１図ｃに示すように、シリコン基板１
の溝３の底面下の部分にイオン注入法などによつ
てシリコン基板１の不純物と同型の不純物を導入
して不純物導入領域４を形成する。さらに、第１
図ｄに示すように、マスク２を除去した後、シリ
コン基板１の表面部を直接に窒化させて窒化シリ
コン膜５を形成する、このとき、窒化シリコン膜
５には溝３に対応する部分に開口部５ａが形成さ
れる。溝３の側面および底面にも窒化シリコン膜
が形成されるが、これらは、シリコン基板１の表
面の窒化シリコン膜５をマスクした後、熱リン酸
でエツチングして取り除く。つづいて、開口部５
ａを有する窒化シリコン膜５をマスクにしてシリ
コン基板１を熱酸化するとシリコン基板１の溝３
の底面および側面に接する部分が酸化され、酸化
シリコンが溝３を埋めて素子間分離絶縁領域６が
形成される。この場合、素子間分離絶縁領域６の
幅は開口部５ａの幅の1.4〜1.5倍になるが、窒化
シリコン膜５の下に下敷膜としての酸化シリコン
膜を用いバーズビークが生じた場合の約２倍より
は小さくなる。すなわち、厚さが厚く、幅が狭い
素子間分離絶縁領域６が形成される。また、窒化
シリコン膜５はシリコン基板１の表面部を直接に
窒化させたものであるから、シリコン基板１との
密着性がよく、また、熱酸化に際してシリコン基
板１に結晶欠陥が生じることがない。さらに、素
子間分離絶縁領域６の底面下には不純物導入領域
４の不純物が拡散して形成されたシリコン基板１
より不純物濃度の高い拡大不純物導入領域４ａが
存在しており、これが分離効果を高めるチヤンネ
ルストツパーになつている。 First, as shown in FIG. 1a, a silicon substrate 1
A mask 2 made of photoresist, metal, etc. and having a required opening 2a is formed on the surface of the mask. Next, as shown in FIG. 1b, using the mask 2 as a mask, the portion directly below the opening 2a of the silicon substrate 1 is etched away by a method such as reactive ion etching (RIE) to form the groove 3. form. Next, as shown in FIG. 1c, the silicon substrate 1
An impurity of the same type as the impurity of the silicon substrate 1 is introduced into a portion below the bottom surface of the groove 3 by ion implantation or the like to form an impurity-introduced region 4. Furthermore, the first
As shown in FIG. d, after removing the mask 2, the surface of the silicon substrate 1 is directly nitrided to form a silicon nitride film 5. At this time, the silicon nitride film 5 has a portion corresponding to the groove 3. An opening 5a is formed. A silicon nitride film is also formed on the side and bottom surfaces of the groove 3, but these are removed by etching with hot phosphoric acid after masking the silicon nitride film 5 on the surface of the silicon substrate 1. Next, opening 5
When the silicon substrate 1 is thermally oxidized using the silicon nitride film 5 having a
The portions in contact with the bottom and side surfaces of the substrate are oxidized, silicon oxide fills the trench 3, and an inter-element isolation insulating region 6 is formed. In this case, the width of the inter-element isolation insulating region 6 is 1.4 to 1.5 times the width of the opening 5a, but it is about 2 times the width when a bird's beak is created using a silicon oxide film as an underlayer film under the silicon nitride film 5. It will be smaller than double. That is, the inter-element isolation insulating region 6 having a large thickness and a narrow width is formed. Furthermore, since the silicon nitride film 5 is obtained by directly nitriding the surface portion of the silicon substrate 1, it has good adhesion to the silicon substrate 1, and crystal defects are not generated in the silicon substrate 1 during thermal oxidation. . Further, under the bottom surface of the element isolation insulating region 6, a silicon substrate 1 is formed by diffusing the impurities of the impurity introduction region 4.
There is an enlarged impurity introduced region 4a having a higher impurity concentration, and this serves as a channel stopper that enhances the separation effect.
第２図ａ〜ｅはこの発明による半導体装置の製
造方法の他の実施例の素子間分離絶縁領域の形成
方法の主要段階を示す断面図である。第２図にお
いて、第１図と同一符号は第１図にて示したもの
と同様のものを表わしている。第２図ａ，ｂの段
階は第１図ａ，ｂの段階と同様にして行う。第２
図ｃに示すようにシリコン基板１の溝３の底面下
の部分にイオン注入法などによつてシリコン基板
１の不純物と異なる型の不純物を導入して第１の
不純物導入領域７を形成する。次に、第２図ｄに
示すように、第２図ｃの場合と同様にして、シリ
コン基板１の不純物と同型の不純物を導入して第
２の不純物導入領域８を形成する。つづいて、第
２図ｅに示すように、第１図に示した実施例と同
様にして開口部５ａを有する窒化シリコン膜５を
マスクにしてシリコン基板１を熱酸化して同様の
素子間分離絶縁領域６を形成する。この場合、第
１の不純物導入領域７および第２の不純物導入領
域８の不純物が拡散してそれぞれ第１の拡大不純
物導入領域７ａおよび第２の拡大不純物導入領域
８ａが形成され、この間に拡散接合容量が形成さ
れる。この拡散接合容量は、素子間分離を強化す
ると共に、保護回路の一部として応用される。 FIGS. 2a to 2e are cross-sectional views showing the main steps of a method for forming an isolation region in another embodiment of the method for manufacturing a semiconductor device according to the present invention. In FIG. 2, the same reference numerals as in FIG. 1 represent the same components as shown in FIG. The steps a and b in FIG. 2 are performed in the same manner as the steps a and b in FIG. 1. Second
As shown in FIG. c, a first impurity-introduced region 7 is formed by introducing an impurity of a type different from that of the silicon substrate 1 into a portion below the bottom surface of the groove 3 of the silicon substrate 1 by ion implantation or the like. Next, as shown in FIG. 2d, in the same manner as in FIG. 2c, an impurity of the same type as the impurity in the silicon substrate 1 is introduced to form a second impurity-introduced region 8. Subsequently, as shown in FIG. 2e, the silicon substrate 1 is thermally oxidized using the silicon nitride film 5 having the opening 5a as a mask in the same manner as in the embodiment shown in FIG. An insulating region 6 is formed. In this case, the impurities in the first impurity introduced region 7 and the second impurity introduced region 8 are diffused to form a first enlarged impurity introduced region 7a and a second enlarged impurity introduced region 8a, and a diffusion bond is formed between them. A capacitance is formed. This diffused junction capacitance strengthens isolation between elements and is applied as part of a protection circuit.
以上詳述したように、この発明による半導体装
置の製造方法においては、シリコン基板の一方の
主面から内部に掘り込んだ溝の側面および底面に
接するシリコン基板の部分を、シリコン基板を直
接に窒化させて形成した窒化シリコン膜をマスク
にして、熱酸化して溝を酸化シリコンで埋めて素
子間分離絶縁領域を形成するので、シリコン基板
に結晶欠陥を生じることなく、厚さが厚く幅が狭
い素子間分離絶縁領域を形成することができる。 As described in detail above, in the method for manufacturing a semiconductor device according to the present invention, the silicon substrate is directly nitrided in the portion of the silicon substrate that is in contact with the side and bottom surfaces of the trench dug inward from one main surface of the silicon substrate. Using the silicon nitride film formed in this process as a mask, thermal oxidation is performed to fill the trench with silicon oxide to form an isolation region between elements, which eliminates crystal defects in the silicon substrate, resulting in a thick and narrow silicon substrate. An element isolation insulating region can be formed.
第１図ａ〜ｄはこの発明の一実施例のこの発明
に関連のある主要段階を示す断面図、第２図ａ〜
ｅはこの発明の他の実施例のこの発明に関連のあ
る主要段階を示す断面図である。
図において、１はシリコン基板、３は溝、４は
不純物導入領域、４ａは拡大不純物導入領域、５
は窒化シリコン膜、６は素子間分離絶縁領域、７
は第１の不純物導入領域、７ａは第１の拡大不純
物導入領域、８は第２の不純物導入領域、８ａは
第２の拡大不純物導入領域である。なお、図中同
一符号はそれぞれ同一または相当部分を示す。
Figures 1 a to d are cross-sectional views showing the main steps related to the present invention in one embodiment of the present invention; Figures 2 a to d
FIG. 5e is a cross-sectional view of another embodiment of the invention showing the main steps relevant to the invention; In the figure, 1 is a silicon substrate, 3 is a trench, 4 is an impurity doped region, 4a is an enlarged impurity doped region, and 5 is a silicon substrate.
6 is a silicon nitride film, 6 is an isolation insulating region between elements, and 7 is a silicon nitride film.
7a is a first expanded impurity implanted region, 8 is a second impurity implanted region, and 8a is a second expanded impurity implanted region. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
んだ溝を形成する工程、上記シリコン基板の表面
部を直接に窒化させて窒化シリコン膜を形成する
工程、上記溝の側面および底面に形成された窒化
シリコン膜を除去する工程、および残存する上記
窒化シリコン膜をマスクにして上記シリコン基板
を熱酸化して酸化シリコンによつて上記溝を埋め
て素子間分離絶縁領域を形成する工程を備えた半
導体装置の製造方法。 ２ 上記シリコン基板の溝の底面に接する部分に
該シリコン基板の不純物と同一型の不純物を導入
し、上記素子間分離絶縁領域の下に上記シリコン
基板より不純物濃度の高い不純物導入領域を形成
するようにしたことを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。 ３ 上記シリコン基板の溝の底面に接する部分に
ｎ型およびｐ型の不純物を導入し、上記素子間分
離絶縁領域の下に拡散接合容量を形成するように
したことを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。[Claims] 1. A step of forming a groove dug inward from one main surface of a silicon substrate, a step of directly nitriding the surface portion of the silicon substrate to form a silicon nitride film, and a step of forming a silicon nitride film by directly nitriding the surface portion of the silicon substrate. A step of removing the silicon nitride film formed on the side and bottom surfaces, and thermally oxidizing the silicon substrate using the remaining silicon nitride film as a mask to fill the trench with silicon oxide to form an isolation insulating region between elements. A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor device. 2. Introducing an impurity of the same type as the impurity of the silicon substrate into a portion of the silicon substrate in contact with the bottom surface of the groove, and forming an impurity-introduced region with a higher impurity concentration than the silicon substrate under the element isolation insulating region. A method of manufacturing a semiconductor device according to claim 1, characterized in that: 3. Claims characterized in that n-type and p-type impurities are introduced into a portion of the silicon substrate in contact with the bottom surface of the groove to form a diffusion junction capacitance under the element isolation insulating region. 2. A method for manufacturing a semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110182A JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110182A JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58216437A JPS58216437A (en) | 1983-12-16 |
| JPS6312380B2 true JPS6312380B2 (en) | 1988-03-18 |
Family
ID=14291692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10110182A Granted JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58216437A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4637553B2 (en) * | 2004-11-22 | 2011-02-23 | パナソニック株式会社 | Schottky barrier diode and integrated circuit using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5429573A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Fine machining method of semiconductor |
-
1982
- 1982-06-10 JP JP10110182A patent/JPS58216437A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5429573A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Fine machining method of semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58216437A (en) | 1983-12-16 |
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