JPS58216437A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS58216437A JPS58216437A JP10110182A JP10110182A JPS58216437A JP S58216437 A JPS58216437 A JP S58216437A JP 10110182 A JP10110182 A JP 10110182A JP 10110182 A JP10110182 A JP 10110182A JP S58216437 A JPS58216437 A JP S58216437A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- nitride film
- groove
- impurity
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、素子間分離絶縁領域を形成する工程を有す
る半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, which includes a step of forming an isolation region between elements.
従来、この種の半導体装置の製造方法としては、酸化シ
リコン膜を下敷膜とした薄い窒化シリコン膜をマスクと
して用いてシリコン基板の高温度・長時間の熱酸化を行
ない、素子間分離絶縁領域を形成する方法が知られてい
る。すなわち、この種の酸化膜形成方法は、シリコンを
材料として選択酸化法を応用するＭＯ８型半導体装置の
フィールド領域の厚い酸化膜の形成やバイポーラ型半導
体装置の分離用の酸化膜の形成など、あらゆる半導体装
置の製造方法に一般的に用いられている。しかしながら
、この方法では、バーズビークと呼ばれる形状の酸化膜
の星状の領域が所要の酸化膜の上部の両側から延びて形
成されてしまう。従って、酸化膜本体の最小線幅が１ミ
クロンなら両側にそれぞれ０．５ミクロンで計１ミクロ
ンのバーズビークが発生し、線幅２ミクロン以下の加工
が困難であった。Conventionally, the method for manufacturing this type of semiconductor device is to thermally oxidize the silicon substrate at high temperature and for a long time using a thin silicon nitride film with a silicon oxide film as an underlying film as a mask, thereby forming an isolation region between elements. Methods of forming are known. In other words, this type of oxide film formation method can be used for all kinds of applications, such as the formation of thick oxide films in the field region of MO8 type semiconductor devices using silicon as the material and the formation of isolation oxide films in bipolar type semiconductor devices. It is generally used in the manufacturing method of semiconductor devices. However, in this method, a star-shaped region of the oxide film with a shape called a bird's beak is formed extending from both sides of the upper part of the required oxide film. Therefore, if the minimum line width of the oxide film body is 1 micron, a bird's beak of 0.5 micron on each side and a total of 1 micron will occur, making it difficult to process lines with a line width of 2 microns or less.
この発明、上記の点に鑑みてなされたものであり、シリ
コン基板に幅の狭い溝を形成し、シリコン基板を直接に
窒化した窒化シリコン膜をマスクにして、シリコン基板
のこの溝に面した部分を熱酸化させることによって、素
子間分離絶縁領域を形成する半導体装置の製造方法を提
供することを目的としたものである。This invention has been made in view of the above points, and involves forming a narrow groove in a silicon substrate, and using a silicon nitride film obtained by directly nitriding the silicon substrate as a mask, the portion of the silicon substrate facing the groove. The object of the present invention is to provide a method for manufacturing a semiconductor device in which an element isolation insulating region is formed by thermally oxidizing the semiconductor device.
以下、実施例に基づいてこの発明を説明する。The present invention will be explained below based on examples.
第１図（ａ）〜（ｄ）はこの発明による半導体装置の製
造方法の一実施例の素子間分離絶縁領域の形成力法の主
要段階な示す断面図である。FIGS. 1(a) to 1(d) are cross-sectional views showing the main steps of forming an interelement isolation region in one embodiment of the method for manufacturing a semiconductor device according to the present invention.
まず、第１図（ａ）に示すように、シリコン基板（＋）
の表面にフォトレジスト、金属などがらなり所要の開口
部（２ａ）を有す゛るマスク（２）を形成する。次に、
第１図（ｂ）に示すように、マスク（２）をマスクとし
て、反応性イオン・エツチング（Ｒ１幻などの方法によ
って、シリコン基板（１）の開口部（２ａ）直下の部分
をエツチング除去して溝（３）を形成する。つづいて、
第１図（０）に示すように、シリコン基板（１）の溝（
３）の底面下の部分にイオン注入法などによってシリコ
ン基板（３）の不純物の同型の不純物を導入して不純物
導入領域（４）妃形成する。さらに、第１図（ｄ）に示
すように、マスク（２）を除去した後、シリコン基板（
１）の表面部を直接に窒化させて窒化シリコン膜（５１
を形成する、このとき、窒化シリコン膜（５）には溝（
３）に対応ｒる部分に開口部（５ａ）が形成される。溝
（３）の側面および底面にも窒化シリコン膜が形成され
るが、これらは、シリコン基板（１）の表面の貿化シリ
コン膜（５）をマスクした後、熱リン酸てエツチングし
て取り除く。つづいて、開口部（５ａ）を有する窒化シ
リコン膜（６）をマスクにして入
シリコン基板１１＋を熱酸化するとシリコン基板（１）
の＊ ｉｌｌの底面および側面に接する部分が酸化され
、酸化シリコンが？ｌｌＮ＋３１を埋めて素子間分離絶
縁領域（６）が形成きれる。この場合、素子間分離絶縁
領域（６）の幅は開口部（５ａ）の幅の１．４〜１．５
倍になるが、窒化シリコン膜（５）の下に下敷膜として
の酸化シリコン膜を用いバーズビークが生じた場合の約
２倍よりは小さくなる。すなわち、厚さが厚く、幅が狭
い素子間分離絶縁領域（６）が形成される。また、窒化
シリコン膜（６１はシリコン基板＋Ｉ＋の表面部を直接
に窒化させたものであるから、シリコン基板（りとの密
着性がよく、また、熱酸化に際してシリコン基板＋１１
に結晶欠陥が生じることがない。さらに、素子間分離絶
縁領域（６１の底面下には不純物導入領域（４）の不純
物が拡散して形成されたシリコン基板（１）より不純物
浸度の高い拡大不純物導入領域（４ａ）が存在しており
、チャンネルストッパーになっている。First, as shown in FIG. 1(a), the silicon substrate (+)
A mask (2) made of photoresist, metal, etc. and having a required opening (2a) is formed on the surface of the mask. next,
As shown in FIG. 1(b), using the mask (2) as a mask, the portion directly below the opening (2a) of the silicon substrate (1) is etched away using a method such as reactive ion etching (R1 phantom). to form a groove (3).Continuing,
As shown in FIG. 1 (0), the groove (
An impurity having the same type as the impurity of the silicon substrate (3) is introduced into a portion below the bottom surface of the silicon substrate (3) by ion implantation or the like to form an impurity-introduced region (4). Furthermore, as shown in FIG. 1(d), after removing the mask (2), the silicon substrate (
1) is directly nitrided to form a silicon nitride film (51
At this time, the silicon nitride film (5) has a groove (
An opening (5a) is formed in a portion r corresponding to 3). A silicon nitride film is also formed on the side and bottom surfaces of the trench (3), but these are removed by etching with hot phosphoric acid after masking the silicon nitride film (5) on the surface of the silicon substrate (1). . Subsequently, when the silicon substrate 11+ is thermally oxidized using the silicon nitride film (6) having the opening (5a) as a mask, the silicon substrate (1) is formed.
*The parts in contact with the bottom and sides of the ill are oxidized, and the silicon oxide is oxidized. An inter-element isolation insulating region (6) can be formed by filling in llN+31. In this case, the width of the element isolation insulation region (6) is 1.4 to 1.5 of the width of the opening (5a).
However, it is smaller than about twice that in the case where a bird's beak is generated using a silicon oxide film as an underlying film under the silicon nitride film (5). That is, an inter-element isolation insulating region (6) having a large thickness and a narrow width is formed. In addition, since the silicon nitride film (61) is obtained by directly nitriding the surface of the silicon substrate +I+, it has good adhesion to the silicon substrate (I+), and also
No crystal defects occur. Further, under the bottom surface of the element isolation insulating region (61), there is an enlarged impurity doped region (4a) with a higher degree of impurity penetration than the silicon substrate (1) formed by diffusion of impurities in the impurity doped region (4). It is a channel stopper.
第２図（ａ）〜（ｅ３）はこの発明による半導体装置の
製造方法の他の実施例の素子間分離絶縁領域の形成方法
の主要段階を示す断面図でおる。第２図において、第１
図と同一符号は第１図にて示したものと同様のものを表
わしている。第２図（ａ） 、 （ｂ）の段階は第１図
（ａ）、 （ｂ）の段階と同様にしで行う。第２図（０
）に示すようにシリコン基板（１）の溝（３）の底面下
の部分にイオン法人法などによってシリコン基板（１）
の不純物と異なる型の不純物を堺大して第１の不純物導
入領域＋？ｌｔ形成する。次に、第２図（ｄ）に示すよ
うに、第２図（０）の場合と同様にして、シリコン基板
＋１１の不純物と同型の不純物を導入して第２の不純物
導入領域（８）を形成する。つづいで、第２図（ｅ）に
示すように、＠１図に示した実施例と同様にして開口１
（５ａ）を有する窒化シリコン膜（６）をマスクにして
シリコン基板ｉｌ＋を熱酸化して同様の素子間分離絶縁
領域（６）を形成する。この場合、第１の不純物導入領
域（７）および第２の不純物導入領域（８）の不純物が
拡散してそれぞれ第１の拡大不純物導入領域（）ａ）お
よび第２の拡大不純物導入領域（８ａ）が形成され、こ
の間に拡散接合容量が形成される。この拡散接合容量は
、素子間分離を強化すると共に、保峡回路の一部として
応用される。FIGS. 2(a) to 2(e3) are cross-sectional views showing the main steps of a method for forming an isolation region in another embodiment of the method for manufacturing a semiconductor device according to the present invention. In Figure 2, the first
The same reference numerals as in the figures represent the same parts as shown in FIG. The steps shown in FIGS. 2(a) and 2(b) are performed in the same way as the steps shown in FIGS. 1(a) and (b). Figure 2 (0
), the silicon substrate (1) is placed under the bottom of the groove (3) of the silicon substrate (1) using an ion corporation method or the like.
The first impurity introduction region +? lt form. Next, as shown in FIG. 2(d), in the same manner as in FIG. 2(0), an impurity of the same type as the impurity in the silicon substrate +11 is introduced to form a second impurity-introduced region (8). Form. Next, as shown in FIG. 2(e), the opening 1 is opened in the same manner as in the embodiment shown in FIG.
A similar inter-element isolation insulating region (6) is formed by thermally oxidizing the silicon substrate il+ using the silicon nitride film (6) having (5a) as a mask. In this case, the impurities in the first impurity doped region (7) and the second impurity doped region (8) are diffused into the first enlarged impurity doped region (a) and the second enlarged impurity doped region (8a), respectively. ) is formed, and a diffusion junction capacitance is formed between them. This diffused junction capacitance strengthens the isolation between elements and is applied as part of the Hokkaido circuit.
以上畦述したように、この発明による半導体装置の製造
方法においては、シリコン基板の一方の主面から内部に
掘り込んだ溝の側面および底面に接するシリコン基板の
部分を、シリコン基板を直接に窒化させて形成した窒化
シリコン膜をマスクにして、熱酸化して溝を酸化シリコ
ンで埋めて素子間分離絶縁領域を形成するので、厚さが
厚く幅が狭い素子間分離絶縁領域を形成することができ
る０As described above, in the method for manufacturing a semiconductor device according to the present invention, the silicon substrate is directly nitrided in the portions of the silicon substrate that are in contact with the side and bottom surfaces of the trench dug inward from one main surface of the silicon substrate. Using the silicon nitride film formed as a mask, thermal oxidation is performed to fill the trenches with silicon oxide to form element isolation insulating regions, making it possible to form thick and narrow inter-element isolation insulating regions. Can do 0
第１図（ａ）〜（ｄ）はこの発明の一実施例のこの発明
に関連のある主要段階を示すｌ！ｉ面図、第２図（ａ）
〜（ｅ）はこの発明の他の集軸側のこの発明に関連のあ
る主要段階を示す断面図である。
図において、（１）はシリコン基板、（３）は溝、（４
）は不純物導入領域、（４ａ）は拡大不純物導入領域、
（６）は窒化シリコン膜、（８１は素子間分離絶に領域
、（７）は第１の不純物導入領域、（７ａ）は第１の拡
大不純物導入領域、（８）は第２の不純物導入領域、（
８ａ）は第２の拡大不純物導入領域である。
なお、図中同一符号はそれぞれ同一または相当部分を示
す。
第１図
手続補正書（自発）
特許庁長官殿
１、事件の表示 特願昭 ５ツ一１０１１０１号
２、発明の名称 半導体装置の製造方法３、補正
をする者
事件との関係 持許出η０人
代表者片由仁へ部
４、代理人
明細書の発明の詳細な説明の橢
６、 補正の内容
明細書をつぎのとおり訂正する。Figures 1(a)-(d) illustrate the main steps relevant to the invention in one embodiment of the invention. i-side view, Figure 2 (a)
-(e) are sectional views showing other main stages related to the present invention on the concentrating side of the present invention. In the figure, (1) is a silicon substrate, (3) is a groove, and (4) is a silicon substrate.
) is the impurity introduced region, (4a) is the enlarged impurity introduced region,
(6) is a silicon nitride film, (81 is an isolation region between elements, (7) is a first impurity doped region, (7a) is a first enlarged impurity doped region, (8) is a second impurity doped region region,(
8a) is a second enlarged impurity doped region. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 1 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office 1. Indication of the case Patent application Sho 5 Tsu-1 No. 101101 2. Title of the invention Method for manufacturing semiconductor devices 3. Relationship with the case of the person making the amendment License η0 To representative Katayuni, Part 4, Detailed explanation of the invention in the agent's specification, Section 6, The description of the amendments will be amended as follows.
Claims (1)
溝を形成する工程、上記シリコン基板の表面部を直接に
窒化させて窒化シリコン膜を形成する工程、上記溝の側
面および底面に形成された窒化シリコン膜を除去する工
程、および残存する上記屋化シリコン膜をマスクにして
上記シリコン基板を熱酸化して酸化−７，ＩＪコンによ
って上記溝を埋めて素子間分離絶縁領域を形成する工程
を備えた半導体装置の製造方法。 （２） シリコン基板の溝の底面に接する部分に上記
シリコン基板の不純物と同−型の不純物を導入すること
によって素子間分離絶縁領域の下にシリコン基板より不
純物濃度の高い不純物導入領域が形成されるようにして
分離効果を高めることを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。 （８） シリコン基板の溝の底面に接する部分にｎ型
およびｐ型の不純物を導入することによって素子間分離
絶縁領域の下に拡散接合容量が形成されるようにしたこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。[Claims] (11) A step of forming a groove dug inward from one main surface of the silicon substrate, a step of directly nitriding the surface portion of the silicon substrate to form a silicon nitride film, A step of removing the silicon nitride film formed on the side and bottom surfaces, and thermally oxidizing the silicon substrate using the remaining silicon nitride film as a mask and filling the trench with oxidation-7 and IJ conductor to isolate the elements. A method for manufacturing a semiconductor device comprising a step of forming an insulating region. (2) Introducing an impurity of the same type as the impurity of the silicon substrate into a portion of the silicon substrate that is in contact with the bottom surface of the trench, thereby forming an isolation insulating region between elements. Claim 1, characterized in that an impurity-introduced region having a higher impurity concentration than the silicon substrate is formed below to enhance the isolation effect.
A method for manufacturing a semiconductor device according to section 1. (8) A patent claim characterized in that by introducing n-type and p-type impurities into the portion of the silicon substrate in contact with the bottom surface of the trench, a diffused junction capacitance is formed under the inter-element isolation insulating region. A method for manufacturing a semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110182A JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10110182A JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58216437A true JPS58216437A (en) | 1983-12-16 |
| JPS6312380B2 JPS6312380B2 (en) | 1988-03-18 |
Family
ID=14291692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10110182A Granted JPS58216437A (en) | 1982-06-10 | 1982-06-10 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58216437A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147951A (en) * | 2004-11-22 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and integrated circuit using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5429573A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Fine machining method of semiconductor |
-
1982
- 1982-06-10 JP JP10110182A patent/JPS58216437A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5429573A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Fine machining method of semiconductor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147951A (en) * | 2004-11-22 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Schottky barrier diode and integrated circuit using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6312380B2 (en) | 1988-03-18 |
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