JPS62113466A - Manufacture of semiconductor memory device - Google Patents

Manufacture of semiconductor memory device

Info

Publication number
JPS62113466A
JPS62113466A JP60252667A JP25266785A JPS62113466A JP S62113466 A JPS62113466 A JP S62113466A JP 60252667 A JP60252667 A JP 60252667A JP 25266785 A JP25266785 A JP 25266785A JP S62113466 A JPS62113466 A JP S62113466A
Authority
JP
Japan
Prior art keywords
groove
capacitor
oxide film
etching
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60252667A
Other languages
Japanese (ja)
Other versions
JPH0712072B2 (en
Inventor
Kenji Anzai
賢二 安西
Yoshiki Nagatomo
良樹 長友
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP60252667A priority Critical patent/JPH0712072B2/en
Publication of JPS62113466A publication Critical patent/JPS62113466A/en
Publication of JPH0712072B2 publication Critical patent/JPH0712072B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the area of a charge storage capacitor in the base section of a groove in addition to the increase of the area only of the side surface section of the capacitor by previously coating a predetermined section in a groove forming section with a substance having an etching rate slower than an silicon substrate and forming a projecting section to the base of the groove after etching. CONSTITUTION:Field oxide films 12 are shaped previously (a), (b) at the same time even in prescribed sections in a groove forming section 12. A mask layer 15 for silicon etching is applied onto the whole surface, and the mask layer 15 in the groove forming section 13 is removed (c). The groove forming section 13 is etched until the field oxide film 12 in the groove forming section 13 is all removed, thus forming a groove for a capacitor, the base thereof has a trapezoid projecting section (d). A capacitor oxide film layer 16 is shaped into the groove for the capacitor, and a polycrystalline silicon electrode 17 is formed, thus obtaining a device having the groove type capacitor (e). The ratio of the etching rates of an silicon substrate 14 and the field oxide film 12 in conditions at the time of etching is kept previously at the ratio or less of desired silicon etching-depth to field oxide film thickness. Accordingly, the groove type capacitor, the base thereof has the projecting section, can be formed simply, and the increase of 30-40% of a charge storage area can be expected in the groove type capacitor.

Description

【発明の詳細な説明】 (産業上の利用分IP) 本発明は半導体記憶装置、特に溝型キャパシタを有する
半導体記憶装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application IP) The present invention relates to a semiconductor memory device, and particularly to a method for manufacturing a semiconductor memory device having a trench type capacitor.

(従来の技術) 溝型キャパシタを有する半導体記憶装置について(よ特
公昭58−12739号公報に示されるものがあり、蓄
積容量を太き(するためにシリコン基板に溝を堀り、こ
の溝に沿ってキャパシタを形成している。
(Prior Art) Regarding a semiconductor memory device having a trench-type capacitor, there is a device shown in Japanese Patent Publication No. 12739/1983, in which a trench is dug in a silicon substrate to increase the storage capacitance. A capacitor is formed along the line.

この溝型キャパシタを有する半導体記憶装置の製造方法
について概説すれば、先づ第3図(a)に示されるよう
に、アクティブ領域11 (あるいはフィールド酸化膜
12頻域)内の溝形成部13を除く全面にエツチングマ
スク層を設ける。しかる後、周知のエツチング技術によ
り、溝形成部13において露出しているシリコン基板1
4(あるいはフィールド酸化膜12)をエツチングし、
溝を形成する。次に第3図(b)のごとく、溝内の表面
にキャパシタ酸化膜層16を設け、さらに多結晶シリコ
ン電極17を形成し溝型キャパシタを得る。
To outline the method for manufacturing a semiconductor memory device having this trench type capacitor, first, as shown in FIG. An etching mask layer is provided on the entire surface except for the etching mask layer. Thereafter, the silicon substrate 1 exposed in the groove forming part 13 is etched using a well-known etching technique.
4 (or field oxide film 12),
Form a groove. Next, as shown in FIG. 3(b), a capacitor oxide film layer 16 is provided on the surface inside the trench, and a polycrystalline silicon electrode 17 is further formed to obtain a trench type capacitor.

(発明が解決しようとする問題点) しかしながら上記、方法で得られた溝型キャパシタは、
プレーナ構造のキャパシタに比べたとき、側面部分のみ
の面積増大を図ったもので、充分な電荷蓄積キャパシタ
面積を得られたものではなかった。
(Problem to be solved by the invention) However, the trench capacitor obtained by the above method is
Compared to a capacitor with a planar structure, the area of only the side portions was increased, and a sufficient charge storage capacitor area could not be obtained.

本発明は、キャパシタの側面部分のみの面積増大に加え
て、溝の底面部分においても電荷蓄積キャパシタ面積の
増大を図る半導体記憶装置の製造方法を提供することを
目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor memory device that increases the area of a charge storage capacitor not only at the side surfaces of the capacitor but also at the bottom surface of the trench.

(問題点を解決するための手段) 本発明の半導体記憶装置の製造方法においては、溝型キ
ャパシタを形成するに際し、溝形成部内の所定部分を予
めシリコン基板よりエツチングレートの遅い物質で覆い
、エツチング後に溝の底面に凸部を設けることを特徴と
するものである。ここでシリコン基板よりエツチングレ
ートの遅い物質としては、酸化シリコン膜が最も適当で
あり、フィールド酸化膜形成時に同時形成する。
(Means for Solving the Problems) In the method for manufacturing a semiconductor memory device of the present invention, when forming a trench capacitor, a predetermined portion within the trench forming portion is covered in advance with a material whose etching rate is slower than that of the silicon substrate. This is characterized in that a convex portion is later provided on the bottom surface of the groove. Here, a silicon oxide film is most suitable as a material whose etching rate is slower than that of a silicon substrate, and it is formed at the same time as the field oxide film is formed.

(作  用) 本発明方法によれば、キャパシタ用溝内の底面に凸部を
設け、溝内の電荷蓄積面積を従来に比へさらに増大させ
たため、キャパシタの平面寸法を大きくとることなく大
容旦の記憶装置を得ることが可能となる。
(Function) According to the method of the present invention, a convex portion is provided on the bottom surface of the capacitor groove, and the charge storage area within the groove is further increased compared to the conventional method. This makes it possible to obtain a storage device of up to 100 days.

(実 施 例) 以下、図面に基づいて本発明を説明する。(Example) The present invention will be explained below based on the drawings.

第1図(al〜(6)ば本発明の第1の実施例を示すも
のである。先づ、アクティブ領域11を周知の酸化膜分
離法によって分離形成するのであるが、このとき溝形成
部13内の所定部分にも同時にフィールド酸化膜12を
形成しておく (第1図(aJ及び(bl参照)。次に
シリコンエツチングのマスク層15を全面に被着し、溝
形成部13のマスク層15を除去する(第1図(e)参
照)。その後、周知のドライエツチング法により露出し
たシリコン基板14とフィールド酸化膜12を同時にエ
ツチングし、溝形成部13内のフィールド酸化膜12が
すべて除去されるまでエツチングを行い、底面に台状の
凸部を有するキャパシタ用溝を形成する(第1図(dl
参照)。
FIGS. 1A to 1C show a first embodiment of the present invention. First, the active region 11 is separated by a well-known oxide film separation method. At the same time, a field oxide film 12 is also formed at a predetermined portion in the groove forming portion 13 (see FIG. The layer 15 is removed (see FIG. 1(e)). Thereafter, the exposed silicon substrate 14 and the field oxide film 12 are simultaneously etched by a well-known dry etching method, until all the field oxide film 12 in the groove forming part 13 is etched. Etching is performed until it is removed, and a capacitor groove having a platform-shaped convex portion on the bottom is formed (see Fig. 1 (dl)).
reference).

前記エツチングの際の条件のうち、シリコン基板14と
フィールド酸化膜12のエツチングレート比は、所望の
シリコンエツチング深さとフィールド酸化膜厚の比以下
に保っておく。例えば、シリコンエツチング深さを3μ
m1フイールド酸化膜厚を5000人とすれば、エツチ
ングレート比は6: 1以下すなわち5: 1あるいは
4: 1等の条件を選択する。
Among the etching conditions, the etching rate ratio between the silicon substrate 14 and the field oxide film 12 is kept below the desired silicon etching depth to field oxide film thickness ratio. For example, set the silicon etching depth to 3μ.
If the m1 field oxide film thickness is 5,000, the etching rate ratio should be 6:1 or less, ie, 5:1 or 4:1.

しかる後、周知の熱酸化法により前記キャパシタ用溝内
にキャパシタ酸化膜層16を設け、さらに多結晶シリコ
ン電極17を形成し、溝型キャパシタを有する半導体記
憶装置を得る(第1図tel参照)。
Thereafter, a capacitor oxide film layer 16 is provided in the capacitor groove by a well-known thermal oxidation method, and a polycrystalline silicon electrode 17 is further formed to obtain a semiconductor memory device having a groove type capacitor (see tel in FIG. 1). .

第2図(a)および(b)は本発明の第2の実施例を示
すものである。前記第1の実施例とほぼ同様であるが、
第2の実施例では溝形成部13内のフィールド酸化Wj
412が第2図(alのごどく形成され、エツチング終
了後の溝においては底面に、−側面とその対向側面を連
結するステップ状の凸部が形成される(第2図(b)参
照)。ただしこの場合、前記凸部の寸法については次の
条件が満たされなければならない。即ち、本発明は従来
の溝型キャパシタよりもその溝内表面積が増大すること
を特徴とするのだから、第2図(b)中の符号で2 m
# −2mk> 0 従って、溝の仕上り形状においてj)k条件が必須とな
る。
FIGS. 2(a) and 2(b) show a second embodiment of the present invention. Almost the same as the first embodiment, but
In the second embodiment, field oxidation Wj in the groove forming portion 13
412 is formed as shown in FIG. 2 (al), and in the groove after etching, a step-shaped convex portion connecting the - side and the opposite side is formed on the bottom surface (see FIG. 2 (b)). However, in this case, the following conditions must be satisfied regarding the dimensions of the convex portion.That is, since the present invention is characterized in that the surface area inside the groove is larger than that of the conventional groove type capacitor, 2 m with the symbol in Figure 2 (b)
# -2mk> 0 Therefore, the j)k condition is essential for the finished shape of the groove.

(発明の効果) 以上説明したように本発明の製造方法によれば、キャパ
シタ形成領域内の一部に予めシリコン基板よりもエツチ
ングレートの遅い物質の被覆層を形成し、その後シリコ
ン基板及び該被覆層を同時にエツチングするようにした
ため、底面に凸部を有する溝型キャパシタを簡便に形成
することができ、この溝型キャパシタでは30〜40%
の電荷蓄積面積の増大が期待できるため、優れた信号出
力特性や耐雑音・ηノアルファ特性を有する半導体記憶
装置の実現が可能となる。
(Effects of the Invention) As explained above, according to the manufacturing method of the present invention, a coating layer of a substance having a slower etching rate than the silicon substrate is formed in advance in a part of the capacitor formation region, and then the silicon substrate and the coating layer are formed in advance. Since the layers are etched at the same time, it is possible to easily form a groove-type capacitor having a convex portion on the bottom surface.
Since the charge storage area can be expected to increase, it becomes possible to realize a semiconductor memory device having excellent signal output characteristics, noise resistance, and η-no-alpha characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al及び第1図(bl〜(elは本発明の第1
の実施例を示す平面図及び断面図、第2図(al及び(
blは本発明の第2の実施例を示す平面図及び斜視図、
第3図(al及び(blは従来の溝型キャパシタを示す
平面図及び断面図である。 11 ・アクティブ領域、12・・・フィールド酸化膜
、13・・・溝(キャパシタ)形成部、14・・シリコ
ン基板、15・マスク層、16・・・キャパシタ酸化膜
層、17・・多結晶シリコン電極。 第 2 凶 0リ 一
FIG. 1 (al and FIG. 1 (bl to (el) are the first
A plan view and a sectional view showing an example of
bl is a plan view and a perspective view showing a second embodiment of the present invention,
FIG. 3 (al and (bl) are a plan view and a cross-sectional view showing a conventional trench capacitor. 11. Active region, 12. Field oxide film, 13. Groove (capacitor) forming portion, 14.・Silicon substrate, 15. Mask layer, 16... Capacitor oxide film layer, 17. Polycrystalline silicon electrode.

Claims (3)

【特許請求の範囲】[Claims] (1)溝型キャパシタを有する半導体記憶装置の製造に
際して、 (a)シリコン基板上の溝型キャパシタ形成領域内の一
部に、前記シリコン基板よりエッチングレートの遅い物
質の被覆層を形成する工程と、 (b)前記溝型キャパシタ形成領域を除く他の領域を覆
うエッチングマスク層を形成する工程と、 (c)前記溝型キャパシタ形成領域内のシリコン基板と
前記被覆層に対して同時にエッチングを行い、底面に凸
部を有する溝を形成する工程と、 (d)形成された溝内部にキャパシタ酸化膜及び電極用
多結晶シリコン層を形成する工程と、を順次施すことを
特徴とする半導体記憶装置の製造方法。
(1) When manufacturing a semiconductor memory device having a trench type capacitor, (a) forming a covering layer of a substance whose etching rate is slower than that of the silicon substrate in a part of the trench type capacitor forming region on the silicon substrate; (b) forming an etching mask layer covering other areas except the trench capacitor formation region; and (c) etching the silicon substrate and the covering layer in the trench capacitor formation region at the same time. (d) forming a capacitor oxide film and an electrode polycrystalline silicon layer inside the formed groove; manufacturing method.
(2)前記シリコン基板よりエッチングレートの遅い物
質は酸化膜層であることを特徴とする特許請求の範囲第
(1)項記載の半導体記憶装置の製造方法。
(2) The method of manufacturing a semiconductor memory device according to claim (1), wherein the material having a slower etching rate than the silicon substrate is an oxide film layer.
(3)前記酸化膜層は酸化膜分離工程で形成されるフィ
ールド酸化膜と同時に形成することを特徴とする特許請
求の範囲第(2)項記載の半導体記憶装置の製造方法。
(3) The method of manufacturing a semiconductor memory device according to claim (2), wherein the oxide film layer is formed at the same time as a field oxide film formed in an oxide film isolation step.
JP60252667A 1985-11-13 1985-11-13 Method of manufacturing semiconductor memory device Expired - Lifetime JPH0712072B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60252667A JPH0712072B2 (en) 1985-11-13 1985-11-13 Method of manufacturing semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60252667A JPH0712072B2 (en) 1985-11-13 1985-11-13 Method of manufacturing semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS62113466A true JPS62113466A (en) 1987-05-25
JPH0712072B2 JPH0712072B2 (en) 1995-02-08

Family

ID=17240553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60252667A Expired - Lifetime JPH0712072B2 (en) 1985-11-13 1985-11-13 Method of manufacturing semiconductor memory device

Country Status (1)

Country Link
JP (1) JPH0712072B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219551A (en) * 1986-03-19 1987-09-26 Mitsubishi Electric Corp Semiconductor memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219551A (en) * 1986-03-19 1987-09-26 Mitsubishi Electric Corp Semiconductor memory

Also Published As

Publication number Publication date
JPH0712072B2 (en) 1995-02-08

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