JPS5931216B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

Generally, as a semiconductor device having this type of multilayer wiring structure, there is a so-called silicon gate field effect semiconductor device using polycrystalline silicon for a gate electrode.

In this semiconductor device, when forming the source and drain regions,
In addition to these regions, another diffusion region may be provided in the semiconductor substrate, and this diffusion region may be used as a wiring region. Further, the above-described semiconductor device uses a diffusion region provided in the semiconductor substrate as a wiring region, and
Polycrystalline silicon produced during the formation of the gate electrode is selectively left and used as a wiring layer. As described above, when manufacturing a semiconductor device that uses polycrystalline silicon as a gate electrode and wiring layer, it is necessary to diffuse impurities into polycrystalline silicon in order to make the polycrystalline silicon conductive.

In general, this impurity diffusion is done in order to avoid duplication of steps.
It is usually performed at the same time as the diffusion process for forming the source and drain regions and the above-mentioned wiring regions in the semiconductor substrate.

0 However, in a method in which impurity diffusion into polycrystalline silicon is performed simultaneously with impurity diffusion into a semiconductor substrate,
The wiring region cannot be formed unless the polycrystalline silicon located above the diffusion wiring region provided in the semiconductor substrate is removed.

Therefore, it is difficult to mount a wiring layer made of polycrystalline silicon on the wiring layer 5 area with an insulating film interposed therebetween. Therefore, in this semiconductor device, the wiring region and the wiring layer are constructed so that they do not overlap, and a perfect multilayer wiring structure cannot be expected, which is one of the factors that prevents miniaturization of the device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a wiring region within a semiconductor substrate and a wiring layer disposed on the semiconductor substrate can be overlapped.

5. Another object of the present invention is to provide a method for manufacturing a semiconductor device that can be expected to achieve higher density.

The present invention provides a method for forming a wiring region in a semiconductor substrate, including the steps of: forming an upper wiring layer that intersects with an area of the semiconductor substrate where the wiring region is to be formed via an insulating film;
forming the wiring region by performing impurity diffusion so that the diffusion layer is continuous from both sides of the upper wiring layer in the area under the upper wiring layer. . 5 The feature of the present invention is that the wiring region is formed by impurity diffusion from both sides of the upper wiring layer, and the diffusion region formed in this way is formed under the insulating layer provided under the wiring layer. A wiring region that extends laterally and has continuous conductivity can be formed.

At the same time, impurity diffusion is also performed on the wiring layer itself, so that it can have the conductivity necessary for the wiring layer. Hereinafter, the present invention will be explained with reference to the drawings. FIGS. 1A and 1B are a cross-sectional view and a plan view for explaining an example of a conventional semiconductor device.

Referring to FIG. 1, in addition to a source region 9 and a drain region 10, a wiring region 4 is formed in a semiconductor substrate 1 by diffusion. Further, in a region between the source region 9 and the drain region 10, a gate insulating film 5 and a gate electrode 7 made of polycrystalline silicon are provided so as to partially overlap the source and drain regions. Further, on the insulating film 2 on the semiconductor substrate 1, a wiring layer 8 made of polycrystalline silicon,
A wiring layer 12 made of an aluminum metal film is provided to form a gap and connect the wiring layers 8 and 8'. In this way, when manufacturing a semiconductor device having multilayer wiring layers, silicon dioxide (SlO2) 2 is first formed on the surface of the semiconductor substrate 1, and the source, drain regions,
The insulating film 2 in the portion corresponding to the gate region and the insulating film 2 in the area where the wiring region is to be provided is selectively removed to expose the surface of the semiconductor substrate 1.

Next, a gate insulating film 5 is formed by thermal oxidation in an oxygen atmosphere, and then a polycrystalline silicon film is provided on the entire surface. This polycrystalline silicon film is selectively etched to form a gate electrode 7.
and wiring layers 8, 8' are formed. Further, the insulating film 5 deposited on the semiconductor substrate 1 is removed, leaving only the portion that will become the gate insulating film, and the semiconductor substrate corresponding to the wiring region 4, source region 9, and drain region 10 is exposed. In this manner, impurity diffusion is performed with the surface of semiconductor substrate 1 being selectively exposed and with polycrystalline silicon layers 8, 8' and gate electrode 7 exposed to the outside.

As a result, the impurity is diffused into the exposed surface and the polycrystalline silicon surface of the semiconductor substrate 1, and further pushed into the conductive source region 9, drain region 10, polycrystalline silicon gate electrode 7, and polycrystalline silicon 7. Wiring layers 8, 8' are formed. Next, after depositing an insulating film 11 on the entire exposed surface, holes are opened at the connecting portions of the polycrystalline silicon wiring layers 8 and 8'. Subsequently, an aluminum metal wiring film is deposited on the entire surface and then selectively etched to form an aluminum metal wiring layer 12 that electrically connects the polycrystalline silicon wiring layers 8 and 8'. In the method described above, the step of providing a diffusion region on a semiconductor substrate and the step of making polycrystalline silicon disposed on the substrate conductive are performed simultaneously.

Therefore, it is difficult to create a multilayer wiring in which the wiring region constituted by the diffusion region and the polycrystalline silicon film overlap. FIGS. 2 to 11 are diagrams showing an embodiment of the present invention in the order of steps.

Here, a case will be described in which a P channel silicon gate MOS transistor is used as the field effect transistor. Referring to FIG. 2, an insulating film 102 made of silicon dioxide is formed to a thickness of 8000 Å on an N-type silicon substrate 101 (eg, resistivity 6Ω·C7n) by thermal oxidation.

Next, as shown in FIG. 3, holes are selectively opened in the insulating film 102 by photolithography to expose the surface of the semiconductor substrate 101 and define the activation region 103 and wiring area 104 of the field effect transistor. . In this case, a hydrofluoric acid solution is suitable as the etching solution for the silicon dioxide film 102. Furthermore, as shown in FIG. 4, a silicon dioxide film 105 having a thickness of 1000λ is deposited on the exposed regions 103 and 104 of the semiconductor substrate 101 by thermal oxidation.

In this case, the insulating film 105 is Si3N4, A
It may also be l2O3 or the like. Next, as shown in Figure 5,
A polycrystalline silicon film 1 is formed on the entire surface of the insulating films 102 and 105.
06 is formed to a thickness of 5000 by thermal decomposition of monosilane (SiLI4). Next, as shown in FIGS. 6A and 6B, the polycrystalline silicon 7 wiring layer 106 is selectively etched by photolithography to define the gate electrode 107 and the polycrystalline silicon wiring layer 108.

During the process, the polycrystalline silicon film 106 is etched using a nitric acid monoglacial acetic acid monofluoric acid based etching solution. In this state, the polycrystalline silicon wiring layer 108 intersects with the wiring area 104 via the insulating film 105 on the wiring area 104, as shown in FIG. 6A. Further, as is clear from the plan view of FIG. 6B, the polycrystalline silicon wiring layer 108 is formed in such a way that the width of the wiring layer becomes narrower in the portion intersecting with the wiring area 104, that is, in the wiring area of the semiconductor substrate 101. A portion of 104 is etched to be exposed. In this example, wiring layer 108 having a width of 8μ is used in wiring area 104.
At the intersection with the wiring layer 108, it is divided into widths of 3 μm each, and a gap is provided inside the wiring layer 108. Figure 7 A and B are the 6th
FIG. 7A is a cross-sectional view taken along the line BOa-a' in FIG. 6, and FIG. It is a sectional view along a line.

Referring to FIG. 7A, the insulating film on the other active regions is removed, leaving the gate insulating film 105 located under the gate electrode 107. Also, referring to Figure 7B,
Only the insulating film 105 under the polycrystalline silicon film 108 is left, and the other parts of the insulating film 105 are removed to expose the surface of the semiconductor substrate 101. In this way, the impurities are diffused with the regions 109 and 110 where the sources and drains are to be formed exposed, and a part of the wiring area 104 where the wiring region is to be formed exposed, and after the diffusion, the impurities are pushed. Figure 8A
7A and 7B are diagrams showing the state after impurity diffusion and indentation, and correspond to FIGS. 7A and 7B, respectively.

As shown in the figure, a source region diffusion layer 109', a drain region diffusion layer 110, and a wiring region diffusion layer 104' are formed on the exposed surface of the semiconductor substrate 101. At this time, in the wiring area 104 where the polycrystalline silicon wiring layer 108 intersects with the insulating film 105, impurities are pushed in from both ends of the narrow polycrystalline silicon wiring layer 108, so that the diffusion deposit area spreads laterally. , a continuous impurity diffusion region 104' is obtained as shown in FIG. 8B. As is clear from this, the width of the narrow polycrystalline silicon layer 108 is selected in consideration of the lateral extent of the diffusion region. In addition, due to the diffusion and indentation of this impurity, the polycrystalline silicon gate film 1
07 and the polycrystalline silicon film 108 become conductive and function as electrodes and wiring layers. In this example, boron trichloride (BCl3) is used as an impurity to be diffused into the N-type silicon substrate, and the layer resistance due to diffusion is 50 (Ω/Ω/cm).
d). Next, as shown in FIG. 9, on the entire surface of the element,
An insulating film 111 having a thickness of 0.5 μm is formed by chemical bonding of monosilane (SiI-114) and oxygen (02), and the insulating film 111 is selectively etched by photolithography.

This partially exposes the polycrystalline silicon wiring layer 108 and the polycrystalline silicon gate electrode 107, or partially exposes the J wiring region 104', source region 105, and drain region 110', and then Prepare for connection by aluminum metal coating to be formed. In this state, as shown in FIG. 10, a metal film 112 of aluminum or the like is deposited on the surface of the element by a thickness of 1.0 μm. Thereafter, as shown in FIG. 11, the metal film 112 is selectively etched by photolithography to form a wiring layer. Note that the aluminum metal film was etched using phosphoric acid. As described above, according to the present invention, it is possible to laminate a wiring region formed by diffusion on the surface of a semiconductor substrate and a polycrystalline silicon layer with an insulating film interposed therebetween, without increasing the number of steps. .

Therefore, a wiring structure is obtained in which the three wiring layers, the wiring area in the semiconductor substrate, the polycrystalline silicon wiring layer, and the metal film wiring layer, are overlapped in the same part through the insulating film, making it possible to create a high-density integrated circuit. can be manufactured. Further, according to the present invention, it is possible to manufacture a semiconductor device having the same function using a multilayer wiring structure in fewer steps than in the conventional manufacturing process.

[Brief explanation of the drawing]

FIGS. 1A and 1B are cross-sectional views and plan views showing the structure of a conventional semiconductor device, and FIGS. 2 to 11 are views for explaining an embodiment of the present invention in the order of steps.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device in which a wiring region is formed in a semiconductor substrate, comprising: forming an upper wiring layer that intersects with an area of the semiconductor substrate in which the wiring region is to be formed via an insulating film; forming the wiring region by performing impurity diffusion so that the diffusion layer is continuous in the area under the upper wiring layer from both sides of the wiring region.