JPH0116015B2 - - Google Patents
Info
- Publication number
- JPH0116015B2 JPH0116015B2 JP58229763A JP22976383A JPH0116015B2 JP H0116015 B2 JPH0116015 B2 JP H0116015B2 JP 58229763 A JP58229763 A JP 58229763A JP 22976383 A JP22976383 A JP 22976383A JP H0116015 B2 JPH0116015 B2 JP H0116015B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- spinel
- electrode
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000013078 crystal Substances 0.000 claims description 56
- 229910052596 spinel Inorganic materials 0.000 claims description 39
- 239000011029 spinel Substances 0.000 claims description 39
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 92
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000010410 layer Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、シリコン基板上に単結晶電極、単
結晶絶縁膜および単結晶シリコン膜を順次積層し
て半導体立体回路素子を形成する半導体立体回路
素子の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor three-dimensional circuit in which a semiconductor three-dimensional circuit element is formed by sequentially laminating a single crystal electrode, a single crystal insulating film, and a single crystal silicon film on a silicon substrate. The present invention relates to a method of manufacturing an element.
一般に、半導体薄膜、電極・配線用薄膜および
絶縁用薄膜を交互に積層して立体的な回路素子、
すなわち半導体立体回路素子を形成し、回路の高
密度化、高集積化を図ることが行なわれている
が、特性の優れた半導体立体回路素子を得るため
に、従来より、前記素子を構成する各材料に単結
晶状態のものを使用し、各材料を単結晶状態のま
ま積層することが試みられている。
In general, three-dimensional circuit elements are created by alternately laminating semiconductor thin films, electrode/wiring thin films, and insulating thin films.
In other words, attempts have been made to form semiconductor three-dimensional circuit elements to increase the density and integration of the circuits, but in order to obtain semiconductor three-dimensional circuit elements with excellent characteristics, it has conventionally been necessary to Attempts have been made to use materials in a single crystal state and to stack each material in a single crystal state.
たとえば、MOSトランジスタを製造する場合、
第１図に示すように、まず、シリコン基板１上に
ソース領域２、ドレイン領域３を形成し、基板１
上に単結晶スピネル膜４を形成するとともに、基
板１とスピネル膜４との界面にシリコン酸化膜５
を形成してスピネル膜４とシリコン酸化膜５との
２重絶縁膜を構成し、つぎに、前記２重絶縁膜に
選択エツチングによりコンタクトホール６を形成
したのち、スピネル膜４上に電極・配線用の単結
晶シリコン膜７を形成し、該シリコン膜７にＮ形
またはＰ形の不純物を高濃度に導入するととも
に、レーザーアニールを施こして低抵抗のシリコ
ン膜７を得る。さらに、シリコン膜７を所定形状
に選択エツチングして電極・配線パターンを形成
したのち、この上面に単結晶絶縁膜としての単結
晶スピネル膜８を形成し、つぎに、単結晶シリコ
ン膜９を形成し、以下前述と同様に、２重絶縁
膜、電極・配線用単結晶シリコン膜、単結晶スピ
ネル膜を順次積層していく。 For example, when manufacturing MOS transistors,
As shown in FIG. 1, first, a source region 2 and a drain region 3 are formed on a silicon substrate 1.
A single crystal spinel film 4 is formed thereon, and a silicon oxide film 5 is formed at the interface between the substrate 1 and the spinel film 4.
A double insulating film of a spinel film 4 and a silicon oxide film 5 is formed by forming a contact hole 6 in the double insulating film by selective etching, and then electrodes and wiring are formed on the spinel film 4. A single-crystal silicon film 7 is formed, and N-type or P-type impurities are introduced into the silicon film 7 at a high concentration, and laser annealing is performed to obtain a low-resistance silicon film 7. Furthermore, after selectively etching the silicon film 7 into a predetermined shape to form an electrode/wiring pattern, a single crystal spinel film 8 as a single crystal insulating film is formed on the upper surface, and then a single crystal silicon film 9 is formed. Then, in the same manner as described above, a double insulating film, a single crystal silicon film for electrodes/wirings, and a single crystal spinel film are sequentially laminated.
ところで、前述したように、デバイスを組み込
むシリコン層間の絶縁膜も単結晶絶縁膜、すなわ
ち単結晶スピネル膜８で形成されるが、この単結
晶スピネル膜８をCVD法で形成した場合、試料
表面にごみ等が付着してスピネル膜８にピンホー
ル１０が発生することがある。このため、前記ス
ピネル膜８上に単結晶シリコン膜９を形成する
と、ピンホール１０を通して単結晶シリコン膜９
と下層デバイスの電極・配線用の単結晶シリコン
膜７とが導通する問題が生じ、この種半導体立体
回路素子の作製歩留りを低下する結果となつてい
る。 By the way, as mentioned above, the insulating film between the silicon layers in which the device is incorporated is also formed of a single crystal insulating film, that is, the single crystal spinel film 8, but when this single crystal spinel film 8 is formed by the CVD method, the Pinholes 10 may occur in the spinel film 8 due to adhesion of dust and the like. For this reason, when the single crystal silicon film 9 is formed on the spinel film 8, the single crystal silicon film 9 can be passed through the pinhole 10.
A problem arises in which conduction occurs between the single-crystal silicon film 7 for electrodes and wiring of the lower layer device, resulting in a decrease in the production yield of this type of semiconductor three-dimensional circuit element.
この発明は、前記の点に留意してなされたもの
であり、単結晶電極の表面を熱酸化して酸化絶縁
膜を形成し、単結晶スピネル膜に生じたピンホー
ルを通して該スピネル膜と単結晶電極とが導通す
ることを防止し、半導体立体回路素子の作製歩留
りを向上することを目的とする。
This invention has been made with the above points in mind, and involves thermally oxidizing the surface of a single crystal electrode to form an oxide insulating film, and connecting the spinel film and the single crystal through pinholes created in the single crystal spinel film. The purpose is to prevent conduction between the electrodes and improve the manufacturing yield of semiconductor three-dimensional circuit elements.
この発明は、シリコン基板上に、単結晶電極、
単結晶絶縁膜および単結晶シリコン膜を順次積層
して半導体立体回路素子を形成する半導体立体回
路素子の製造方法において、前記単結晶電極とし
て単結晶シリコン膜またはシリサイド膜を形成す
る工程と、前記単結晶絶縁膜として単結晶スピネ
ル膜を形成する工程と、前記単結晶スピネル膜を
通して前記単結晶電極を熱酸化し該単結晶電極の
表面に酸化絶縁膜を形成する工程とを含むことを
特徴とする半導体立体回路素子の製造方法であ
る。
This invention provides a single crystal electrode on a silicon substrate,
A method for manufacturing a semiconductor three-dimensional circuit element in which a single crystal insulating film and a single crystal silicon film are successively laminated to form a semiconductor three-dimensional circuit element, which comprises the steps of forming a single crystal silicon film or a silicide film as the single crystal electrode; The method is characterized by comprising a step of forming a single crystal spinel film as a crystal insulating film, and a step of thermally oxidizing the single crystal electrode through the single crystal spinel film to form an oxide insulating film on the surface of the single crystal electrode. This is a method for manufacturing a semiconductor three-dimensional circuit element.
したがつて、この発明の半導体立体回路素子の
製造方法によると、単結晶シリコン膜またはシリ
サイド膜の単結晶電極上に単結晶スピネル膜を形
成後、該スピネル膜を通して単結晶電極の表面に
酸化絶縁膜を形成するため、前記スピネル膜の形
成時にピンホールが生じても、スピネル膜上に形
成された単結晶シリコン膜がピンホールを通して
単結晶電極に導通する不都合を回避できるもので
あり、このため、この種半導体立体回路素子の作
製歩留りを向上できるものである。
Therefore, according to the method of manufacturing a semiconductor three-dimensional circuit element of the present invention, after forming a single crystal spinel film on a single crystal electrode of a single crystal silicon film or a silicide film, oxidation insulation is applied to the surface of the single crystal electrode through the spinel film. Since a film is formed, even if pinholes occur during the formation of the spinel film, the inconvenience of the single crystal silicon film formed on the spinel film being electrically connected to the single crystal electrode through the pinhole can be avoided. , it is possible to improve the production yield of this type of semiconductor three-dimensional circuit element.
つぎにこの発明を、MOSトランジスタを製造
する場合の１実施例を示した第２図とともに詳細
に説明する。
Next, the present invention will be explained in detail with reference to FIG. 2, which shows one embodiment of manufacturing a MOS transistor.
まず、第１の工程において、シリコン基板１
上にシリコン酸化膜からなる拡散マスクを形成
し、基板１の露出部分に不純物を拡散させてソ
ース領域２およびドレイン領域３を形成し、そ
の後拡散マスクを除去する。 First, in the first step, a silicon substrate 1
A diffusion mask made of a silicon oxide film is formed thereon, impurities are diffused into the exposed portion of the substrate 1 to form a source region 2 and a drain region 3, and then the diffusion mask is removed.
つぎに、第２の工程において、基板１上に
CVD法により単結晶スピネル膜４を膜厚500Å
に成長させる。 Next, in the second step, the
Single-crystal spinel film 4 was formed with a thickness of 500 Å using the CVD method.
to grow.
さらに、第３の工程において、wetO2法によ
り前記スピネル膜４を通して基板１の表面を酸
化し、基板１とスピネル膜４との界面にシリコ
ン酸化膜５を厚さ500Åに成長させ、単結晶ス
ピネル膜４とシリコン酸化膜５との２重のゲー
ト絶縁膜を形成する。 Furthermore, in the third step, the surface of the substrate 1 is oxidized through the spinel film 4 by the wetO 2 method, and a silicon oxide film 5 is grown to a thickness of 500 Å on the interface between the substrate 1 and the spinel film 4, and a single crystal spinel film is formed. A double gate insulating film of film 4 and silicon oxide film 5 is formed.
そして、第４の工程において、写真蝕刻法お
よびドライエツチング技術により２重絶縁膜、
すなわち単結晶スピネル膜４およびシリコン酸
化膜５を選択エツチングしてソース領域２およ
びドレイン領域３に通じるコンタクトホール６
を形成する。 In the fourth step, a double insulating film is formed using photolithography and dry etching techniques.
That is, contact holes 6 communicating with the source region 2 and drain region 3 are formed by selectively etching the single crystal spinel film 4 and the silicon oxide film 5.
form.
つぎに、第５の工程において、イオン化蒸着
法により厚さ約0.3μｍの電極・配線用の単結晶
シリコン膜を形成し、該シリコン膜にイオン注
入法によりＮ形またはＰ形の不純物を高濃度に
注入した後、レーザーアニールを施こし、低抵
抗の電極用単結晶シリコン膜７を形成する。 Next, in the fifth step, a single crystal silicon film for electrodes and wiring with a thickness of about 0.3 μm is formed by ionization vapor deposition, and N-type or P-type impurities are injected into the silicon film at a high concentration by ion implantation. After implantation, laser annealing is performed to form a low-resistance single-crystal silicon film 7 for electrodes.
さらに、第６の工程において、前記単結晶シ
リコン膜７を選択エツチングして所定形状の配
線パターンを形成する。 Furthermore, in a sixth step, the single crystal silicon film 7 is selectively etched to form a wiring pattern of a predetermined shape.
つぎに、第７の工程において、前記第２の工
程と同様に、CVD法により単結晶絶縁膜の一
部として単結晶スピネル膜８′を厚さ約0.1μｍ
に成長させる。 Next, in a seventh step, similarly to the second step, a single crystal spinel film 8' is deposited to a thickness of about 0.1 μm as a part of the single crystal insulating film by the CVD method.
to grow.
さらに、第８の工程において、前記第３の工
程と同様に、wetO2法により単結晶スピネル膜
８′を通して電極用単結晶シリコン膜７の表面
を熱酸化し、該表面に酸化絶縁膜となるシリコ
ン酸化膜１１を約0.1μｍ成長させる。 Furthermore, in the eighth step, similarly to the third step, the surface of the single crystal silicon film 7 for electrode is thermally oxidized through the single crystal spinel film 8' by the wetO 2 method, and an oxide insulating film is formed on the surface. A silicon oxide film 11 is grown to a thickness of about 0.1 μm.
そして、第９の工程において、CVD法によ
り前記単結晶スピネル膜８′上に該単結晶スピ
ネル膜８′とともに層間の単結晶絶縁膜を構成
する単結晶スピネル膜８を厚さ約0.3μｍに成長
させ、必要に応じて単結晶スピネル膜８の表面
を平坦化する。 Then, in a ninth step, a single crystal spinel film 8 that constitutes an interlayer single crystal insulating film together with the single crystal spinel film 8' is grown to a thickness of about 0.3 μm on the single crystal spinel film 8' by the CVD method. The surface of the single crystal spinel film 8 is flattened as necessary.
つぎり、第10の工程において、イオン化蒸着
法により単結晶スピネル膜８上に２層目の単結
晶シリコン膜９を厚さ約1.0μｍに成長させる。 Next, in a tenth step, a second layer of single-crystal silicon film 9 is grown to a thickness of about 1.0 μm on single-crystal spinel film 8 by ionization vapor deposition.
以下、第１ないし第10の工程を繰り返して第２
層目、第３層目、…の半導体回路を形成する。 From then on, repeat steps 1 to 10 to obtain the second step.
A semiconductor circuit is formed in the third layer, the third layer, and so on.
したがつて、前記実施例によると、第８の工程
において電極用単結晶シリコン膜７の表面にこの
上の単結晶スピネル膜８′を通してシリコン酸化
膜１１を形成し、シリコン膜７をシリコン酸化膜
１１で覆うことができるため、第９の工程におい
て単結晶スピネル膜８を形成した場合、試料表面
にごみ等が付着してスピネル膜８にピンホール１
０が発生しても、第10の工程において形成された
単結晶シリコン膜９がピンホール１０を通つて電
極用単結晶シリコン膜７に至ることはなく、下層
デバイスの電極と上層デバイスとの導通を防止で
き、半導体立体回路素子の作製歩留りを向上でき
るものである。 Therefore, according to the embodiment, in the eighth step, a silicon oxide film 11 is formed on the surface of the electrode single crystal silicon film 7 through the single crystal spinel film 8' thereon, and the silicon film 7 is replaced with a silicon oxide film. Therefore, when the single crystal spinel film 8 is formed in the ninth step, dust etc. may adhere to the sample surface and pinholes 1 may be formed in the spinel film 8.
Even if 0 occurs, the single crystal silicon film 9 formed in the tenth step will not reach the electrode single crystal silicon film 7 through the pinhole 10, and the conduction between the electrode of the lower layer device and the upper layer device will be maintained. It is possible to prevent this and improve the manufacturing yield of semiconductor three-dimensional circuit elements.
なお、前記では、単結晶電極として単結晶シリ
コン膜７を用いた場合を示したが、単結晶シリサ
イド膜を用いても同様の効果があることは容易に
類推できる。 Note that although the case where the single-crystal silicon film 7 is used as the single-crystal electrode has been described above, it can be easily inferred that the same effect can be obtained even if a single-crystal silicide film is used.
第１図は従来の半導体立体回路素子の断面図、
第２図はこの発明の半導体立体回路素子の製造方
法の１実施例による半導体立体回路素子の断面図
である。
１…シリコン基板、７…電極用単結晶シリコン
膜、８，８′…単結晶スピネル膜、９…単結晶シ
リコン膜、１１…シリコン酸化膜。
Figure 1 is a cross-sectional view of a conventional semiconductor three-dimensional circuit element.
FIG. 2 is a sectional view of a semiconductor three-dimensional circuit element according to an embodiment of the method for manufacturing a semiconductor three-dimensional circuit element of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 7... Single-crystal silicon film for electrodes, 8, 8'... Single-crystal spinel film, 9... Single-crystal silicon film, 11... Silicon oxide film.
Claims (1)
膜および単結晶シリコン膜を順次積層して半導体
立体回路素子を形成する半導体立体回路素子の製
造方法において、 ） 前記単結晶電極として単結晶シリコン膜ま
たはシリサイド膜を形成する工程と、 ） 前記単結晶電極上に、第１の単結晶スピネ
ル膜を形成する工程と、 ） 前記第１の単結晶スピネル膜を通して前記
単結晶電極を熱酸化し、該単結晶電極の表面に
酸化絶縁膜を形成する工程と、 ） 前記熱酸化工程の後、前記第１の単結晶ス
ピネル膜上に、第２の単結晶スピネル膜を形成
する工程と、 ） 第１、第２の単結晶スピネル膜を前記単結
晶絶縁膜とし、該単結晶絶縁膜上に単結晶シリ
コン膜を形成する工程と、 を含むことを特徴とする半導体立体回路素子の製
造方法。[Scope of Claims] 1. A method for manufacturing a semiconductor three-dimensional circuit element in which a semiconductor three-dimensional circuit element is formed by sequentially laminating a single crystal electrode, a single crystal insulating film, and a single crystal silicon film on a silicon substrate, including: ) the single crystal; a step of forming a single crystal silicon film or a silicide film as an electrode, a step of forming a first single crystal spinel film on the single crystal electrode, and a step of forming the single crystal electrode through the first single crystal spinel film. a step of thermally oxidizing to form an oxide insulating film on the surface of the single crystal electrode; and) after the thermal oxidation step, forming a second single crystal spinel film on the first single crystal spinel film. A semiconductor three-dimensional circuit element comprising the following steps: (1) using the first and second single-crystal spinel films as the single-crystal insulating film, and forming a single-crystal silicon film on the single-crystal insulating film. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22976383A JPS60123048A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor solid circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22976383A JPS60123048A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor solid circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60123048A JPS60123048A (en) | 1985-07-01 |
| JPH0116015B2 true JPH0116015B2 (en) | 1989-03-22 |
Family
ID=16897287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22976383A Granted JPS60123048A (en) | 1983-12-07 | 1983-12-07 | Manufacture of semiconductor solid circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60123048A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586147A (en) * | 1981-07-03 | 1983-01-13 | Nec Corp | Semiconductor device and its manufacture |
-
1983
- 1983-12-07 JP JP22976383A patent/JPS60123048A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586147A (en) * | 1981-07-03 | 1983-01-13 | Nec Corp | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60123048A (en) | 1985-07-01 |
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