JPS627708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has a semiconductor substrate having a first insulating layer formed on its main surface, a conductive layer selectively formed on the first insulating layer, and , relates to a method for manufacturing an MIS type semiconductor device having a configuration in which the conductive layer is embedded in a second insulating layer.

A semiconductor substrate has a first insulating layer formed on a main surface, a conductive layer is selectively formed on the first insulating layer, and the conductive layer is a second insulating layer. MIS with a configuration embedded by
The MIS type semiconductor device is also conventionally seen in MIS type semiconductor devices that constitute MIS type transistors.

Now, the MIS type transistor is made up of
A conventional example of a MIS type semiconductor device has the configuration described below with reference to FIG.

That is, it has a P-type semiconductor substrate 1 made of, for example, P-type silicon, and has an insulating layer 4 made of a relatively thick silicon oxide layer forming a relatively large window 3 on its main surface 2 side. .

On the other hand, N-type semiconductor regions 5 and 6 are formed on the main surface 2 side within the region within the window 3 when viewed from above the semiconductor substrate 1.
are formed as a source region and a drain region, respectively.

Further, windows 7 and 8 are provided on the area facing the window 3 of the main surface 2, and allow the semiconductor regions 5 and 6 to be exposed to the outside.
An insulating layer 9 made of a relatively thin silicon oxide layer is formed using a region below a conductive layer 10, which will be described below, as a gate insulating layer.

Furthermore, the semiconductor region 5 seen from above the insulating layer 9
and 6, a conductive layer 10 is formed as a gate electrode, and an insulating layer 1 is formed on the outer surface of the conductive layer 10 so as to embed this conductive layer 10.
1 is formed.

Further, conductive layers 12 and 13 connected to semiconductor regions 5 and 6 through windows 7 and 8 and extending over insulating layers 4 and 11 serve as a source electrode/wiring layer and a drain electrode/wiring layer, respectively. , is formed.

Further, a window 14 is formed in the insulating layer 11 so that the conductive layer 10 is exposed to the outside, and a conductive layer 15 is formed which is connected to the conductive layer 10 through the window 14 and extends onto the insulating layer 4. ing.

The above constitutes an MIS type transistor.
This is a configuration of a conventional example of an MIS type semiconductor device.

The MIS type semiconductor device having such a configuration is
The conductive layer 10 is embedded in the insulating layer 11, and therefore, as shown in the figure, the insulating layer 11
1, the other conductive layers 12 and 13 can be extended so as to overlap with the conductive layer 10 when viewed from above, so that not only can the conductive layers 12 and 13 be easily formed, but also the overall structure can be improved. It has great features such as being small and being able to be compacted.

In addition, as shown in Fig. 1, which has such characteristics
The MIS type semiconductor device can be manufactured by the method described below with reference to FIG.

That is, although the same reference numerals are given to corresponding parts to those in FIG. 1 and detailed explanation is omitted, an insulating layer 4 forming a window 3 on the main surface 2 side is formed as shown in FIG. 2A. , and a semiconductor substrate 1 having an insulating layer 9 formed on the region facing the window 3 of the main surface 2 is prepared in advance, and a conductive layer 10 is formed on the insulating layer 4 as shown in FIG. 2B. form.

Next, an insulating layer 11 is formed on the outer surface of this conductive layer 10, as shown in FIG. 2C.

Next, as shown in FIG. 2D, windows 7' and 8' are formed in the insulating layer 9.

Next, as shown in FIG. 2E, semiconductor regions 5 and 6 are formed in the semiconductor substrate 1 by thermal diffusion treatment of impurities through the windows 7' and 8'.
At this time, an oxide layer that is connected to the insulating layer 9 is formed on the semiconductor regions 5 and 6 (for simplicity, in the drawings and the following explanation, this oxide layer and the insulating layer 9 are included in the insulating layer). layer 9).

Next, as shown in FIG. 2F, windows 7 and 8 are formed in this insulating layer 9 so as to expose the semiconductor regions 5 and 6, and then, or before that, windows 7 and 8 are formed in the insulating layer 11.
A window 14 is bored through which the conductive layer 10 is exposed to the outside.

Next, as shown in FIG. 2G, the semiconductor region 5,
6 and 10 are formed with conductive layers 12, 13 and 14 connected through windows 7, 8 and 14, respectively.

The above is an example of the method for manufacturing the MIS type semiconductor device shown in FIG.

By the way, in the case of the MIS type semiconductor device described above in FIG. 1, conventionally, the conductive layer 10 is formed of polycrystalline silicon or molybdenum silicide, and the insulating layer 11 is formed of such polycrystalline silicon or molybdenum silicide. Generally, the conductive layer 10 is formed by oxidizing the outer surface of the conductive layer 10.

In addition, when obtaining such a conventional MIS type semiconductor device, conventionally, when it is obtained by the process described above in FIG. 2, the conductivity obtained by the process described above in FIG. 2B is Layer 10 is formed of polycrystalline silicon or molybdenum silicide, and
Insulating layer 11 obtained by the process described above in FIG. 2C
was usually formed by thermal oxidation in a high-temperature oxidizing atmosphere.

However, in the case of the conventional MIS type semiconductor device and its manufacturing method described above, since the insulating layer 11 is formed by thermal oxidation of the surface of the conductive layer 10 in a high temperature oxidizing atmosphere, during the thermal oxidation treatment, The polycrystalline silicon or molybdenum silicide of the conductive layer 10 is recrystallized and the conductive layer 10 is obtained with a rough surface.
There were certain limits to creating a fine shape with high precision.

Furthermore, looking at the breakdown voltage of the insulating layer 11, when the insulating layer 11 is formed by thermal oxidation of the surface of a conductive layer made of polycrystalline silicon, the breakdown voltage is the same as that of a normal one with the same thickness. It was only about half the thickness of a silicon thermal oxide film, and there were problems with the withstand voltage and insulation properties of the insulating layer 11.

Further, as shown in FIG. 3, the conductive layer 10 is obtained in a warped shape, and the insulating layer 1
1 is a conductive layer 10 as also shown in FIG.
The conductive layer 10 is formed in a raised manner at a position corresponding to the upper edge, and therefore the entire area of the conductive layer 10 does not face the main surface 2 of the semiconductor substrate 1 with a predetermined spacing, and thus the resulting MIS type semiconductor Not only is there a risk that the device may not have the desired characteristics, but there is also a risk that the conductive layers 12 and 13 may not be able to adhere well and extend over the insulating layer 11. Ta.

Furthermore, since the insulating layer 11 is formed by thermal oxidation of the surface of the conductive layer 10, it is preferable that the insulating layer 11, which is formed by thermal oxidation of the surface of the conductive layer 10, be made of an electrically and chemically stable material. It has various drawbacks, such as being limited to the polycrystalline silicon or molybdenum silicide materials mentioned above.

Therefore, the present invention provides a new and novel product free from the above-mentioned drawbacks.
The purpose is to propose a method for manufacturing an MIS type semiconductor device, which will become clear from the detailed description below with reference to the drawings from FIG.

First, in order to facilitate understanding of the method for manufacturing an MIS type semiconductor device according to the present invention, a configuration diagram of an MIS type transistor that can be obtained by the method for manufacturing an MIS type semiconductor device according to the present invention will be explained with reference to FIG. An example of a MIS type semiconductor device is:
It has an apparently similar configuration to that in FIG.
Although the same reference numerals are given to parts corresponding to those in the figure and detailed explanations are omitted, the insulating layer 11 is obtained by thermally melting a hot-melting glass material as a starting material, and the windows 7 and 8 are , has the same configuration as described above in FIG. 1, except that it extends from a position corresponding to the outer edge of the insulating layer 11 in this case.

The above is an example of the configuration of an MIS type semiconductor device that can be obtained by the method of manufacturing an MIS type semiconductor device according to the present invention. It is clear that an MIS type transistor similar to that described above is configured. In addition, as described above in Fig. 1,
Since the other conductive layers 12 and 13 can be extended on the insulating layer 11 so as to overlap with the conductive layer 10 when viewed from above, the conductive layers 12 and 13 can not only be easily formed, but also can be formed as a whole. In addition to having great features such as being small and compact, as will become clearer from what will be described later, the insulating layer 11 is formed by thermal oxidation of a conductive layer as in the case of FIG. However, since the conductive layer is obtained by thermally melting a hot-melting glass material as a starting material, the conductive layer cannot be warped as described above in FIG. Since the insulating layer 11 does not bulge at the position corresponding to the upper edge of the conductive layer 10, the MIS type semiconductor device obtained has the desired characteristics and is conductive. It has great features such as the fact that layers 12 and 13 extend well over insulating layer 11.

Next, with Figure 5, the MIS described above in Figure 4
An example of a method for manufacturing an MIS type semiconductor device according to the present invention will be described to obtain a MIS type semiconductor device.

In FIG. 5, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

An example of the method for manufacturing the MIS type semiconductor device according to the present invention shown in FIG. 5 includes the following sequential steps:
The MIS type semiconductor device described above with reference to FIG. 4 is manufactured.

That is, as shown in FIG. 4A, a relatively thick insulating layer 4 made of, for example, a silicon oxide layer forming a window 3 on the main surface 2 side is formed, and a region of the main surface 2 facing the window 3 is formed. A semiconductor substrate 1 is prepared in advance, on which an insulating layer 9 made of, for example, a silicon oxide layer and having a relatively thin thickness of, for example, about 500 Å is formed. , as shown in FIG. 5B, a conductive layer 51 made of a polycrystalline silicon layer is formed.

Next, on this conductive layer 51, as shown in FIG. 5C, an insulating layer 52 made of a heat-melting glass material is formed.

Next, by selectively removing the insulating layer 52 by photo-etching the insulating layer 52, as shown in FIG. 5D, from the insulating layer 52,
An insulating layer 53 is formed which extends across the window 3 when viewed from above.

Next, a conductive layer 51 using the insulating layer 53 as a mask
By selectively etching the
As shown in FIG.
A conductive layer 10 is formed by the region below.

Next, for example, 1000 in a nitrogen gas atmosphere.
As shown in FIG. 5F, an insulating layer 54 is formed from the insulating layer 53 by thermally melting the insulating layer 53 at a temperature of 1200° C. to 1200° C., in which the conductive layer 10 is buried and the insulating layer 54 is connected to the insulating layer 9. .

Next, the insulating layers 9 and 54 are etched using a common etchant while a mask material (not shown) is previously formed in a partial area on the insulating layer 54, as shown in FIG. 5G. As shown, the insulating layer 11 whose surface is partially etched is formed from the insulating layer 54, and the area of the insulating layer 9 other than the area under the insulating layer 11 is selectively removed to form the main part of the semiconductor substrate 1. Windows 7 and 8 are formed so that the surface 2 faces the outside. Note that in FIG. 5G, the insulating layer 11
The thick region is the region where the mask material was formed during the etching process.

Next, by selectively etching the insulating layer 11, a window 14 is formed in the insulating layer 11 at a position on the conductive layer 10, as shown in FIG. 5H.

Next, as shown in FIG. 5I, the insulating layer 4 is connected to the semiconductor substrate 1 through the windows 7 and 8, respectively.
conductive layers 12 and 13 consisting of a layer of polycrystalline silicon extending over and over 11; and a layer of polycrystalline silicon connected to conductive layer 10 through window 14 and extending over insulating layer 11. Layer 15 is formed, for example, by vapor deposition of a conductive material followed by selective etching.

Next, N
After implanting type impurity ions, heat treatment is performed to form N-type semiconductor regions 5 and 6 connected to conductive layers 12 and 13, respectively, in regions facing windows 7 and 8 of semiconductor substrate 1. Form.

The above is an example of a method for manufacturing an MIS type semiconductor device according to the present invention to obtain the MIS type semiconductor device described above with reference to FIG.

According to such a manufacturing method, in particular, the insulating layer 11
However, it is not formed by thermal oxidation of the conductive layer 10 as in the conventional case described above with reference to FIG. Since the conductive layer 10 is formed based on thermal melting of the conductive layer 53, the conductive layer 10 will not be warped as described above with reference to FIG.

Further, the insulating layer 10 is not obtained in a heaped manner, and furthermore, the conductive layer 10 in the finally obtained MIS type semiconductor device maintains the shape as it was before obtaining the insulating layer 11. aim
The MIS type semiconductor device has excellent characteristics, and can be easily obtained in a compact and compact manner.

Furthermore, since the windows 7 and 8 can be obtained without using a mask for the windows 7 and 8, a desired MIS type semiconductor device can be easily obtained.

Note that the above description merely shows one embodiment of the present invention, and detailed explanation is omitted.
In the manufacturing method according to the present invention described above in the figures, the etching treatment for the conductive layer 51 is shown in FIG.
6, corresponding to FIG. The same steps as those described above are taken to compensate for the fact that the insulating layers 54 to 11 are thinner at positions corresponding to the upper outer edge of the conductive layer 10 than at other positions. You can also do this.

Further, although a detailed explanation is omitted, in the manufacturing method according to the present invention described above with reference to FIG. As shown in FIG. 5, steps similar to those described above in FIG. 5 are taken, except that the insulating layer 54 is formed by oxidizing the surface of the conductive layer 10, and then the insulating layer 54 is formed. Because the thickness of the position corresponding to the upper outer edge of the conductive layer 10 of 1 to 11 is thinner than other positions, the withstand voltage of the insulating layer 11, which can be a problem, is reduced by the surface of the conductive layer 10. Compensation can also be provided by an oxidized layer.

Furthermore, in the above, the MIS type semiconductor device
Although it has been described as an MIS type semiconductor device that constitutes an MIS type transistor, any other MIS
The present invention can also be applied to obtain a type semiconductor device,
In addition, various modifications and changes may be made without departing from the spirit of the present invention, such as forming the conductive layer 10 with a layer made of a conductive material other than a polycrystalline silicon layer.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing a conventional MIS type semiconductor device. FIG. 2 is a schematic cross-sectional view showing sequential steps of a manufacturing method for obtaining the MIS type semiconductor device shown in FIG. 1. Figure 3 shows the conventional
FIG. 2 is a schematic cross-sectional view showing a part of the MIS type semiconductor device. FIG. 4 is a schematic cross-sectional view showing an example of an MIS type semiconductor device that can be obtained by the method of manufacturing an MIS type semiconductor device according to the present invention. FIG. 5 is a schematic cross-sectional view of sequential steps showing an example of a method for manufacturing an MIS semiconductor device according to the present invention to obtain an example of the MIS type semiconductor device shown in FIG. 4. 6 and 7 are schematic cross-sectional views showing other examples of the method for manufacturing an MIS type semiconductor device according to the present invention. 1...Semiconductor substrate, 2...Main surface, 3...Window, 4
...Insulating layer, 5, 6...Semiconductor region, 7,8...
Window, 9... Insulating layer, 10... Conductive layer, 11...
Insulating layer, 12, 13... Conductive layer, 14... Window,
15... Conductive layer, 51... Conductive layer, 52,5
3,54...Insulating layer.

Claims (1)

[Scope of Claims] 1. The first insulating layer on the main surface of a semiconductor substrate prepared in advance and having a first insulating layer formed on the main surface.
forming a first conductive layer on the insulating layer; forming a second insulating layer made of a hot-melt glass material on the first conductive layer; and forming the second insulating layer on the first conductive layer. selectively removing the second insulating layer to form a third insulating layer; and selectively etching the first conductive layer using the third insulating layer as a mask. burying the second conductive layer by forming a second conductive layer using a region under the third insulating layer of the first conductive layer; and heat treating the third insulating layer; forming a fourth insulating layer obtained by thermally melting the third insulating layer. 2. In the method for manufacturing an MIS type semiconductor device as set forth in claim 1, the first conductive layer is etched by selectively etching the first conductive layer using the third insulating layer as a mask. In the step of forming a second conductive layer in a region under the third insulating layer, the second conductive layer is formed so that its outer edge is inside the outer edge of the third insulating layer. A method for manufacturing an MIS type semiconductor device, characterized in that a first conductive layer is selectively etched. 3. The first insulating layer on the main surface of the semiconductor substrate, on which the first insulating layer is formed, is prepared in advance.
forming a first conductive layer on the insulating layer; forming a second insulating layer made of a hot-melt glass material on the first conductive layer; and forming the second insulating layer on the first conductive layer. selectively removing the second insulating layer to form a third insulating layer; and selectively etching the first conductive layer using the third insulating layer as a mask. The step of forming a second conductive layer by the region under the third insulating layer of the first conductive layer, and the heat treatment of the third insulating layer in a high temperature oxidizing atmosphere, The surface of the conductive layer is oxidized to form a fourth insulating layer in which the second conductive layer is buried;
forming a fifth insulating layer obtained by thermally melting the third insulating layer in which the conductive layer is buried together with the fourth insulating layer. Manufacturing method. 4. The first insulating layer on the main surface of the semiconductor substrate prepared in advance and having the first insulating layer formed on the main surface.
forming a first conductive layer on the insulating layer; forming a second insulating layer made of a hot-melt glass material on the first conductive layer; and forming the second insulating layer on the first conductive layer. selectively removing the second insulating layer to form a third insulating layer; and selectively etching the first conductive layer using the third insulating layer as a mask. burying the second conductive layer by forming a second conductive layer using a region under the third insulating layer of the first conductive layer; and heat treating the third insulating layer; forming a fourth insulating layer obtained by thermally melting the third insulating layer, and etching the first and fourth insulating layers using a common etchant; forming a fifth insulating layer of the fourth insulating layer whose surface is etched, and selectively removing a region of the first insulating layer other than under the fifth insulating layer; forming a window that exposes the main surface of the semiconductor substrate to the outside only in a selectively removed region of the first insulating layer other than under the fifth insulating layer. A method for manufacturing an MIS type semiconductor device characterized by: