JPS6159664B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an insulated gate field effect transistor.

One of the conventional insulated gate field effect transistors is to form drain and source regions of opposite conductivity type on a semiconductor substrate of one conductivity type, and to form a thin insulated gate film on the surface of the semiconductor substrate between these regions. Thereafter, an opening is formed in the insulating film deposited above the drain/source region, an ohmic electrode is led out from the drain/source region, and a gate electrode is provided on the gate film together with the ohmic electrode.

According to this type of manufacturing method, the insulated gate film region is aligned between the drain and source regions by photolithography, which increases the geometrical shape of this type of transistor and makes it possible to create a semiconductor monolithic IC.
This was hindering the improvement of the degree of integration. In addition, for the same reason, the gate electrode and the drain/source regions overlap each other with a thin insulating gate film in between, so the gate electrode has a floating capacitance, which causes electrical characteristics of this type of insulated gate transistor. It has the disadvantage that improvement is hindered.

On the other hand, in order to improve the drawbacks of the above-mentioned insulated gate transistor, a thin insulated gate film is formed on the surface of a semiconductor substrate of one conductivity type, and then a polycrystalline silicon film is grown in a vapor phase, and this polycrystalline silicon film is selectively etched. After that, polycrystalline silicon is left only in the gate electrode formation part, and then impurities are diffused and oxidized to simultaneously form the drain/source region and gate electrode of the opposite conductivity type to the substrate, and then the insulation is deposited on the surface. A silicon gate field effect transistor has been proposed in which an ohmic electrode is led out from the drain/source region and gate electrode by providing an opening in the film.

However, since polycrystalline silicon needs to function as a gate electrode after diffusion and oxidation of impurities, its film thickness cannot be made thin and requires a thickness of 5,000 to 8,000 Å.

As a result, the accuracy of selective corrosion of polycrystalline silicon deteriorates, making it difficult to accurately shorten the channel length of the transistor, which greatly contributes to the electrical characteristics of the insulated gate field effect transistor.

It is an object of the present invention to provide a method of manufacturing an insulated gate field effect transistor having short channels with high accuracy by eliminating the drawbacks of the various insulated gate field effect transistors described above and facilitating manufacturing.

The method for manufacturing an insulated gate field effect transistor according to the present invention includes a step of covering one principal plane of a semiconductor substrate of one conductivity type with an insulating film and a thinner gate insulating film, and forming a film to become a gate electrode on the gate insulating film. a step of forming the gate electrode, a PR resist film obtained by adding only the gate electrode or a photo-etching step, a step of removing the insulating film using the gate electrode as a mask to expose the substrate surface, and a step of infiltrating impurities from this exposed portion. A process of oxidizing to form drain and source regions of opposite conductivity type to the substrate, and
The method is characterized in that it includes the step of forming an opening in the source region by photolithography and leading out an ohmic electrode.

According to the present invention, using a thin gate insulating film on the surface of a semiconductor substrate of one conductivity type as a mask, drain and source regions of the opposite conductivity type to the substrate are formed in self-alignment,
In addition, an insulated gate field effect transistor is obtained in which the gate electrode and the drain (source) region partially overlap with an insulating film thicker than the gate insulating film interposed therebetween.

Next, one embodiment of the present invention will be described with reference to FIG.

A silicon dioxide film 2 grown to a thickness of about 2,000 to 4,000 Å by thermally oxidizing the entire surface of a P-type silicon single crystal substrate 1 is photo-etched to open holes, and then thermally oxidized again to form a thin film of 400 to 800 Å in thickness. A silicon dioxide film 3 that will become a gate insulating film is grown (see Fig. 1A,
A') Next, after a polycrystalline silicon film with a thickness of about 6000 Å is grown in a vapor phase, the remaining part is removed by photolithography, leaving only the part 4 that will become the gate electrode (FIGS. 1B and B').

Next, an opening 5 is formed in the resist film by photolithography (FIG. 1 C, C'), and the silicon dioxide film 2 is removed to the vicinity of the gate insulating film 3 using the polycrystalline silicon film 4 and the resist film as a mask. After opening the hole 7 and exposing the surface of the substrate 1, the PR resist film is removed (FIG. 1D). Thereafter, phosphorus is diffused and oxidized into the substrate 1 through the polycrystalline silicon film piece 4 and the opening 7 to simultaneously form an N conductivity type drain/source region 8 and a gate electrode 9 (FIG. 7E). Next, holes are formed above the drain/source region 8 and above the gate electrode by photolithography, and aluminum wiring is then formed to obtain an N-channel field effect transistor.

On the other hand, if a part of the thin gate insulating film 2 between the polycrystalline silicon film piece 4 and the substrate 1 is excessively etched due to overetching in the step of etching the silicon dioxide film 2 (FIG. 1D), By adding a step of filling this void with silicon dioxide by thermal oxidation (Fig. 1E), then melt-diffusion and oxidation of phosphorus, and performing the same steps as above, an N-channel field effect transistor is formed. is obtained.

Next, another embodiment of the present invention will be described with reference to FIG.

Openings 12 are formed by photolithography in a silicon dioxide film 11 having a thickness of 5,000 to 8,000 Å, which is deposited by oxidizing the entire surface of the P-type single crystal substrate 10 (FIG. 2A). Thereafter, a silicon nitride film 13 with a thickness of 1000 to 2000 Å is deposited on the entire surface by vapor phase growth, and then a portion of the nitride film is oxidized by thermal oxidation at 1000°C for 100 minutes in a steam atmosphere. A silicon dioxide film 14 of 100 Å is formed (FIG. 2B). Next, holes are formed in this silicon dioxide film by photolithography, the photoresist is removed, and the silicon nitride film 13 is removed using this silicon dioxide film as a mask to expose the surface of the substrate 10. (Figure 2C). Next, the silicon dioxide film 14 used as a mask is completely removed, and then thermal oxidation is performed at 950°C for 10 minutes in a steam atmosphere to change the exposed surface of the substrate to silicon dioxide with a thickness of 500 to 800 Å.
A gate insulating film 15 is formed (FIG. 2D).

After that, polycrystalline silicon is deposited on the entire surface,
By photolithography, a portion 16 that will become the gate electrode is left (FIG. 2 E, E'). Next, if the nitride film 13 is completely removed using the polycrystalline silicon film piece 16 that will become the gate electrode as a mask, the geometrical shape of the gate insulating film 15 will not change at all (FIG. 2F). Thereafter, phosphorus is diffused into the substrate 1 and the polycrystalline silicon piece 16 and oxidized to form an N-conducting drain.
By forming the source region 17 and the gate electrode 18, an N-channel field effect transistor as shown in FIG. 2G is obtained.

This embodiment is characterized in that the photoresist film 6 corresponding to FIG. 1C is unnecessary, and that the geometry of the gate insulating film 15 produced in FIG. 2D does not change during all subsequent steps. .

These embodiments of the invention have a number of advantages as described below.

First, as seen in each embodiment, the drain/source regions are self-aligned using the contact surfaces between the polycrystalline silicon film pieces 4, 16 and the thin silicon dioxide films 3, 15 as masks, as shown in FIG. D. As seen in FIG. 2F, polycrystalline silicon film piece 4,
In order to allow phosphorus to infiltrate into the substrates 1, 10 from the gap below 16, the channel length of the transistor of the present invention does not depend on the manufacturing precision of the polycrystalline silicon film pieces 4, 16, and is set as shown in FIG. 1A, FIG. 2C, It is determined depending on the manufacturing precision of the geometrical shape of the thin silicon dioxide films 3 and 15 in D.

On the other hand, the geometric shapes of the thin silicon dioxide films 3 and 15 are determined by the etching accuracy of the silicon dioxide film 2 (nitride film 13) with a thickness of 1000 to 2000 Å, but this type of etching is limited to 4000 to 6000 Å. This allows for more precise control than etching of polycrystalline silicon, making it easier to create short channel transistors than conventional silicon gate field effect transistors, where the channel length is determined by etching the polycrystalline silicon film. realizable.

Second, as the channels of conventional silicon gate field effect transistors become shorter, the geometric shape of the polycrystalline silicon that serves as the gate electrode needs to be narrower in the channel width direction. The internal resistance in the channel width direction increases, deteriorating the electrical characteristics of this type of transistor, but in this example, as shown in FIGS. 1E and 2G, the channel length and the gate electrode This type of drawback is eliminated since the geometry of the crystalline silicon film pieces can be determined independently.

3 and 4 are for explaining other advantages of the present invention, and FIG. 3 shows that the polycrystalline silicon piece 4 of FIG. Everything else is the same except that FIG. 4 shows only the diffusion layer region in this example.

Now, if we remove the portion corresponding to the silicon dioxide film 2 in FIG. In the conventional silicon gate field effect transistor, impurities are not diffused directly under the lead-out part of piece 19, and the drain/source region is created by impurity diffusion oxidation in the next process. ) region was separated into two regions, but in the present invention, as shown in FIG. It is electrically insulated from each diffusion layer region by the element. Therefore, in the present invention, the gate electrode of the transistor can be taken out from any direction, which can contribute to improving the degree of integration of monolithic semiconductor integrated circuits.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views at each step of manufacturing a silicon gate field effect transistor according to an embodiment of the present invention, and FIGS. 1A' to C' are sectional views of FIGS.
It is a top view corresponding to ~C. FIGS. 2A to 2G are cross-sectional views in the order of steps for explaining another embodiment of the present invention, and FIG. 2E' is a plan view corresponding to FIG. 2E. 3 and 4 are plan views for explaining the advantages of the present invention, and in particular, FIG. 4 shows the diffusion layer region. 1, 10... Semiconductor substrate, 2, 11... Insulating film, 13... Silicon nitride film.

Claims (1)

[Claims] 1. A step of forming an insulating film and a gate insulating film on one principal plane of a semiconductor substrate of one conductivity type, and a step of forming a film to become a gate electrode on the gate insulating film.
removing the insulating film using the gate electrode as a mask to expose the substrate surface; and infiltrating impurities of opposite conductivity type into the substrate from the exposed portion to form drain and source regions of opposite conductivity type in the substrate. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.