JPH07245339A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which a gate wiring layer can be formed with high precision the element area of a MOS transistor and its manufacturing method. CONSTITUTION:An element separating insulating film 2 is formed on a silicon substrate 1 and a single-crystal silicon layer 10 is formed on an element area by selective epitaxial growth so that the upper surface of the silicon layer 10 can become higher than the upper surface of the insulating film 2. Therefore, the over exposure of the element area to the reflected light of exposing light rays from the edge section of the insulating film 2 can be prevented when a photoengraving process is performed at the time of forming a gate wiring layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure in a MOS transistor portion and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the recent trend toward higher integration and miniaturization of semiconductor devices, what has never been a problem has become a serious problem. Since various problems have occurred especially in highly integrated MOS transistors, we are looking forward to future research and development.

FIG. 10 is a sectional view showing the structure of a conventional MOS transistor. In the figure, 1 is a silicon substrate which is a semiconductor substrate, 2 is an insulating film for element isolation, 3 is a gate oxide film, 4 and 5 are gate electrodes and their wiring layers, respectively, a polysilicon film and a refractory metal silicide. 6 is a source / drain region. As can be seen from the figure, the upper surface of the element isolation insulating film 2 formed by the LOCOS method has a gate oxide film 3, a polysilicon film 4, and a silicon in an element region where a gate wiring layer 9 made of a refractory metal silicide film 5 is formed. Upper surface 1a of substrate 1
Is formed higher than.

FIG. 11 is a sectional view showing one step of a conventional method of manufacturing a gate wiring layer of a MOS transistor. As shown in the figure, a part of the silicon substrate 1 is oxidized by the LOCOS method to form an element isolation insulating film 2, a gate oxide film 3, a polysilicon film 4, and a refractory metal silicide film 5 are sequentially formed, and then a resist 7 is formed. Is applied, and a pattern is printed on the resist 7 by irradiating it with a light beam 8 and developed to form a resist pattern for gate wiring.

At this time, since the upper surface of the element isolation insulating film 2 is formed higher than the upper surface 1a of the silicon substrate 1, the polysilicon film 4, the refractory metal silicide film 5 and the resist 7 formed thereon are also elements. A step is generated between the upper portion of the isolation insulating film 2 and the upper portion of the silicon substrate 1. Therefore, the light beam 8 at the time of exposure in the photomechanical process is resist 7
On the silicide film 5 on the edge 2a of the element isolation insulating film 2, the light beam 8 is reflected toward the element region side and the exposure amount to the resist 7 is increased by the reflected light. It can be finely cut or become thick.
Thereafter, development and etching are performed to form the gate wiring layer 9 of FIG.

12 and 13 are plan views of FIG.
FIG. 12 shows the case where a positive type resist is used for the resist 7, and as shown in the figure, the gate wiring layer 9 has a narrow constriction 9a on the element region. Further, FIG. 13 shows a case where a negative type resist is used for the resist 7. As shown in the figure, the gate wiring layer 9 has a thick protruding portion 9a on the element region, contrary to the case of the positive type resist.

[0007]

Since the conventional semiconductor device is constructed as described above, the light beam 8 is reflected on the edge portion 2a of the element isolation insulating film 2 to the element region side during exposure in the photolithography process. As a result, the resist width is partially changed, and as shown in FIGS. 12 and 13, the processing accuracy of the gate wiring layer 9 after etching is lowered.

As shown in FIG. 12, when the gate wiring layer 9 has a thin constricted portion 9a on the element region, the channel length is shortened at that portion and the isolation breakdown voltage between the source and drain is lowered, resulting in the reliability of the transistor. Will be reduced. On the contrary, as shown in FIG. 13, when the gate wiring layer 9 has a thick protruding portion 9a on the element region, the channel length becomes long at that portion, the channel resistance becomes high, and the drain current is lowered, so that There was a problem that performance was lowered.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which a gate wiring on an element region can be accurately processed, and a manufacturing method thereof.

[0010]

[Means for Solving the Problems] Claim 1 according to the present invention
In this semiconductor device, the upper surface of the element region is formed higher than the upper surface of the element isolation insulating film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming an element isolation insulating film on a semiconductor substrate by a LOCOS method, and a step of forming an element region isolated by the element isolation insulating film. And a step of forming a silicon single crystal layer so that the upper surface of the element isolation insulating film is higher than the upper surface thereof.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming an insulating film on the entire surface of a semiconductor substrate, and a part of the insulating film is removed by etching to form an element isolation insulating film and an element. And a step of forming a silicon single crystal layer in the element region such that the upper surface of the element isolation insulating film is higher than the upper surface of the element isolation insulating film.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming an element isolation insulating film on a semiconductor substrate by a LOCOS method, and the step of etching the element isolation insulating film to form an upper surface of the element isolation insulating film is performed. And a step of forming the semiconductor substrate lower than the upper surface of the semiconductor substrate.

Further, according to a fifth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of etching a semiconductor substrate to form a groove in the semiconductor substrate, and a step of forming an insulating film on the entire surface including the inside of the groove. And a step of etching the insulating film to form an element isolation insulating film whose upper surface is lower than the upper surface of the semiconductor substrate.

[0015]

In the semiconductor device according to the present invention, since the upper surface of the element region is formed higher than the upper surface of the element isolation insulating film,
It is possible to prevent reflection of light toward the element region at the edge portion of the element isolation insulating film and prevent overexposure in the element region.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming an element isolation insulating film on a semiconductor substrate by a LOCOS method and a step of forming the element isolation insulating film on an element region separated by the element isolation insulating film. Since the step of forming the silicon single crystal layer so that the upper surface is higher than the upper surface is provided, it is possible to prevent reflection of light at the element isolation insulating film edge portion toward the element region side, and to prevent the over-reflection in the element region. Exposure can be prevented.

Further, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of removing a part of the insulating film by etching to form an element isolation insulating film and an element region, and the element isolation insulating film in the element region. Since the step of forming a silicon single crystal layer so that its upper surface is higher than the film upper surface is provided, it is possible to prevent reflection of light at the element isolation insulating film edge portion toward the element region side, and Overexposure can be prevented.

Since the device isolation insulating film is formed on the semiconductor substrate by the LOCOS method, the device isolation insulating film is etched so that its upper surface is lower than the upper surface of the semiconductor substrate. It is possible to prevent reflection of light at the edge portion of the element isolation insulating film toward the element region side and prevent overexposure in the element region.

Further, the step of etching the semiconductor substrate to form a groove in the semiconductor substrate, the step of forming an insulating film on the entire surface including the inside of the groove, and the step of etching the insulating film to make the upper surface of the semiconductor Since the step of forming the element isolation insulating film lower than the upper surface of the substrate is provided, it is possible to prevent reflection of light at the edge portion of the element isolation insulating film toward the element region side and prevent overexposure in the element region.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 is a sectional view showing the structure of a MOS transistor of the present invention. In the figure, 1 is a silicon substrate which is a semiconductor substrate, 2 is an element isolation insulating film, 3 is a gate oxide film, 4 is a polysilicon film, 5 is a refractory metal silicide film, 6 is a source / drain region, and gate is a gate. The gate wiring layer 9 is formed of the oxide film 3, the polysilicon film 4, and the refractory metal silicide film 5.

Next, a method of manufacturing the gate wiring layer of the MOS transistor shown in FIG. 1 will be sequentially described with reference to FIGS. First, in FIG. 2, the LOCOS is performed in the same manner as the conventional example.
The element isolation insulating film 2 is formed by oxidizing a part of the silicon substrate 1 by the method.

Next, as shown in FIG. 3, the silicon single crystal layer 10 is selectively formed only on the surface of the silicon substrate 1 which is the element region.
Are epitaxially grown to form the upper surface of the silicon single crystal layer 10 higher than the upper surface of the element isolation insulating film 2. This selective epitaxial growth is carried out by a CVD method using a mixture of SiH ₄ or SiH ₂ Cl ₂ and HCl in a gas of about 800-9.
It is carried out by thermal decomposition at a temperature of 00 ° C.

Next, as shown in FIG. 4, a gate oxide film 3, a polysilicon film 4, and a refractory metal silicide film 5 are sequentially formed on the entire surface, a resist 7 is applied, and a photolithography process is performed. At this time, since the upper surface of the silicon single crystal layer 10 is formed higher than the upper surface of the element isolation insulating film 2, a step is formed at the shoulder portion 10a of the silicon single crystal layer. At the time of exposure, the light beam 8 is emitted from the shoulder portion 10a of the silicon single crystal layer.
Although the reflected light is reflected to the element isolation insulating film 2 side above and the exposure amount of the resist 7 on the element isolation insulating film 2 is increased by the reflected light, it is not reflected to the element region side. Then, development and etching are performed to form the gate wiring layer 9 shown in FIG.

5 and 6 are plan views of FIG. 5 shows the case where a positive type resist is used for the resist 7, and FIG. 6 shows the case where a negative type resist is used. As shown in FIGS. 5 and 6, the thin constricted portion 9a and the thick protruding portion 9a in the gate wiring layer 9 are not on the element region but on the element isolation insulating film 2
Since it is formed above, the performance and reliability of the MOS transistor are not deteriorated.

Example 2. In the first embodiment, the LOC
Although the case where the element isolation insulating film 2 is formed by the OS method is shown, the insulating film 11 made of an oxide film or a nitride film is formed on the entire surface of the silicon substrate 1 as shown in FIG. As shown in b), the insulating film 11 on the element region may be removed by etching to form the element isolation insulating film 2. After that, as shown in FIG. 7C, the silicon single crystal layer 10 may be selectively epitaxially grown on the element region until it becomes higher than the upper surface of the element isolation insulating film 2 in the same manner as in FIG. Also in this case, the same effect as that of the first embodiment is obtained.

Example 3. In the first embodiment, the LOC
The case where the silicon single crystal layer 10 is selectively epitaxially grown on the silicon substrate 1 in the element region after the element isolation insulating film 2 is formed by the OS method is shown in FIG.
As shown in FIG. 8A, the element isolation insulating film 2 is formed by the LOCOS method in the same manner as in FIG. 2, and then the element isolation insulating film 2 is entirely etched as shown in FIG. The upper surface of the film 2 may be formed lower than the upper surface of the silicon substrate 1. Also in this case, the same effect as that of the first embodiment is obtained.

Example 4. Further, in the above-mentioned third embodiment, the LOC
The case where the upper surface of the element isolation insulating film 2 is formed lower than the upper surface of the silicide substrate 1 by etching the entire surface of the element isolation insulating film 2 formed by the OS method has been described. However, as shown in FIG. It can be formed in the same manner. First, a part of the silicon substrate 1 is etched to form a groove in the silicon substrate 1 (FIG. 9).
(A)). Next, an insulating film 12 such as an oxide film or a nitride film is deposited on the entire surface (FIG. 9B). Thereafter, the insulating film 12 is entirely etched to form the element isolation insulating film 2. At this time, the entire surface is etched until the upper surface of the element isolation insulating film 2 becomes lower than the upper surface of the silicon substrate 1 (FIG. 9).
(C)). Also in this case, the same effect as that of the first embodiment is obtained.

[0028]

As described above, according to the present invention, since the upper surface of the element region is formed higher than the upper surface of the element isolation insulating film, reflection at the edge of the element isolation insulating film to the element region side can be prevented. Overexposure in the inside can be prevented, and the gate wiring layer in the element region can be accurately formed.

In the method of manufacturing a semiconductor device according to the present invention, the element isolation insulating film is formed on the semiconductor substrate by the LOCOS method, and the element isolation insulating film is formed on the element region isolated by the element isolation insulating film. Since it has a step of forming a silicon single crystal layer so that its upper surface is higher than its upper surface, reflection on the element region side at the element isolation insulating film edge can be prevented and overexposure in the element region can be prevented. Therefore, the gate wiring layer in the element region can be accurately formed.

Further, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of etching away a part of the insulating film to form an element isolation insulating film and an element region, and the element isolation insulating film in the element region. Since the step of forming a silicon single crystal layer so that its upper surface is higher than the film upper surface is provided, reflection on the element region side at the element isolation insulating film edge portion can be prevented and overexposure in the element region can be prevented. This can be prevented, and the gate wiring layer in the element region can be formed with high accuracy.

Since the device isolation insulating film is formed on the semiconductor substrate by the LOCOS method, the device isolation insulating film is etched to form the upper surface thereof lower than the upper surface of the semiconductor substrate. In addition, it is possible to prevent reflection on the element region side at the edge portion of the element isolation insulating film, prevent overexposure in the element region, and accurately form the gate wiring layer in the element region.

Further, the step of etching the semiconductor substrate to form a groove in the semiconductor substrate, the step of forming an insulating film on the entire surface including the inside of the groove, and the step of etching the insulating film to make the upper surface of the semiconductor substrate Since it is provided with a step of forming an element isolation insulating film lower than the upper surface, it is possible to prevent reflection to the element region side at the edge portion of the element isolation insulating film and prevent overexposure in the element region, The gate wiring layer can be accurately formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a MOS transistor of the present invention.

FIG. 2 is a cross-sectional view showing a step in the method of forming the gate wiring layer according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step in the method of forming the gate wiring layer according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step in the method of forming the gate wiring layer according to the first embodiment of the present invention.

5 is a plan view of the MOS transistor of FIG. 1. FIG.

FIG. 6 is a plan view of the MOS transistor of FIG.

FIG. 7 is a process sectional view of Embodiment 2 of the present invention.

FIG. 8 is a process sectional view of Embodiment 3 of the present invention.

FIG. 9 is a process sectional view of Embodiment 4 of the present invention.

FIG. 10 is a sectional view showing the structure of a conventional MOS transistor.

FIG. 11 is a cross-sectional view showing a step in the conventional method for manufacturing a MOS transistor.

FIG. 12 is a plan view of a conventional MOS transistor.

FIG. 13 is a plan view of a conventional MOS transistor.

[Explanation of symbols]

 1 Silicon substrate which is a semiconductor substrate 2 Element isolation insulating film 3 Gate oxide film 4 Polysilicon film 5 Refractory metal silicide film 9 Gate wiring layer 10 Silicon single crystal layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication 7514-4M H01L 29/78 301 G 7514-4M 301 X

Claims (5)

[Claims] 1. A semiconductor device in which an element isolation insulating film is formed on a semiconductor substrate, and a gate wiring layer is formed on an element region separated by the element isolation insulating film, wherein the element region upper surface is the element isolation insulating film. A semiconductor device characterized in that it is formed higher than the upper surface. 2. A step of forming an element isolation insulating film on a semiconductor substrate by a LOCOS method, and an upper surface of the element isolation insulating film higher than an upper surface of the element isolation insulating film on an element region isolated by the element isolation insulating film. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicon single crystal layer. 3. A step of forming an insulating film on the entire surface of a semiconductor substrate, a step of etching away a part of the insulating film to form an element isolation insulating film and an element region, and the element isolation in the element region. Forming the silicon single crystal layer so that the upper surface of the insulating film is higher than the upper surface of the insulating film.
A method for manufacturing a semiconductor device as described above. 4. A step of forming an element isolation insulating film on a semiconductor substrate by a LOCOS method, and a step of etching the element isolation insulating film to form an upper surface thereof lower than an upper surface of the semiconductor substrate. 1. The method for manufacturing a semiconductor device according to 1. 5. A step of etching a semiconductor substrate to form a groove in the semiconductor substrate, a step of forming an insulating film over the entire surface including the inside of the groove, and the step of etching the insulating film so that the upper surface of the semiconductor film is the semiconductor. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming an element isolation insulating film lower than the upper surface of the substrate.