JPS60113473A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60113473A JPS60113473A JP22110883A JP22110883A JPS60113473A JP S60113473 A JPS60113473 A JP S60113473A JP 22110883 A JP22110883 A JP 22110883A JP 22110883 A JP22110883 A JP 22110883A JP S60113473 A JPS60113473 A JP S60113473A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- semiconductor device
- mask
- gate electrode
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000470 constituent Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はマスクパターンを介してエツチングを施して
半導体装置を製作する方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device by etching through a mask pattern.
以下、MOSトランジスタ(MO8T)を製造する場合
を例にとって説明する。The following will explain the case of manufacturing a MOS transistor (MO8T) as an example.
第1図は従来のMO8Tの製造に当ってのゲートの作成
段階を示す断面図で、第2図はその平面図である。シリ
コン基板(1)の素子形成領域を囲むように、フィール
ド酸化膜(2)を形成し、これに囲まれたシリコン基板
(1)の表面部に互いに所要距離へだてでソース(3)
およびドレイン(4)を形成し、その上を含めてシリコ
ン基板(1)の上にゲート酸化膜(5)を形成し、更に
その上にゲート電極となるべきポリシリコン層(6)を
形成した後に、このポリシリコン層(6)にエツチング
を施してゲート電極を形成するためのホトレジストマス
ク(7)を形成する。FIG. 1 is a sectional view showing the steps of forming a gate in manufacturing a conventional MO8T, and FIG. 2 is a plan view thereof. A field oxide film (2) is formed so as to surround the element formation region of the silicon substrate (1), and sources (3) are formed on the surface of the silicon substrate (1) surrounded by this film at a required distance from each other.
A gate oxide film (5) was formed on the silicon substrate (1) including the drain (4), and a polysilicon layer (6) to become a gate electrode was further formed on the gate oxide film (5). Later, this polysilicon layer (6) is etched to form a photoresist mask (7) for forming a gate electrode.
とのホトレジストマスク(7)の形成方法は周知のよう
にポリシリコン層(6)の上全面にホトレジスト膜を被
着させ、これに所要パターンのマスクlI−して露光、
現像を施し、上記マスクと同一パターンのホトレジスト
マスク(力が得られる。As is well known, the method for forming the photoresist mask (7) is to deposit a photoresist film on the entire surface of the polysilicon layer (6), and then expose it to light using a mask of a desired pattern.
After development, a photoresist mask with the same pattern as the above mask (power can be obtained).
このホトレジストマスク(7)を介してポリシリコン層
(6)にエツチングを施して第3図に平面図を示すよう
に、ゲート電極(6a)を形成してMO8Tは完成する
。勿論、ソース(3)およびドレイン(4)は、このゲ
ート電極(6a)を形成後、その直下以外の部分のゲー
ト酸化膜(5)を除去し、その上で不純物を拡散させて
形成する方法もある。The MO8T is completed by etching the polysilicon layer (6) through this photoresist mask (7) to form a gate electrode (6a) as shown in the plan view of FIG. Of course, the source (3) and drain (4) are formed by forming the gate electrode (6a), removing the gate oxide film (5) other than directly below it, and then diffusing impurities thereon. There is also.
さて、このような従来の方法ではホトレジストマスク(
7)を介してポリシリコン層(6)にエツチングを施す
際に、オーバーエツチングなどにより、第3図に示すよ
うにゲート電極(6a)の端部において、マスクパター
ンより細くなり、その影響がチャネル領域まで及び、こ
の部分のゲート長が短くなる。Now, in this conventional method, a photoresist mask (
When etching the polysilicon layer (6) through the polysilicon layer (6), the edge of the gate electrode (6a) becomes thinner than the mask pattern as shown in FIG. The gate length in this area is shortened.
第4図はこの点を避ける従来の方法を示す平面図で、ゲ
ート電極を形成すべきホトレジストマスクをMO8Tの
チャネル領域を大幅に越えて延ばしておいて、その端部
においてポリシリコン層(6)にオーバーエツチングが
生じても、その影響がチャネル領域に及ばないようにし
たものであるが、この方法では、図示のようにMO8T
を形成するためのウェーハ上の面積が大きくなるという
問題点がある。FIG. 4 is a plan view showing a conventional method to avoid this problem, in which the photoresist mask in which the gate electrode is to be formed is extended far beyond the channel region of the MO8T, and at its end a polysilicon layer (6) is formed. This method is designed to prevent overetching from affecting the channel region even if overetching occurs in the MO8T as shown in the figure.
There is a problem that the area on the wafer for forming the wafer becomes large.
この発明は以上のような点に鑑みてなされたもので、オ
ーバーエツチングによって端部が細くなるウェーハ面積
を大きくすることなく、所要幅のパターンを所要部分に
形成できる半導体装置の製造方法を提供するものである
。This invention has been made in view of the above points, and provides a method for manufacturing a semiconductor device that can form a pattern of a desired width in a desired portion without increasing the area of the wafer whose edges become thin due to overetching. It is something.
第5図はこの発明の一実施例のエツチングマスク形成段
階の状況を示す平面図で、従来例と同一符号は同等部分
を示す0この実施例ではポリシリコン層(6)をエツチ
ングしてゲート電極を形成すべきホトレジストマスク(
7)を図示のようにその端部において幅を広くしておい
て、ゲート電極の端部テノオーバーエッチングによる細
りを補償することによって、形成されたゲート電極のゲ
ート長が短くなるのを防ぐことができる。FIG. 5 is a plan view showing the stage of forming an etching mask according to an embodiment of the present invention, in which the same reference numerals as in the conventional example indicate the same parts. In this embodiment, the polysilicon layer (6) is etched to form the gate electrode. A photoresist mask (
7) Prevent the gate length of the formed gate electrode from becoming short by widening the width at the end as shown in the figure and compensating for the thinning caused by teno-over etching at the end of the gate electrode. I can do it.
なお、上記実施例ではMO8Tのゲート電極形成の場合
について説明したが、他の半導体装置における配線の形
成にもこの発明を適用できる。In the above embodiment, the case of forming a MO8T gate electrode has been described, but the present invention can also be applied to forming wiring in other semiconductor devices.
以上説明したように、この発明では所要パターンのマス
クを介してエツチングを施してその部分を形成する半導
体装置の製造方法において、そのパターンの端部におけ
る幅を広くしたので、当該部分を必要以上に長くするこ
となく、エツチング時の端部の細シを補償して、当該部
分を所要幅に形成することができる。As explained above, in the present invention, in the method of manufacturing a semiconductor device in which a portion is formed by etching through a mask having a desired pattern, the width at the end of the pattern is made wider, so that the portion is made larger than necessary. It is possible to compensate for the thinning of the end portion during etching and form the portion to the required width without increasing the length.
第1図は従来のMO8Tの製造に商ってのゲートの作成
段階を示す断面図、第2図はその平面図、第3図は従来
方法によるゲート電極の形成状況を示す平面図、第4図
は従来の改良された方法におけるエツチングマスク形成
段階を示す平面図、第5図はこの発明の一実施例のエツ
チングマスク形成段階を示す平面図である。
図において、(6)はポリシリコン層、(6a)はゲー
ト電極、(7)はホトレジストマスクである。
なお、図中同一符号は同一または相当部分を示す0
代理人 大岩増雄
N ’>4
昭和 年 汀プへ日
特許庁長官殿
1、事件の表示 特願昭58−221108号2、発明
の名称 半導体装置の製造方法3、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号名 称
(601)三菱電機株式会社
代表者片山仁八部
4、代理人
住 所 東京都千代田区丸の内二丁目2番3号王の対象
凶圓
6、補正の内容
(1)図面の第1図、第2図、第4図および第5図を添
付図の通りに訂正する。
7、添付書類の目録
訂正後の第1図、第2図、第尋図および第5図を示す図
面 1通
以上FIG. 1 is a cross-sectional view showing the steps of forming a gate in the conventional MO8T manufacturing process, FIG. 2 is a plan view thereof, FIG. This figure is a plan view showing the step of forming an etching mask in a conventional improved method, and FIG. 5 is a plan view showing the step of forming an etching mask in an embodiment of the present invention. In the figure, (6) is a polysilicon layer, (6a) is a gate electrode, and (7) is a photoresist mask. Note that the same reference numerals in the drawings indicate the same or equivalent parts.0 Agent: Masuo Oiwa N'>4 Showa year: To the Commissioner of the Japan Patent Office1, Indication of case: Japanese Patent Application No. 58-2211082, Title of invention: Semiconductor Device manufacturing method 3, relationship with the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama Hachibu 4, Agent Address 2-2-3 Marunouchi 2-chome, Chiyoda-ku, Tokyo Target Kakuen 6, Contents of Amendment (1) Figures 1 and 1 of the drawings Figures 2, 4, and 5 are corrected as shown in the attached figures. 7. One or more drawings showing Figure 1, Figure 2, Figure 5, and Figure 5 after the catalog of attached documents has been corrected.
Claims (3)
て所要幅のその構成部分を形成する工程を有する半導体
装置の製造方法において、上記マスクのパターンをその
端部近傍において上記所要幅より幅を広くすることを特
徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device, which includes a step of etching through a mask having a desired pattern to form a constituent portion thereof having a desired width, the pattern of the mask is made wider than the required width near the end thereof. A method for manufacturing a semiconductor device, characterized in that:
ングによって形成するその構成部分がゲート電極である
ととを特徴とする特許請求の範囲第1項記載の半導体装
置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an MO8 type semiconductor device, and the component formed by etching is a gate electrode.
とする特許請求の範囲第1項または第2項記載の半導体
装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the mask is a photoresist mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22110883A JPS60113473A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22110883A JPS60113473A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60113473A true JPS60113473A (en) | 1985-06-19 |
Family
ID=16761606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22110883A Pending JPS60113473A (en) | 1983-11-22 | 1983-11-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60113473A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6286762A (en) * | 1985-10-11 | 1987-04-21 | Sony Corp | Manufacture of mos field effect transistor |
JPH0212823A (en) * | 1988-06-30 | 1990-01-17 | Seiko Epson Corp | Semiconductor device |
-
1983
- 1983-11-22 JP JP22110883A patent/JPS60113473A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6286762A (en) * | 1985-10-11 | 1987-04-21 | Sony Corp | Manufacture of mos field effect transistor |
JPH0212823A (en) * | 1988-06-30 | 1990-01-17 | Seiko Epson Corp | Semiconductor device |
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