JPS6211514B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device having self-aligned contact holes, and in particular to a method for manufacturing a MOS type FET using a silicon local oxidation process.
The present invention relates to a manufacturing method suitable for integrated circuit devices such as the above.

In a semiconductor device that integrates a large number of MOS FETs, when connecting metal wiring to the drain, source, and diffusion wiring regions formed with impurities of the opposite conductivity type to the substrate, a silicon oxide film covering these regions is used. A method is used in which a contact hole is formed in a predetermined portion of the semiconductor device by photolithography to expose a diffusion region, and then a metal wiring is connected. In such a conventional contact hole forming method, when mask dimensional accuracy, overetching, and alignment accuracy are taken into consideration, it is necessary to provide a large margin for the size of the diffusion layer and the contact hole on the mask. Particularly when using a local oxidation process, the width of the diffusion layer is narrowed when forming the field silicon oxide film (approximately 1 μm), so the distance between one side of the contact hole and one side of the diffusion layer is 400 mm on the mask.
Requires μ. Also, due to the difficulty of developing technology, negative type photoresists are generally used rather than positive types, but in the latter case, the light is reflected during exposure and is reflected from the silicon oxide film, so if the contact hole is made smaller, the contact This causes holes to fail to come out, and currently 5.
The minimum value is μ×5μ. Therefore, the size of the diffusion layer forming the contact hole is at least 12μ. 3
When one bit is composed of transistors, the number of contacts in a 4K-bit memory is nearly 10,000, and the size of the contacts and the margin with the diffusion layer have an extremely large effect on the degree of integration.

Therefore, it is an object of the present invention to have a small contact hole, a small margin for the impurity region, and
It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device with a simplified manufacturing process and high reliability.

The present invention is characterized in that a portion of a silicon substrate of one conductivity type that corresponds to the contact hole is covered with an insulating film that is inactive against thermal oxidation, an impurity of the opposite conductivity type is introduced into the silicon substrate through the insulating film, and then an impurity of the opposite conductivity type is introduced into the silicon substrate through the insulating film. A silicon oxide film is formed by thermal oxidation using the insulating film as a mask, and at the same time, this thermal oxidation step diffuses the impurity of the opposite conductivity type into the substrate to form an impurity region of the opposite conductivity type. The present invention provides a method of manufacturing a semiconductor integrated circuit device in which a self-aligned contact hole is formed by removing the silicon nitride film whose side surfaces are covered.

Since a film inactive against thermal oxidation, such as a silicon nitride film, is provided only in the contact area in this way, an integrated circuit device with a high degree of integration can be obtained.
In addition, since the introduction and diffusion of impurities of the opposite conductivity type is carried out with the mask insulating film attached without removing it, unlike the case where, for example, ion implantation is performed and forced diffusion is performed while the substrate is exposed, crystal Surface contamination can be prevented without causing drooling. Moreover, since the formation of the surrounding silicon oxide film and the formation of the impurity region by diffusion of the introduced impurity are performed in the same heat treatment step, the method is simplified as a whole and has high productivity.

Next, in order to better understand the present invention, examples will be described using drawings.

Referring to FIGS. 1A to 1D, in the technology related to the present invention, a high impurity concentration region 12 of the conductivity type opposite to that of the substrate 11 exists between the field silicon oxide films 10, and a method for making contact therewith. It shows. That is, while leaving a predetermined portion of the silicon nitride film 13, an impurity of the same conductivity type as the substrate 11 is diffused and oxidized onto the starting substrate (FIG. 1A).
The impurity 14, which has conductivity opposite to that of the substrate, is ionized. The high concentration region 12 is formed by implantation (FIG. 1B) and pressing at high temperature (FIG. 1C). Next, after removing the silicon nitride film 13 by etching with hot phosphoric acid, a metal wiring 15 is provided. This method makes it possible to form contact holes only in the remaining portion of the silicon nitride film.

Referring to FIGS. 2A to 2G, the embodiment of the present invention uses the starting substrate of FIG. 2A obtained by the same method as that of FIG. 1, and as shown in FIG. After leaving 13, a gate oxide film 16 and a polysilicon layer are grown on the surface without the silicon nitride film. Thereafter, as shown in FIG. 2C, a gate electrode is formed by leaving polysilicon 17 only in the part that will become the gate electrode, and then the silicon nitride film is removed by photolithography except in the part where it is necessary to make a contact hole. After that (FIG. 2D), an impurity 18 of a conductivity type opposite to that of the substrate is implanted at a high concentration (FIG. 2E), and oxidation is performed. As a result, areas other than the silicon nitride film are covered with the silicon oxide film 19, and at the same time, source and drain regions 20 of the opposite conductivity type to the substrate are formed (FIG. 2F). Thereafter, only the silicon nitride film is etched away by immersion in a hot phosphoric acid solution, and the metal wiring 21 is made in contact with the common source or drain of the two MOS transistors as shown in FIG. 2G. The structure is completed.

As shown in Figure 1, for a structure in which the contact hole is surrounded by a field silicon oxide film,
Conventional self-aligned contact formation methods utilize the difference in thickness between the field silicon oxide film and the silicon oxide film on the high concentration area to use a contact hole that is larger than the high concentration area on the mask. A contact method is known. However, if the gate electrode 17 is adjacent to the high concentration region 20 as shown in the embodiment of FIG. 2 and it is necessary to contact the metal wiring to the high concentration region, the silicon oxide film surrounding the polysilicon film 17 may Since there is no difference between the thickness of the area 19 and that of the high concentration area 20, the outer punching method cannot be used and the present invention is effective. As mentioned above, the conventional contact forming method is to make a contact hole in a silicon oxide film, and when a positive type photoresist is used, the size of the contact hole on the mask is limited to 5 μm, but in this example, the contact hole size is limited to 5μ. Because of the structure in which the nitride film remains, 3μ can be fully realized. Furthermore, with regard to over-etching, in contrast to the conventional method in which the contact hole widens, in the embodiment of the present invention, the contact hole becomes smaller, so that the relationship between the gate insulating film 16 and the gate electrode 17 shown in FIG. As for the edge difference 23, it is sufficient to consider only the margin of alignment, and 1 μ is sufficient. Therefore, the high concentration region with contacts has a thickness of 5μ.
That's enough.

FIG. 3 shows a case in which a phosphor glass film 24 is further grown on the contact hole and the silicon oxide film 19 in order to reduce the capacitance between the polysilicon 17 and the aluminum gate or aluminum wiring layer 21 in the embodiment shown in FIG. This figure shows how to make the contact hole in Figure 3A), where the phosphor glass film 24 and the silicon oxide film 1
By utilizing the difference in etching speed of 9,
As shown in FIG. 3B, the above-mentioned external contact method becomes possible.

As shown in the above embodiments, contact holes adjacent to either the field silicon oxide film or the polysilicon gate or wiring can be self-aligned.

Although the above explanation was made using a silicon nitride film, it is also possible to replace this with another heat-resistant oxide film such as an aluminum oxide film. Taking advantage of the fact that impurities such as boron can pass through, a diffusion method can be used instead of the implantation in the embodiment of FIG.

[Brief explanation of the drawing]

FIGS. 1A to 1D are cross-sectional views of each step of the technology related to the present invention, FIGS. 2A to G are sectional views of each step of the embodiment of the present invention, and FIGS. 3A and B are
FIG. 7 is a sectional view of a modification of the illustrated embodiment; 13: Silicon nitride film, 11: One conductivity type silicon substrate, 10, 16, 19: Silicon oxide film, 1
2, 20: opposite conductivity type region, 17: silicon. gate electrode.

Claims (1)

[Claims] 1. A step of forming an insulating film that is inactive against thermal oxidation on an element formation region adjacent to the field silicon oxide film of a silicon substrate of one conductivity type on which a thick field silicon oxide film is formed, and selectively removing the first and second portions in contact with the field silicon oxide film and a third portion located at the center; forming a gate oxide film on the surface of the silicon substrate between the second and third portions; forming a polysilicon gate electrode on the gate oxide film; After removing the portion, introducing an impurity of the opposite conductivity type into a portion of the silicon substrate between the gate electrode and between the gate electrode and the field silicon oxide film, including under the third portion of the remaining insulating film; Next, thermal oxidation is performed using the third portion of the insulating film as a mask to form a silicon oxide film adjacent to the periphery of the third portion of the insulating film, and at the same time, the reverse conductivity introduced into the silicon substrate is removed. This thermal oxidation diffuses type impurities deep into the substrate to form a source or drain region of opposite conductivity type extending from below the third portion of the insulating film to the periphery of the third portion of the insulating film. The silicon formed by the thermal oxidation is removed by forming a source or drain region of opposite conductivity type in the silicon substrate in between, and then by removing the third portion of the insulating film. a step of exposing the surface of the contact portion of the source or drain region of the opposite conductivity type whose both ends are adjacent to the oxide film, and coating the contact portion over the entire surface area between the both ends of the contact portion and forming a contact portion on each of the both ends. a step of forming a wiring layer for the source or drain region so as to partially overlap the gate electrodes by extending over adjacent portions of the silicon oxide film. A method of manufacturing a circuit device.