JPH0653519A - Semiconductor non-volatile memory and fabrication thereof - Google Patents

Abstract

PURPOSE:To fabricate a MONOS memory exhibiting reliable read out operation by forming a memory gate electrode film at least in an element region smaller than a memory nitride film in the element region. CONSTITUTION:A memory nitride film 5 and a tunnel oxide film 3 are removed selectively through etching and a semiconductor substrate 1 is thermally oxidized thus forming the gate oxide film 11 of MOS transistor for peripheral circuit. Gate electrode material is formed on the film and then a resist pattern is formed thereon through exposure and developing. At that time, resist pattern is set smaller than a pattern of a top oxide film 7, a memory nitride film 5, and the tunnel oxide film 3. A memory gate electrode film 9 and a gate electrode film 13 for MOS transistor constituting a peripheral circuit are then formed by the use of the resist through etching. The memory gate electrode film 9 is formed smaller than the memory nitride film 5 in order to eliminate positional shift of an aligner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory gate electrode
The present invention relates to a configuration of a semiconductor non-volatile memory having a MONOS structure including a top oxide film-memory nitride film-tunnel oxide film-semiconductor substrate structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A semiconductor non-volatile memory having a MONOS structure (hereinafter referred to as MONOS memory) has high reliability,
Since it can be rewritten a great number of times, it has recently attracted particular attention.

This MONOS memory comprises a semiconductor substrate, a tunnel oxide film, a memory nitride film, a top oxide film and a memory gate electrode film. In the conventional MONOS memory, at least in the element region, the top oxide film, the memory nitride film, the tunnel oxide film, and the memory gate electrode film are formed with the same pattern size.

A MONO in a conventional example will be described below with reference to the drawings.
The configuration of the S memory will be described. FIG. 10 shows a conventional MONO.
It is sectional drawing which shows the structure of S memory. However, FIG. 10 shows only the vicinity of the gate of the MONOS memory in the element region and the vicinity of the gate of the MOS transistor forming the peripheral circuit, and detailed description of the connection with the metal wiring is omitted. To do.

As shown in FIG. 10, as a MONOS memory, a tunnel oxide film 3 having the same pattern dimension and a memory nitride film 5 are formed on a semiconductor substrate 1.
And a top oxide film 7 and a memory gate electrode film 9. Further, the semiconductor substrate 1 other than the MONOS memory area
The gate oxide film 11 of the MOS transistor forming the peripheral circuit is formed on the surface of, and the gate electrode film 13 of the MOS transistor is further provided on the gate oxide film 11.

The memory gate electrode film 9 and the gate electrode film 13 of the MOS transistor can be formed in the same process or can be formed in different processes.
In order not to impair the characteristics of the MOS transistor of the peripheral circuit, these memory gate electrode film 9 and M
The gate electrode film 13 of the OS transistor is generally formed in the same step. A method of manufacturing a conventional MONOS memory will be described below with reference to the drawings.

11 to 17 are cross-sectional views showing a method of manufacturing a semiconductor device having a conventional MONOS memory in the order of steps. However, FIGS. 11 to 17 show the steps from the formation of the element isolation region to the step of forming the gate electrode, and detailed description of the steps before and after that is omitted.

First, as shown in FIG. 11, the surface of the semiconductor substrate 1 is thermally oxidized to form a tunnel oxide film 3.

Next, as shown in FIG. 12, a memory nitride film 5 is formed on the tunnel oxide film 3.

Next, as shown in FIG. 13, the memory nitride film 5 is thermally oxidized to form a top oxide film 7 on the memory nitride film 5.

Next, as shown in FIG. 14, the top oxide film 7 is selectively removed by etching using a resist 4, and then the memory nitride film 5 and the tunnel oxide film 3 are selectively etched. Remove.

Next, after removing the resist 4, as shown in FIG. 15, the semiconductor substrate 1 is thermally oxidized to form the gate oxide film 11 of the MOS transistor for the peripheral circuit.

Next, as shown in FIG. 16, a gate electrode film material 15 made of polycrystalline silicon is formed on the entire surface of these films.
To form.

Next, as shown in FIG. 17, the gate electrode film material 15 is selectively removed by etching using the resist 4, and the same material as the top oxide film 7, the memory nitride film 5, the tunnel oxide film 3 and the like is obtained. Size of memory gate electrode film 9
To form. At the same time, the MOS that constitutes the peripheral circuit
The gate electrode film 13 of the transistor is also formed.

The subsequent steps are the same as the steps for manufacturing a semiconductor device having no MONOS memory.

[0016]

The above-mentioned FIG. 10 to FIG.
In the conventional MONOS memory and the manufacturing method thereof as described using FIG. 7, the memory gate electrode film 9 and the constituent films thereunder, that is, the top oxide film 7, the memory nitride film 5, and the tunnel oxide film 3 are the same. Although it has a pattern dimension of the size of, it is not formed by self-alignment. For this reason, the memory gate electrode film 9 is formed at a position slightly displaced from the underlying film.

That is, the memory gate electrode film 9 is formed so that its position is shifted, so that the memory gate electrode film 9 is formed on the gate insulating film 11 of the MOS transistor.

Therefore, either the source side of the MONOS memory,
Alternatively, a structure similar to that of the MOS transistor forming the peripheral circuit is formed on the drain side. Therefore, there is a problem that the misaligned memory gate electrode film 9 and the gate oxide film 11 region of the MOS transistor serve as an offset gate, and the read operation of the MONOS memory becomes uncertain.

An object of the present invention is to solve the above-mentioned problems and to provide a reliable MONOS memory structure for reading operation, and this MONO memory structure.
A manufacturing method for forming a NOS memory.

[0020]

To achieve the above object, the present invention employs the structure and method described below.

The MONOS memory of the present invention is characterized in that at least the memory gate electrode film in the element region is smaller than the pattern size of the memory nitride film in the element region.

A method of manufacturing a MONOS memory according to the present invention comprises a step of thermally oxidizing the surface of a semiconductor substrate to form a tunnel oxide film, a step of forming a memory nitride film on the tunnel oxide film, and a step of forming the memory nitride film. Forming a top oxide film by thermal oxidation of silicon, exposing the semiconductor substrate surface by selectively removing these top oxide film, memory nitride film and tunnel oxide film, and the exposed semiconductor substrate A step of thermally oxidizing the surface to form a gate oxide film; a step of forming a gate electrode film material on the semiconductor substrate on which the gate oxide film is formed; And forming a memory gate electrode film on the film by selectively removing with a pattern size smaller than that of the top oxide film. To.

[0023]

When the gate electrode film material is selectively removed and processed into a desired shape, usually, the resist is first exposed and developed, and the mask pattern is transferred to the resist. After that, using this resist as an etching mask,
A method of etching the gate electrode film material is adopted.

For transferring the mask pattern to the resist,
An alignment device such as a stepper is used, but such an alignment device always has misalignment. Therefore, it is impossible to form a pattern having the same size as the underlying film at the same position.

Therefore, if the underlying film is enlarged in advance by the amount of misalignment of the alignment device, the upper pattern will not be displaced from the position of the underlying film.

In the present invention, the underlying film when processing the gate electrode film material is, firstly, the top oxide film.
Therefore, the pattern size of the resist is made smaller than that of this top oxide film, and the gate electrode film material is selectively removed by etching.

However, since this top oxide film has a film thickness of only about 5 nm, it is etched to the same size as the memory gate electrode film due to over-etching when etching the gate electrode film material.

Therefore, in the final shape, the tunnel oxide film and the memory nitride film have the same size, and the top oxide film and the gate electrode film are larger than the pattern dimensions of these tunnel oxide film and the memory nitride film. A little smaller.

Therefore, in the configuration of the MONOS memory of the present invention, the pattern size of the memory gate electrode film is made smaller than at least the memory nitride film.

[0030]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a MONOS memory of the present invention. However, FIG. 1 shows only the vicinity of the gate of the MONOS memory in the element region and the vicinity of the gate of the MOS transistor forming the peripheral circuit, and detailed description of the connection portion with the metal wiring is omitted. .

First, the configuration of the semiconductor nonvolatile memory of the present invention will be described with reference to FIG. As shown in Figure 1,
On the semiconductor substrate 1, a tunnel oxide film 3 having the same pattern size and a memory nitride film 5 are provided.

On top of that, these tunnel oxide films 3 are formed.
A top oxide film 7 having a pattern size smaller than that of the memory nitride film 5 and a memory gate electrode film 9 are provided.

Further, on the surface of the semiconductor substrate 1 other than the regions where the tunnel oxide film 3 and the memory nitride film 5 are formed, the gate oxide film 1 of the MOS transistor constituting the peripheral circuit is formed.
1 is set. Further, on the gate oxide film 11 of the MOS transistor, the gate electrode film 1 of the MOS transistor is formed.
3 is provided.

In FIG. 1, how much the top oxide film 7 and the memory gate electrode film 9 should be made smaller than the pattern size of the tunnel oxide film 3 and the memory nitride film 5 depends on the memory gate. It depends on the alignment accuracy of the alignment device used when forming the resist pattern on the electrode film 9.

In the current alignment apparatus, it is necessary to expect a misalignment amount of about 0.1 μm.

Therefore, the size of the pattern dimension of the top oxide film 7 and the memory gate electrode film 9 needs to be at least about 0.2 μm smaller than that of the tunnel oxide film 3 and the memory nitride film 5 thereunder. There is.

Next, the MONO in the present invention will be described with reference to the drawings.
An embodiment of the method of manufacturing the S memory will be described in detail. Figure 2
9A to 9D are sectional views showing a method of manufacturing the MONOS memory in the present invention in the order of steps. However, these drawings, like FIG. 1, show only the vicinity of the gate of the MONOS memory in the element region and the vicinity of the gates of the MOS transistors that form the peripheral circuit. Shows the steps from the formation of the element isolation region to the formation of the gate electrode.

First, as shown in FIG. 2, the semiconductor substrate 1 is thermally oxidized to form a tunnel oxide film 3 having a thickness of about 2 nm on the surface of the semiconductor substrate 1.

Next, as shown in FIG. 3, a memory nitride film 5 made of a silicon nitride film having a film thickness of about 10 nm is formed on the tunnel oxide film 3 by using a chemical vapor deposition apparatus.

Next, as shown in FIG. 4, the memory nitride film 5 is thermally oxidized to form a top oxide film 7 having a thickness of 5 nm.

Next, as shown in FIG. 5, the top oxide film 7 is formed by using a resist 4 formed by exposure and development.
Is selectively removed by etching, and then the memory nitride film 5 and the tunnel oxide film 3 are selectively removed by etching.

Next, after removing the resist 4, the semiconductor substrate 1 is subjected to thermal oxidation treatment as shown in FIG.
A gate oxide film 11 of a MOS transistor for peripheral circuits is formed to some extent.

Next, as shown in FIG. 7, a gate electrode film material 15 made of polycrystalline silicon is formed on the entire surface of these films.
With a film thickness of about 400 nm using a chemical vapor deposition apparatus.

Next, as shown in FIG. 8, a pattern of the resist 4 is formed on the gate electrode film material 15 by exposing and developing. At this time, the pattern size of the resist 4 is smaller than the pattern size of the top oxide film 7, the memory nitride film 5, and the tunnel oxide film 3. A resist 4 having a pattern size of a predetermined size as a peripheral circuit is formed on the gate oxide film 11 of the MOS transistor for the peripheral circuit.

Next, as shown in FIG. 9, using this resist 4 as an etching mask, the gate electrode film material 15 is formed.
Are etched to form the memory gate electrode film 9 and the gate electrode film 13 of the MOS transistor forming the peripheral circuit. At that time, the portion of the top oxide film 7 that protrudes from the memory gate electrode film 9 is etched together with the memory gate electrode film 9. This is due to performances such as etching uniformity and etching selection ratio possessed by the current etching apparatus.

In the subsequent steps, the same manufacturing steps as those of the semiconductor device having no MONOS memory may be performed.

By the manufacturing method as described above, M of the present invention can be obtained.
ONOS memory can be manufactured.

In the description of the present invention, as shown in FIG. 1, the top oxide film 7 and the memory gate electrode film 9 have the same size. However, as is clear from the description of the manufacturing method described with reference to FIGS. 2 to 9 above, this is eventually the same due to the performance of the current etching apparatus, and the performance of the etching apparatus in the future. When the memory gate electrode film 9 is formed, the MONOS memory can be formed with the same size as the memory nitride film 5 and the tunnel oxide film 3 without etching the top oxide film 7. Even if it happens, it doesn't matter.

[0049]

As described above, by making the size of the memory gate electrode film of the MONOS memory smaller than at least the memory nitride film below the memory gate electrode film, the memory gate electrode film is not aligned due to misalignment of the alignment device. It will not be formed at a position displaced from the underlying constituent film. As a result, MONOS with reliable read operation
It is possible to provide a memory, and it is possible to obtain a highly reliable semiconductor non-volatile memory that can be rewritten very many times.

[Brief description of drawings]

FIG. 1 is a sectional view showing a MONOS memory according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the MONOS memory according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a MONOS memory in a conventional example.

FIG. 11 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 12 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 13 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 14 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 15 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 16 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

FIG. 17 is a cross-sectional view showing the method of manufacturing the MONOS memory in the conventional example.

[Explanation of symbols]

 1 semiconductor substrate 3 tunnel oxide film 5 memory nitride film 7 top oxide film 9 memory gate electrode film 11 gate oxide film of MOS transistor 13 gate electrode film of MOS transistor

Claims (2)

[Claims] 1. A semiconductor non-volatile memory having a MONOS structure comprising a semiconductor substrate, a tunnel oxide film, a memory nitride film, a top oxide film, and a memory gate electrode film, the memory gate electrode being at least in an element region. The semiconductor non-volatile memory is characterized in that the film is smaller than the memory nitride film in the element region. 2. A step of forming a tunnel oxide film by thermally oxidizing the surface of a semiconductor substrate, a step of forming a memory nitride film on the tunnel oxide film, and a step of thermally oxidizing the memory nitride film to form a top oxide film. A step of selectively removing the top oxide film, the memory nitride film, and the tunnel oxide film to expose the semiconductor substrate surface; and a step of thermally oxidizing the exposed semiconductor substrate surface to form a gate oxide film. , A step of forming a gate electrode film material on the semiconductor substrate on which the gate oxide film is formed, and the gate electrode film material is selectively made to be smaller than the selectively removed memory nitride film at least in the element region. And a step of forming a memory gate electrode by removing it.