JPS594056A - Formation of contact hole - Google Patents

Abstract

PURPOSE:To provide a miniature and high precision through hole with good yield by forming a through hole in such dimension as is larger than the desired dimension and leaving as insulating film in high accuracy at the side wall of said hole without mask alignment. CONSTITUTION:A P type Si substrate 21 is isolated by an oxide film 22 and a gate oxide film 23, a phosphor added polycrystalline gate electrode 24 are formed. The N type layers 25a, 25b are formed by implanting As ion and the surface is covered with an SiO2 film 26 and an element is annealed in the N2 ambient. A hole 27 is bored in the dimension larger than the desired dimension by the photo etching method. Thereby the surface of gate electrode 24 is partly exposed in the hole 27. The surface is covered with SiO2 28 by the ion planting and a miniature electrode window can be obtained by covering the film 26 and the side wall of electrode 24 with the SiO2 film 28 being left by the reactive ion etching. Thereafter, an FET can be completed by providing Al wiring 29 and protection film 30. According to this structure, a margin of alignment can be made large at the time of forming a through hole and a hole can be opened in the vicinity of gate electrode 24. Thereby, areas of source, drain 25a, 25b can be reduced, realizing reduction in size of element and high integration density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor manufacturing technology, and particularly to improvements in a method for forming contact holes for establishing electrical connections.

[Technical background of the invention and its problems]

In recent years, semiconductor devices have become smaller and more highly integrated, and prototypes of so-called integrated circuits (ICs), large-scale integrated circuits (LSIs), and even ultra-L8Is have been developed. In order to improve the integration density of semiconductor devices, especially integrated circuits, it is necessary to further reduce the dimensions of the elements constituting the circuits. For this reason, there have been remarkable advances in microfabrication technology, and the photoresists used for light exposure have changed from negative to positive resists, which are more suitable for microfabrication, and the exposure method has been reduced from contact exposure to step-and-repeat. Research and development is progressing into exposure methods, as well as electron beam exposure methods and X-ray exposure methods.

However, it is not easy to accurately form fine patterns and replace them with semiconductor element structures.
Various problems remain to be resolved. -For example, the reduction of processing dimensions has brought about serious difficulties in terms of accuracy and reliability, and in particular, the formation of fine opening patterns (contact holes) is considered to be the most difficult task due to its shape. ing. Furthermore, in order to improve the degree of integration of a semiconductor device, it is necessary not only to reduce the size of the contact hole but also to reduce the size of element elements such as sources and drains. However, when forming a contact hole, alignment errors are taken into account, for example, at the light exposure technology stage, and alignment margins for these errors are not determined. Therefore, as shown in FIG. The drain region is shown.

When using a step-and-repeat reduction exposure device that is currently commonly used, an alignment margin of about 1 [μm] is required, and this is an impediment to higher integration. .

- h Note: In order to reduce the alignment margin, a technology called the self-line contact method has recently been announced. For example, J a p a n e se J o
u r na 1 of Applied Physi
cs, Volume 18 (1979) P'255
~260 to 8ELOC8 (5elective 0xi
de Coatingof 8 mouths 1 con Gate
) Technological power 1 known as law has been announced. In this method, a field oxidation film 12, a gate oxide film 13, and a doped polycrystalline silicon gate 14 are formed on a silicon substrate II shown in FIG. 2(a). As shown in FIG. 1, using the property that the oxidation rate of phosphorus-doped polycrystalline silicon is faster than that of single crystal silicon, a silicon oxide film I5 is formed to be particularly thick at the gate 14F.

Note that 168 and 16b in the figure indicate the source and drain. Next, in Fig. 2 (C) 1″-showing Calo<POC
In step 1, the surface layer of the silicon oxide film 15 is transformed into an IJ fused silicate glass (PEG) film 17. after that,
PSG until source/drain 16a, 16b is exposed.
The film 17 is etched, leaving the silicon oxide film 15 only on the gate 14 and its sides, as shown in FIG. 2 (d+).

Next, an Al wiring film 18 is formed as shown in FIG. 2(e).

Therefore, when forming the contact hole 1, this method does not require alignment margin with respect to the gate 2 as shown in FIG. In this method, the gate 1
There is a problem that the withstand voltage of the silicon oxide film 15 covering the silicon oxide film 4 is low.

Further, by oxidizing the polycrystalline silicon and forming the silicon oxide film 15, the gate 14 becomes thinner. When the dimensions of the gate 14 become smaller and the film thickness becomes thinner, the resistance of the gate 14 increases. Furthermore, the thicker the polycrystalline silicon is oxidized in order to increase the withstand voltage of the silicon oxide film 15, the thinner the gate 14 becomes, and it has been difficult to solve these problems at the same time.

[Purpose of the invention]

An object of the present invention is to be able to form fine contact holes for electrical connection with a high yield, to reduce the alignment margin when forming contact holes, and to achieve high integration of semiconductor devices. It is an object of the present invention to provide a contact hole forming method that can contribute to the improvement of technology.

[Summary of the invention]

The gist of the present invention is that when forming a contact hole for electrical connection with a conductive layer such as a diffusion layer in a position close to a conductive film such as a date electrode, firstly, a contact hole having a diameter larger than that of the desired contact hole is formed in an insulating film. The purpose of this invention is to form an opening 17 and then provide a new insulating film on the side wall of the opening, thereby providing a margin for pattern dimensions when forming the opening and reducing alignment margin.

That is, the present invention provides a first insulating film provided on the upper surface of each of a conductive layer and a first conductive film insulated on the conductive layer, and a second conductive film provided on the insulating film. When forming a contact hole for connection between the film and the h-channel conductive layer, an opening having a diameter larger than the desired contact hole is formed in the first insulating film adjacent to the conductive film of '@1. After forming the first insulating film, a second insulating film is provided on the conductive layer and the first insulating film including the primary openings, and then a portion of the second insulating film L is etched to form the insulating film in the openings. In this method, only the side wall portions are left with self-alignment lines. Further, the present invention provides a method for forming the second insulating film between the conductive film on the first conductive film and the first insulating film L as a pre-process of forming an opening in the first insulating film. The third layer has different etching properties from the film. In this method, an insulating film is provided.

Here, in order to improve the processing precision of the contact hole, it is necessary to perform a step of leaving the second insulating film on the side wall of the opening without mask alignment. It is desirable to provide a film over the entire surface and then etch the entire surface of the insulating film by an anisotropic dry etching method. At this time, as the step 7 for forming the second insulating film, the most preferable method is the ion blasting method since it can form fine holes with good coverage, but a thermal oxidation method or a CVD method may also be used. Furthermore, the material of the second insulating film and 1. Alternatively, a silicon oxide film, a silicon nitride film, or a composite film thereof may be used.

In order to control the second insulating film remaining on the side wall of the opening with higher precision, after providing the second insulating film, a control film is deposited on the insulating film (12).
Next, a method may be used in which the control film is etched over the entire surface by a W-oriented dry etching method, and then the second insulating film is selectively etched using the E-oriented film as a mask. At this time, as the control film, it is possible to use a semiconductor such as polycrystalline silicon, a metal such as KL or an alloy thereof, or an organic film such as resist.

Furthermore, when forming a closed hole in the first thread-colored edge, a part of the surface of the first conductive film is generally exposed.
, it is not necessary to actively expose the first conductive film. In other words, it is sufficient to form the opening at a position in front of the first conductive film to the extent that the first conductive film protrudes.

〔Effect of the invention〕

According to the present invention, when forming a contact hole (17), the size of the large opening to be patterned can be made larger than the desired contact hole diameter. In other words, since it is possible to increase the minimum dimension that must be formed in patterning technology, it is extremely effective in forming fine contact holes that are at or below the patterning limit. [7] Since the width of the insulating film left on the side wall of the opening can be controlled with high precision without mask alignment → masking, even minute contact holes can be formed with a high yield.

Therefore, it is effective for downsizing and highly integrating semiconductor devices, especially integrated circuits.

Further, even if an opening is formed in the first insulating film,
Since the exposed first conductive film can be removed by the subsequent remaining process of the second insulating film, it is possible to reduce the alignment margin when forming the contact hole.

Therefore, it has the effect of contributing to even higher integration of semiconductor devices.

Furthermore, if the insulating film of the temple 2 is formed by an ion blating method or the like, the remaining width of the second insulating film left on the side wall of the opening can be made sufficiently thick without causing thinning of the first conductive film. I can do it. For this reason, FFI mentioned S 1
8 L (,) The effect is tremendous compared to the CS method.

[Embodiments of the invention]

3(a) to ff) are cross-sectional views showing the manufacturing process of the MOS transistor fiA according to the first embodiment of the present invention. First, as shown in Figure 3 (l), the specific resistance is 5 to 50 [Q-
m) (7) P type (ioo) i/! J:+y71.
A plate 2I is prepared, a field oxide film 22 is embedded in the confectionery isolation region of this substrate 21, and a gate oxide film 23 and a gate electrode (first conductive film) 24 made of a phosphorous-doped polycrystalline silicon film are formed on the element formation region. form. continue,
Masking the gate electrode 24, As is applied to the silicon substrate 2.
Accelerating ions at a voltage of 40 (KeV) and a dose of lXl0”
Ion implantation is performed using [Keise] to form source/drain regions (conductive 1ift) 2sn, zsb. Next, using a vapor phase growth method, a silicon oxide film (first insulating film) 26 of about 1 [μm] was formed on the specimen as shown in FIG. 'C) Anneal for 20 minutes in nitrogen atmosphere. Next, a hole pattern (not shown) is formed in a resist using photolithography technology, and the silicon oxide film 2 is formed using this pattern as a mask.
6 to form an opening 27 as shown in FIG. 3 fc). At this time, the size of the opening 27 was made larger than the required contact hole diameter. Further, a 10:1 step-and-repeat type light exposure apparatus was used for patterning the resist, so that an opening 27 was formed at a position adjacent to the gate electrode 24. As a result, a portion of the surface of the gate electrode 24 was exposed within the opening 27.

Next, using the vapor phase growth method, the entire surface of the sample was coated as shown in FIG.
As shown in fl), a silicon oxide film (second insulating film) 28
4000(A). Next, using a reactive ion etching method, the entire surface of the silicon oxide film 28 is etched to about 4000 (A) as shown in FIG. 24 and silicon oxide film 2
A silicon oxide film 28 remains so as to cover the side walls of 6.

Then, the portion surrounded by the silicon oxide film 28 will be used as a contact hole.

From this point on, an N-channel MO8 transistor is manufactured by forming the A/wiring film (second conductive film) 29, protective film 30, etc. as shown in FIG. 3 (fl).

Thus, according to this embodiment, when forming a contact ball, the size of the opening 27 to be patterned can be made thicker than the required contact hole, and patterning can be facilitated. Further, it is possible to design the opening pattern of the resist to be as close as possible to the gate electrode 24 during back-cooning using a light exposure technique. 1.0: tThe overlay accuracy of a step-and-repeat type light exposure device can be approximately 0.3 [μm], so if a resist pattern is formed with the mask design as described above, the opening 27 will become the gate electrode. Even if it deviates to the 24 side, it is at most 0.3 [μm]. The exposed portion of the gate electrode 24 due to this degree of deviation is completely covered by the remaining silicon oxide film 28 in the subsequent process, so there is no problem with insulation. Therefore, the alignment margin when forming the contact hole can be reduced, and the contact hole can be formed in the vicinity of the gate electrode 24. Therefore, the source/drain region 25a
, 25b can be reduced, which allows the device to be made smaller and more highly integrated.

FIGS. 4(a) to 4(C) are cross-sectional views showing the steps of the second embodiment. This embodiment differs from the embodiment described in 1-y above in that a silicon nitride film (a third insulating film 2
3). That is, when forming the gate electrode 24, a silicon nitride film 31 is previously formed on the polycrystalline silicon film that will become the gate electrode 24.

By patterning, a silicon nitride film 31 and a gate electrode 24 are formed as shown in FIG. 4 (al).

Thereafter, through the formation of the silicon oxide Itψ26 described above and selective etching step 1, the opening 2 is formed as shown in FIG. 4 tb+.
form 7. In this case, even if the position of the opening 27 is shifted in multiple layers, the upper surface of the gate electrode 24 will not be exposed. Subsequently, the silicon oxide film 28 is formed and the entire surface is etched as described above, so that the silicon oxide film 28 is left on the side wall of the opening 27 as shown in FIG. 4(C). From this point on, a MOS resistor is manufactured through the same steps as in the previous embodiment.

Thus, according to this embodiment, not only the same effects as the previous embodiment but also the following effects can be achieved. That is, the opening 2
Setting the formation position force of 7. Only the side surfaces of the gate electrode 24 are exposed to the surface of the gate electrode 7 (FIG. 4(b)). Then, the side surface of the gate electrode 24 forming the side wall of the opening 27 is completely covered by the silicon oxide film 28 (FIG. 4(C)). Even if the formation position of the hole 27 is significantly shifted, it will cause insulation problems#
This makes it possible to reduce the alignment margin more than in the previous implementation. Therefore, it is possible to use an exposure apparatus using a batch transfer method, which has a small overlap margin (Q), compared to the exposure apparatus used in the previous embodiment.

FIGS. 5(a) to (cl) are cross-sectional views showing the steps of the third embodiment. The difference between this embodiment and the previous first embodiment is that the remaining nitric oxide film 28 is It is in.

That is, as shown in FIG. 3(d) (-) is the formation process of the silicon oxide film 28, and as shown in FIG. Using a dry etching method, the entire surface of the resist 32 is etched as shown in FIG. 5 (rb), leaving the resist 592 only on the exposed sidewalls. Next is 1. Silicon oxide film 28 using the remaining resist 32 as a mask
By selectively etching and then removing the resist 32, it was possible to leave the silicon oxide film 28 only on the side wall of the opening 27, as shown in FIG. 5 (CI).

Therefore, according to this embodiment, not only can the same effects as in the first embodiment described above be achieved, but also the remaining width of the silicon oxide film 28 remaining on the side wall of the opening 27 can be controlled with higher precision. becomes.

Note that the present invention is not limited to the embodiments described above. For example, the first insulating film is not limited to one layer, and may have a multilayer structure of two or more layers. Furthermore, the second insulating film is not limited to a silicon oxide film grown using a vapor phase growth method;
Alternatively, it may be a silicon oxide film or a silicon nitride film formed by thermal oxidation of silicon, or a multilayer film combining these. Furthermore, the dimension h of the opening to be formed in the first insulating film, the desired contact hole dimension, and the second
It may be determined as appropriate depending on conditions such as the remaining width of the insulating film.

Further, the third insulating film is not limited to a silicon nitride film, but may be any film having etching characteristics different from those of the second insulating film. Furthermore, instead of the resist as the control film, it is also possible to use polycrystalline silicon, silicon nitride film, /l film, or the like. Also, MOS
) The present invention is applicable not only to transistors but also to the manufacture of various semiconductor devices in which it is necessary to form a contact hole near the side of a first conductor film that is not connected to the conductor film. That is, the conductive layer is not limited to the source/drain region, but may be a conductive film such as polycrystalline silicon or Al wiring. In short, the present invention can be implemented with various modifications 17 without departing from the gist thereof.

[Brief explanation of the drawing]

@1 Figure (81, (h) is a schematic diagram for explaining the problem of alignment margin in contact hole formation, Figures 2 (a) to (el is a conventional MOS) sectional view showing the transistor manufacturing process, Figure 3 (at to ge) is a cross-sectional view showing the manufacturing process of a MOS transistor according to the first embodiment of the present invention;
FIG. 4 (al~(C1) is a sectional view showing the process of the second embodiment, FIG. 5 (al~(C) is a sectional view showing the process of the third example. 21...Silicon substrate, 22... Field oxide film, 23... Gate oxide film, 24... Gate electrode (first conductive film), 25a, 25b... Source/drain region (conductive layer), 26... Silicon Oxide film (first insulating film), 27... Opening, 28... Silicon oxide film (second insulating film), 29... A, J wiring film (second conductive film), 3o. ...protective odor, 31...silicon nitride H (3
3), 32...resist (control film). Applicant's agent Patent attorney Takehiko Suzue Figure 1 (a) (1)) Figure 2 (a)

Claims (1)

[Scope of Claims] In the method of forming a contact hole for connection between a second conductive film and the conductive layer, a contact hole having a diameter larger than a desired contact hole is formed in the first insulating film adjacent to the first conductive film. forming an opening in the conductive layer and the first conductive layer including the opening;
a step of providing a second insulating film on the insulating film, and then a step of etching a portion of the second insulating film described in E to leave the insulating film only on the side wall of the opening as a self-line. A contact hole forming method characterized by: (2) The contact hole forming method according to claim 1, wherein the conductive layer is a source region or a drain region formed on a surface of a semiconductor substrate. (3) The contact hole forming method according to claim 1, wherein the second conductive film is an AJ film or an A7 alloy film used as a second layer wiring. (4) The contact hole forming method according to claim 1, wherein the second insulating film is a silicon oxide film formed by an ion blating method or a thermal oxidation method. (5) As a step of leaving the second insulating film only on the side wall portion of the opening, the above @
2. The contact hole forming method according to claim 1, wherein the insulating film No. 2 is etched over the entire surface. (6) As the step of leaving the second insulating film only on the side wall of the opening, after providing the second insulating film, coating the second insulating film with a resist, and then A patent claim characterized in that the entire surface of the resist is etched by an anisotropic etching method so that the resist remains only on the side wall of the opening, and then the second insulating film is selectively etched using the resist as a mask. The contact hole forming method according to item 1. (7) α゛31 provided on the upper surface of each of the conductive layer and the first conductive film provided insulated on the conductive layer.
In the method of forming a contact hole in an insulating film for connection between a second conductive film provided on the insulating film and the conductive layer, the conductive film on the first conductive film and the conductive layer are formed in advance. a step of providing a third insulating film between the first insulating film, and then forming an opening in the first insulating film adjacent to the third insulating film and having a diameter larger than a desired contact hole. a second insulating film having different etching characteristics from the third insulating film; Contact pole formation characterized by comprising a step of etching a portion of the insulating film so that a self-line remains only on the side wall of the opening of the insulating film.