KR0130200B1 - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
KR0130200B1
KR0130200B1 KR1019890011519A KR890011519A KR0130200B1 KR 0130200 B1 KR0130200 B1 KR 0130200B1 KR 1019890011519 A KR1019890011519 A KR 1019890011519A KR 890011519 A KR890011519 A KR 890011519A KR 0130200 B1 KR0130200 B1 KR 0130200B1
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South Korea
Prior art keywords
forming
polysilicon
layer
intermediate layer
poly
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KR1019890011519A
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Korean (ko)
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KR910005428A (en
Inventor
김준기
여인석
김홍석
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문정환
엘지반도체주식회사
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Publication of KR910005428A publication Critical patent/KR910005428A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

A fabrication method of IC's(Integrated Circuits) using a low temperature oxide sidewall is disclosed. The method comprises the steps of: forming a spacer(4) at both sides of a gate(3); forming a source(5) and a drain(6) by ion-implanting using the gate(3) and the spacer(4) as a mask; forming a buried contact by etching a low temperature oxide layer(7); depositing a poly-Si layer(8) and a photoresist pattern(PR); forming sidewalls(9) at both sides of the poly-Si layer(8) and the PR pattern; removing the PR pattern and depositing a poly-Si layer(8'); and forming a storage node by etching the poly-Si layer(8').

Description

반도체 소자 제조 방법Semiconductor device manufacturing method

제1도는 (가)-(차)는 본 발명의 제조공정을 설명하기 위한 반도체 소자의 수직 단면도.1A to 4D are vertical cross-sectional views of a semiconductor device for explaining the manufacturing process of the present invention.

제2도는 종래의 집적회로 제조공정을 설명하기 위한 수직 단면도.2 is a vertical cross-sectional view for explaining a conventional integrated circuit manufacturing process.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 기판 2 : 절연층1: semiconductor substrate 2: insulating layer

3 : 게이트 전극 4 : 스페이서3: gate electrode 4: spacer

5 : 소오스 6 : 드레인5: source 6: drain

7 : 제 1 절연막 8,10 : 폴리실리콘7: first insulating film 8,10 polysilicon

9 : 제 2 절연막9: second insulating film

본 발명은 저온 증착 산화막(Low Temperature Oxide : LTO)의 측벽(Side Wall)을 이용하여 대용량 캐패시턴스를 갖도록 한 것으로, 특히 좁은 면적에 대용량 캐패시턴스를 필요로 하는 초집적도(Very Large Scale Integration)를 갖는 IC 제조에 적합하도록 한 반도체 소자 제조 방법에 관한 것이다.The present invention is to have a large capacitance by using the side wall (Lide Temperature Oxide (LTO) side wall) of the low temperature oxide (LTO), particularly IC having a large scale (Very Large Scale Integration) that requires a large capacitance in a small area It relates to a method for manufacturing a semiconductor device suitable for manufacturing.

종래의 IC 제조 방법에 있어서는 제2도에 나타낸 바와 같이, 기판(31)상에 절연층(32)과 게이트(33)을 연이어 형성시킨 다음 게이트(33)를 따라 띠(Ribon)가 형성되는 것을 방지하고, 게이트(33)을 절연시키기 위해 저온 증착 산화막을 침적시킨 후 블랭키트(Blanket) 에칭 공정을 거쳐 게이트(33)의 측면에 스페이서(34)를 형성한 다음 이온 주입 및 열처리 공정을 거쳐 소오스(35)와 드레인(36)을 형성하고, 이어서 스토리지 노드(Storage Node)와 동작영역이 접촉하는 대몰 접촉 영역(Buride Contact)을 제외한 영역에서 스토리지 노드를 격리시키기 위해 저온 증착 산화막(37)을 침적(Deposition)시킨 후 스토리지 노드와 동작영역이 접촉되도록 마스크 및 에칭 공정을 거쳐 메몰 접촉 영역을 형성시킨 다음 스토리지 노드에 사용할 폴리실리콘(38)을 침적한 후 마스크와 에칭 공정을 거쳐 스토리지 노드를 형성하는 것이었으나, 이는 스토리지 노드의 표면적이 좁으므로 이에 따라 집적회로 내에서 대용량 캐패시턴스를 갖지 못하는 단점이 있었다.In the conventional IC manufacturing method, as shown in FIG. 2, the insulating layer 32 and the gate 33 are successively formed on the substrate 31, and then a rib is formed along the gate 33. After the deposition of the low-temperature deposition oxide film to insulate the gate 33, the spacer 34 is formed on the side of the gate 33 through a blanket etching process, and then subjected to an ion implantation and heat treatment process. The low-temperature deposition oxide film 37 is formed to form the source 35 and the drain 36, and to isolate the storage node from an area other than the bulk contact area where the storage node and the operation area contact each other. After deposition, a mask and etching process is performed to make contact with the storage node and the operation region, and then a recessed contact region is formed, and then the polysilicon 38 to be used for the storage node is deposited, and then the mask and etching process is performed. However, the storage node was formed, but since the surface area of the storage node is narrow, there is a disadvantage in that it does not have a large capacitance in the integrated circuit.

본 발명은 이와 같은 종래의 단점을 해서시키기 위하여 스토리지 노드가 형성된 종래의 IC 상면에 감광막을 입힌 다음 감광막 측면에 저온 증착 산화막으로 된 측벽을 형성시킨 다음 이어서 감광막을 제거하고, 그의 상면에 스토리지 노드가 될 폴리층을 침적시키므로서 대용량 캐패시턴스를 갖는 VLSI급 집적회로를 제조할 수 있도록 한 저온 증착 산화막 측벽을 이용한 집적회로 제조방법을 제공하는 것을 목적으로 하는 것으로, 이하 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.In order to solve the above disadvantages, the present invention coats a photoresist film on an upper surface of a conventional IC in which a storage node is formed, and then forms a sidewall of a low temperature deposition oxide film on the side of the photoresist film, and then removes the photoresist film, It is an object of the present invention to provide an integrated circuit fabrication method using a low-temperature deposited oxide sidewall to manufacture a VLSI class integrated circuit having a large capacitance by depositing a poly layer to be deposited. It will be described in detail as follows.

제1도의 (가)-(차)에 나타낸 바와 같이, 본 발명의 반도체 소자 제조방법은 반도체 기판(1)상에 절연층(2)와 게이트 전극(3)을 연이어 형성시킨 다음 게이트 전극(3) 측면에 스페이서(4)를 형성시키고, 이어서 이온 주입 및 열처리 공정으로 소오스(5)와 드레인(6)을 형성시키는 제 1 공정과, 상기 제 1 공정 이후 저온 증착 산화막으로 된 제 1 절연막(7)을 침적시킨 다음 마스크와 에칭공정을 거쳐 메몰 접촉영역을 형성시킨 후 그의 상면에 제 1 폴리실리콘(8)을 침적하는 제 2 공정으로 된 집적회로 제조 방법에 있어서, 상기 제 2 공정 이후 스토리지 노드 마스크를 이용하여 제 1 폴리실리콘(8) 상면에 감광막으로 된 중간층(P/R)을 형성시킨 다음 제 1 폴리실리콘을 에칭한 후, 상기 제 2 폴리실리콘(8)과 중간층(P/R) 측면에 저온 증착 산화막 도포 및 블랭키트 에칭 공정을 거쳐 제 2 절연막 측벽(9)을 형성시키고, 이어서 중간층(P/R)을 제거시킨 후 그의 상면에 콘덴서 노드가 될 제 2 폴리실리콘(8')을 침적시킨 다음 포토 식각법과 에칭 공정을 실시하여 콘덴서 노드를 형성하는 제 3 공정으로 이루어진 것이다.As shown in (a)-(d) of FIG. 1, in the method of manufacturing a semiconductor device of the present invention, the insulating layer 2 and the gate electrode 3 are successively formed on the semiconductor substrate 1, and then the gate electrode 3 The first step of forming a spacer (4) on the side surface, and then the source (5) and the drain (6) by the ion implantation and heat treatment process, and the first insulating film (7) made of a low-temperature deposition oxide film after the first process ). A method of fabricating an integrated circuit comprising a second process of depositing a first polysilicon 8 on the upper surface thereof by forming a buried contact region through a mask and an etching process after depositing the same). After forming a photoresist intermediate layer (P / R) on the upper surface of the first polysilicon 8 using a mask, and then etching the first polysilicon, the second polysilicon 8 and the intermediate layer (P / R) Low temperature deposition oxide coating and blank kit etching on the side After the formation of the second insulating film sidewall 9, the intermediate layer P / R is removed, and then the second polysilicon 8 ', which will be a capacitor node, is deposited on the upper surface thereof, followed by photo etching and etching. And a third step of forming a capacitor node.

이와 같은 방법으로 이루어진 본 발명의 작용효과를 설명하면 다음과 같다.Referring to the effects of the present invention made in such a way as follows.

먼저, 반도체 기판(1)상에 절연층(2)과 게이트 전극(3)을 연이어 형성시키는 공정에 서 제 1 폴리실리콘(8)을 침적하는 공정은 종래와 동일한 방법에 의해 형성하므로 중복된 설명을 피하기 위해 이에 대한 설명은 생략한다.First, in the step of forming the insulating layer 2 and the gate electrode 3 on the semiconductor substrate 1 in succession, the step of depositing the first polysilicon 8 is formed by the same method as in the prior art, and thus the overlapping description will be given. In order to avoid the description thereof will be omitted.

이어서 제 1 폴리실리콘(8)을 형성시킨 IC 상면에 스토리지 노드 마스크를 이용한 포토 식각 공정을 제 1 폴리실리콘(8)의 일부를 에칭하게 되는데, 이때 마지막 공정에서 사용할 마스크와 동일한 디스크를 사용하기 위해서는 정상 감광시간보다 길게 감광을 하여 포토 식각 공정중의 디벨릅 바이어스(Develp Dias)를 최대한 크게 한다.Subsequently, a part of the first polysilicon 8 is etched by a photo etching process using a storage node mask on the upper surface of the IC on which the first polysilicon 8 is formed. In this case, in order to use the same disk as the mask to be used in the last process, The photosensitive process is longer than the normal photosensitive time to maximize the development of the developer bias during the photolithography process.

이어서 저온 증착 산화막 도포 및 블랭키트 에칭을 실시하여 중간층 측면에 제 2 절연막 측벽(9)을 형성시킨 후 중간층(P/R)만을 제거한 다음 콘덴서 노드가 될 제 2 폴리실리콘(8')을 침적한 후 콘덴서 노드를 포토 식각법과 에칭 공정에 의해 형성하므로 콘덴서 노드의 표면적이 넓게 형성되어 이에 따라 집적회로가 대용량 캐패시턴스를 가질수가 있다.Subsequently, a low-temperature deposition oxide film was applied and a blank kit was etched to form the second insulating film sidewall 9 on the side of the intermediate layer. Then, only the intermediate layer P / R was removed, and the second polysilicon 8 'to be a capacitor node was deposited. After that, since the capacitor node is formed by the photo etching method and the etching process, the surface area of the capacitor node is widened, thereby allowing the integrated circuit to have a large capacitance.

이상에서 설명한 바와 같이 본 발명에 의하면 저온 증착 산화막으로 측벽을 형성하여 콘덴서 노드의 표면적을 넓힘으로서 이에 따라 대용량 캐패시턴스를 가질 수가 있는 것이어서 좁은 면적에서도 대용량 캐패시턴스를 필요로 하는 VLSI 집적회로 제조공정에 가장 적합한 것이다.As described above, according to the present invention, by forming a sidewall with a low temperature deposition oxide film to increase the surface area of a capacitor node, it is possible to have a large capacitance, which is most suitable for a VLSI integrated circuit manufacturing process requiring a large capacitance even in a small area. will be.

Claims (1)

반도체 기판(1)에 게이트 전극(3)과, 상기 게이트 전극(3) 양측에 소오스(5) 및 드레인(6) 영역을 형성하는 제 1 공정과, 제 1 공정 이후 게이트 전극(3)을 포함한 반도체 기판(1) 위에 제 1 절연막(7)을 형성하고, 소오스(5) 및 드레인(6) 영역중 일영역의 제 1 절연막(7)을 선택식각하여 접촉영역을 형성하는 제 2 공정과, 상기 접촉영역이 형성된 제 1 절연막(7) 위에 제 1 폴리실리콘(8)을 형성하는 제 3 공정과, 제 3 공정 이후 제 1 폴리실리콘(8) 위에 중간층(P/R)을 형성한 후 콘덴서 노드 전극 영역에 중간층(P/R)과 제 1 폴리실리콘(8)을 잔류시키는 제 4 공정과, 상기 제 4 공정 이후 잔류된 중간층(P/R)과 제 1 폴리실리콘(8)의 측면에 제 2 절연막 측벽(9)을 형성하고, 중간층(P/R)을 제거하는 제 5 공정과, 상기 중간층(P/R)을 제거하여 노출된 기판 전면에 제 2 폴리실리콘(8')을 형성하는 제 6 공정으로 이루어진 반도체 소자 제조 방법.A first process of forming a gate electrode 3 on the semiconductor substrate 1, a source 5 and a drain 6 region on both sides of the gate electrode 3, and a gate electrode 3 after the first process. Forming a contact region by forming a first insulating film 7 on the semiconductor substrate 1 and selectively etching the first insulating film 7 in one region of the source 5 and drain regions 6; A third process of forming the first polysilicon 8 on the first insulating film 7 having the contact region formed thereon, and after forming the intermediate layer P / R on the first polysilicon 8 after the third process, A fourth process of leaving the intermediate layer (P / R) and the first polysilicon (8) in the node electrode region; and a side surface of the intermediate layer (P / R) and the first polysilicon (8) remaining after the fourth process. A fifth process of forming the second insulating film sidewall 9 and removing the intermediate layer (P / R); and removing the intermediate layer (P / R) to expose the entire surface of the second polysilicon (8 '). Method of manufacturing a semiconductor device comprising a sixth step of forming.
KR1019890011519A 1989-08-12 1989-08-12 Manufacture of semiconductor device KR0130200B1 (en)

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KR1019890011519A KR0130200B1 (en) 1989-08-12 1989-08-12 Manufacture of semiconductor device

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KR1019890011519A KR0130200B1 (en) 1989-08-12 1989-08-12 Manufacture of semiconductor device

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KR910005428A KR910005428A (en) 1991-03-30
KR0130200B1 true KR0130200B1 (en) 1998-04-06

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