KR100246804B1 - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device Download PDF

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KR100246804B1
KR100246804B1 KR1019970027379A KR19970027379A KR100246804B1 KR 100246804 B1 KR100246804 B1 KR 100246804B1 KR 1019970027379 A KR1019970027379 A KR 1019970027379A KR 19970027379 A KR19970027379 A KR 19970027379A KR 100246804 B1 KR100246804 B1 KR 100246804B1
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pattern
mask
charge storage
storage electrode
semiconductor device
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KR1019970027379A
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Korean (ko)
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KR19990003498A (en
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조찬섭
장환수
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

3반도체 소자의 전하저장전극 형성에 있어서, 마스크상의 종래 고립패턴은 노광시 빛의 회절로 인하여 패턴에 불량이 발생한다. 따라서 본 발명은 두 번에 걸쳐 마스크공정을 실시하고 각 마스크상에 선형패턴 및 보조패턴을 형성하여 노광시 패턴의 라운딩 현상을 제거하므로 패턴의 불량을 제거하고 균일성을 향상시키는 전하저장전극 형성방법이 개시된다.In the formation of the charge storage electrode of a three-semiconductor element, the conventional isolated pattern on the mask causes defects in the pattern due to diffraction of light upon exposure. Therefore, the present invention performs a mask process twice and forms a linear pattern and an auxiliary pattern on each mask to remove the rounding phenomenon of the pattern during exposure, thereby eliminating defects in the pattern and improving the uniformity of the charge storage electrode formation method. This is disclosed.

Description

반도체 소자의 전하저장전극 형성방법Method for forming charge storage electrode of semiconductor device

본 발명은 반도체 소자의 전하저장전극 형성방법에 관한 것으로, 특히 사진공정에서 프로세스 윈도우(Process Window)를 충분히 확보하기 위해 전하저장전극용폴리실리콘 패턴을 디자인하는 기술에 관한 것이다.The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly, to a technology for designing a polysilicon pattern for a charge storage electrode in order to sufficiently secure a process window in a photographic process.

일반적인 반도체 소자의 전하저장전극 형성 공정을 도 1을 참조하여 설명하면 다음과 같다.A charge storage electrode forming process of a general semiconductor device will be described with reference to FIG. 1.

소자분리공정으로 액티브 영역(1)을 확정한 후 트랜지스터(도시않됨) 형성공정과 층간절연막(도시않됨) 형성공정을 완료한 후 콘택 마스크를 사용한 층간 절연막 식각공정으로 트랜지스터의 소오스 영역(도시않됨)이 노출되는 콘택 홀(2)을 형성한다. 폴리실리콘 증착 및 전하저장전극용 마스크를 사용한 폴리실리콘층 식각공정으로 콘택 홀(2)을 통해 소오스영역과 연결되는 전하저장전극(3)이 형성된다. 전하저장전극(3)의 이상적인 형상(Profile)은 전하저장전극용 마스크에 디자인된 크롬 패턴과 동일하게 형성되어야 하지만 노광공정시 크롬 패턴의 모서리진 부분에서 빛의 회절이 일어나 전하저장전극(3)의 모서리진 부분(A)에서 라운딩 현상이 발생하는 등 패턴에 불량이 발생한다.After the active region 1 is determined by the device isolation process, the transistor (not shown) forming process and the interlayer insulating film (not shown) forming process are completed, and then the source region (not shown) of the transistor is formed by the interlayer insulating film etching process using a contact mask. This expose contact hole 2 is formed. In the polysilicon layer etching process using the polysilicon deposition and the mask for the charge storage electrode, the charge storage electrode 3 connected to the source region is formed through the contact hole 2. The ideal profile of the charge storage electrode 3 should be formed in the same way as the chromium pattern designed on the mask for the charge storage electrode, but the light diffraction occurs at the corners of the chromium pattern during the exposure process. Defects occur in the pattern, such as a rounding phenomenon occurs in the corner portion (A) of.

따라서, 본 발명은 사진공정시 이중마스크와 보조 패턴을 이용하여 상기 문제점을 해소할 수 있는 저장전극 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a storage electrode that can solve the above problem by using a double mask and an auxiliary pattern during a photo process.

상기 목적을 달성하기 위한 본 발명은 반도체 소자의 전하저장전극 형성방법에 있어서, 폴리실리콘층상에 포토레지스트를 도포하는 단계와, X축 선형 패턴과 다수의 보조패턴이 형성된 제 1 마스크로 1차 노광공정을 실시하는 단계와, Y축 선형패턴이 형성된 제 2 마스크로 2차 노광공정을 실시하는 단계와, 상기 제 1 및 제 2차 노광공정을 거친 상기 포토레지스트를 현상한 후 상기 폴리시리콘층의 노출된 부분을 제거하는 단계로 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a charge storage electrode of a semiconductor device, the method comprising: applying a photoresist on a polysilicon layer, and first exposure with a first mask having an X-axis linear pattern and a plurality of auxiliary patterns formed thereon Performing a process; performing a second exposure process with a second mask having a Y-axis linear pattern; developing the photoresist after the first and second exposure processes; Removing the exposed part.

도 1은 종래 반도체 소자의 전하저장전극을 형성하기 위한 레이아웃.1 is a layout for forming a charge storage electrode of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 전하저장전극을 형성하기 위한 레이 아웃.2A to 2C are layouts for forming a charge storage electrode of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명>* Explanation of symbols for main parts of drawings

1 및 11 : 액티브영역 2 및 14 : 콘택 홀1 and 11: active region 2 and 14: contact hole

12 : 전하저장전극 12A : X축 선형 패턴12: charge storage electrode 12A: X-axis linear pattern

12B : Y축 선형 패턴 13 : 보조패턴12B: Y-axis linear pattern 13: auxiliary pattern

이하, 첨부도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 전하저장전극 형성방법을 설명하기 위한 레이아웃이다.2A to 2C are layouts for describing a method of forming a charge storage electrode according to the present invention.

소자 분리공정으로 액티브 영역(11)을 확정한 후 트랜지스터(도시않됨)형성 및 층간절연막(도시않됨) 형성공정을 완료한 후 콘택 마스크를 사용한 층간 절연막 식각공정으로 트랜지스터의 소오스 영역(도시않됨)이 노출되는 콘택 홀(14)을 형성한다. 콘택 홀(14)이 형성된 전체구조상에 폴리실리콘을 증착한 후, 폴리실리콘층상에 포토레지스트(도시않됨)를 도포한다. 이후 도 2a에 도시된 바와같이 X축 선형패턴(12A)과 보조패턴(13)이 형성된 제 1 마스크로 1차 노광공정을 실시하고, 도 2b에 도시된 바와같이 Y축 선형패턴(12B)이 형성된 제 2 마스크로 2차 노광공정을 실시한다. 2 단계 노광공정을 거친 포토레지스트를 현상하여 포토레지스트 패턴을 형성하고, 포토레지스트 패턴을 이용한 폴리실리콘층 식각공정으로 도 2c에 도시된 전하저장전극(12)이 형성된다.After the active region 11 is determined by the device isolation process, the transistor (not shown) formation and the interlayer dielectric film (not shown) are completed, and the source region (not shown) of the transistor is formed by the interlayer insulation layer etching process using a contact mask. The exposed contact hole 14 is formed. After depositing polysilicon on the entire structure in which the contact hole 14 is formed, a photoresist (not shown) is applied on the polysilicon layer. Thereafter, as shown in FIG. 2A, the first exposure process is performed using the first mask having the X-axis linear pattern 12A and the auxiliary pattern 13 formed thereon, and as shown in FIG. 2B, the Y-axis linear pattern 12B is formed. The secondary exposure process is performed with the formed second mask. The photoresist, which has undergone the two-step exposure process, is developed to form a photoresist pattern, and the charge storage electrode 12 shown in FIG. 2C is formed by a polysilicon layer etching process using the photoresist pattern.

상기에서, 제 1마스크는 전하저장전극(12)의 X축 방향의 패턴 형상을 정의하고, 제 2 마스크는 전하저장전극(12)의 Y축 방향의 패턴을 형상을 정의하는데 사용된다. 제 1마스크에 삽입된 보조패턴(13)은 제 1 마스크와 제 2 마스크를 겹쳤을 때 X축 선형 패턴(12A)과 Y축 선형 패턴(12B)이 중첩되는 부분의 가장자리에 위치되며, 노광공정시 빛의 회절현상을 고려하여 중첩부분중 각진 부분에 위치시키는 것이 바람직하다. 이로 인하여 전하저장전극(12)의 모서리 부분(A)에서 라운딩 현상을 방지할 수 있다.In the above, the first mask defines a pattern shape in the X-axis direction of the charge storage electrode 12, and the second mask is used to define a shape in the Y-axis direction of the charge storage electrode 12. The auxiliary pattern 13 inserted in the first mask is positioned at the edge of the portion where the X-axis linear pattern 12A and the Y-axis linear pattern 12B overlap when the first mask and the second mask overlap. In consideration of the diffraction phenomenon of the time light, it is preferable to locate the angular part of the overlapping part. As a result, a rounding phenomenon may be prevented at the corner portion A of the charge storage electrode 12.

상술한 바와같이 이중 마스크 및 보조 패턴을 사용하므로 패턴의 불량 및 단차가 개선되고, 보조 패턴이 라운딩 현상을 방지하므로 폴리실리콘 패턴의 균일성을 향상시킴으로써 전하저장용량을 균일하게 하고 충전특성을 향상시키는 효과가 있다.As described above, the use of the double mask and the auxiliary pattern improves the defect and the step of the pattern, and the auxiliary pattern prevents the rounding phenomenon, thereby improving the uniformity of the polysilicon pattern, thereby making the charge storage capacity uniform and improving the charging characteristics. It works.

Claims (3)

반도체 소자의 전하저장전극 형성방법에 있어서,In the method of forming a charge storage electrode of a semiconductor device, 소정의 기판의 폴리실리콘층상에 포토레지스트를 도포하는 단계와,Applying a photoresist on the polysilicon layer of the given substrate, X축 선형 패턴과 다수의 보조패턴이 형성된 제 1 마스크로 1차 노광공정을 실시하는 단계와,Performing a first exposure process with a first mask on which an X-axis linear pattern and a plurality of auxiliary patterns are formed; Y축 선형패턴이 형성된 제 2 마스크로 2차 노광공정을 실시하는 단계와,Performing a second exposure process with a second mask having a Y-axis linear pattern formed thereon; 상기 제 1 및 제 2차 노광공정을 거친 상기 포토레지스트를 현상한 후 상기 폴리실리콘층의 노출된 부분을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.And removing the exposed portion of the polysilicon layer after developing the photoresist through the first and second exposure processes. 제 1 항에 있어서,The method of claim 1, 상기 제 1 마스크에 삽입된 보조패턴들 각각은 상기 X축 선형패턴과 상기 Y축 선형패턴이 중첩되는 부분의 가장자리에 위치되는 것을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.Each of the auxiliary patterns inserted into the first mask is positioned at an edge of a portion where the X-axis linear pattern and the Y-axis linear pattern overlap. 제 1 항에 있어서,The method of claim 1, 상기 제 2 마스크에 다수의 보조패턴이 형성됨을 특징으로 하는 반도체 소자의 전하저장전극 형성방법.A method of forming a charge storage electrode of a semiconductor device, characterized in that a plurality of auxiliary patterns are formed in the second mask.
KR1019970027379A 1997-06-25 1997-06-25 Manufacture of semiconductor device KR100246804B1 (en)

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KR100510455B1 (en) * 1998-02-12 2005-10-24 삼성전자주식회사 Mask pattern for formation of an isolated pattern, method for fabricating the same and method for forming an isolated pattern using the same

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