JP2655371B2 - Method for forming mask pattern of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a mask pattern of a highly integrated semiconductor device, and more particularly to a method of forming a first photosensitive film on a semiconductor substrate in order to minimize the interval between patterns formed on a predetermined portion thereof. Is applied to form a first photosensitive film mask in an exposure and development process, and a second photosensitive film is applied at predetermined intervals to form a second photosensitive film mask in an exposure and development process to form a pattern. The present invention relates to a method for forming a mask pattern of a semiconductor device to be formed.

[0002]

2. Description of the Related Art In the prior art, a predetermined conductive layer is first formed on a semiconductor substrate in order to form an electrode or a wiring having a predetermined shape. And after applying a photosensitive film on the top,
Depending on the exposure and development technology, the desired size, ie,
A photosensitive mask having a predetermined width and length is formed. Thereafter, the portion of the conductive layer exposed by the photosensitive film mask was etched to form a predetermined target electrode or wiring.

However, according to the above-mentioned method, the distance between the photosensitive mask patterns that can be formed by the exposure and development techniques is limited. For example,
According to equipment and technology commonly used to date,
A minimum photosensitive mask line width of about 0.6 μm or more must be required.

Accordingly, the present invention provides a first photosensitive film mask using a first photosensitive film to minimize the space between the limited mask line widths, and a predetermined distance between the first photosensitive film mask and the first photosensitive film mask. And forming a second photosensitive film mask using the second space. In order to reduce the line width of the mask by minimizing the space between the first and second photosensitive film masks, etc. It is an object of the present invention to provide a method for forming a mask pattern of a semiconductor device.

[0005]

According to the method of forming a mask pattern of a semiconductor device according to the present invention, a substrate having a conductive layer on which a mask pattern is formed is provided, and a first photosensitive film is provided on the entire structure. Forming a layer,
Arranging a first mask configured such that only a predetermined portion is exposed above the photosensitive film, and exposing a part of the first photosensitive film exposed by the first mask to ultraviolet rays to develop the structure; Removing the first photosensitive film exposed to ultraviolet light in a liquid to form a first photosensitive film mask layer;
Depositing a second photosensitive film on the exposed entire structure, and arranging a second mask on the second photosensitive film at a predetermined distance from one side of the first photosensitive mask layer; A portion of the second photosensitive film exposed by the mask for the second charge storage electrode is exposed to ultraviolet light, and the structure is put into a developer to remove the second photosensitive film exposed to ultraviolet light to remove the first photosensitive film. Forming a second photosensitive mask layer having a predetermined distance from one side of the mask to expose a conductive layer desired to be etched; and defining a predetermined distance between the first and second photosensitive mask layers. Performing a mask pattern of the conductive layer except for the conductive layer exposed at a predetermined interval, thereby minimizing the width of the mask pattern of the conductive layer.

According to another embodiment of the present invention, there is provided a method of forming a mask pattern of a semiconductor device, comprising the steps of providing a substrate, and forming an insulating layer, a charge storage electrode conductive layer and a first layer on the substrate.
Sequentially forming a photosensitive film layer; arranging a first charge storage electrode mask configured to expose only a predetermined portion on the first photosensitive film; and forming the first charge storage electrode. Exposing a part of the first photosensitive film exposed by the mask to ultraviolet light, and forming the first photosensitive film mask layer by removing the first photosensitive film exposed to ultraviolet light by putting the structure in a developer. Exposing a portion of the conductive layer for the charge storage electrode thereunder; and baking the first photosensitive mask layer at a predetermined temperature for a predetermined time so as to cure the first photosensitive film mask layer. Depositing a second photosensitive layer on the exposed entire structure, and storing a second charge on the second photosensitive layer at a predetermined distance from one side of the first photosensitive mask layer. Arranging a mask for the second electric charge, Exposing a portion of the second photosensitive film exposed by the electrode mask to ultraviolet light; and removing the second photosensitive film exposed to ultraviolet light by putting the structure in a developer to remove the cured second photosensitive film. Forming a second photosensitive film mask layer having a predetermined distance from one side of the film mask to expose a conductive layer for a charge storage electrode to be etched; and forming the first and second photosensitive film mask layers. Forming a charge storage electrode excluding the charge storage electrode conductive layer exposed at a predetermined interval between,
Thus, the distance between the charge storage electrodes can be minimized.

According to the present invention, the step of baking the first photosensitive film mask layer is characterized by hard baking at a temperature of 100 to 150 ° C. for about 10 to 60 minutes.

According to the present invention, the mask for the second charge storage electrode is disposed between one side surface of the first photosensitive film mask and a minimum misalignment effective distance required in a mask process and between the charge storage electrodes formed later. Are arranged in consideration of only the minimum insulation interval of

When a predetermined electrode or wiring is formed by the mask pattern method of the present invention, the first and second electrodes are formed.
Minimize the distance between the photosensitive film masks and reduce the line width to 0.
It can be reduced to 6 μm or less.

The method for forming a mask pattern according to the present invention is also applied to a method for manufacturing a charge storage electrode, for example, a method for minimizing a space between wirings or a method for minimizing a line width of wirings. be able to.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout diagram in which main mask layers for manufacturing a DRAM (Dynamic Random Access Memory) cell having a laminated capacitor structure according to the prior art are arranged. Generally, an active mask A in a region where source and drain electrodes (not shown) of the MOSFET are formed, a mask B for a gate electrode in which a long gate electrode (not shown) of the MOSFET is formed, And a mask C for a charge storage electrode on a predetermined upper portion such as an active region. Here, it should be noted that the charge storage electrode mask C is arranged such that the vertical and horizontal intervals (d1, d2) between the charge storage electrodes are the minimum line width intervals that can be formed in the exposure and development processes. .

FIGS. 2A to 2D show a of FIG.
FIG. 6 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting an end surface of a-a ′.

FIG. 2A shows, as described in FIG. 1, an upper portion of an active mask region (A) where a source electrode and a drain electrode of a MOSFET are formed and a gate electrode through which a gate electrode of the MOSFET passes. It is assumed that the charge storage electrode connected to the source electrode is formed in the charge storage electrode mask (C) region shown by a dotted line above the mask region (B), and an insulating layer is formed on the substrate 10 including the MOSFET. FIG. 2 is a cross-sectional view showing a state in which a layer 1, a conductive layer 2 for charge storage electrodes, and a photosensitive film 3 thereon are sequentially applied.

FIG. 2 (B) shows a mask window 4 made of glass 4A and chromium 4B for shielding light above the photosensitive film 3.
FIG. 4 is a cross-sectional view illustrating a state in which a mask 4 for a charge storage electrode on which C is formed is arranged and a part of the photosensitive film 3 is exposed to ultraviolet rays through the mask window 4C.

FIG. 2C shows that the photosensitive film 3 exposed in the above step is removed by placing it in a developing solution.
And FIG. 3B is a cross-sectional view showing a state in which a part of a conductive layer 1 for a charge storage electrode under the conductive layer is exposed. The minimum distance (d1) at which the photosensitive mask layers 3A and 3B can be formed in the above exposure and development steps is generally about 0.6.
It is within μm.

FIG. 2D shows the photosensitive film mask layer 3.
FIG. 4 is a cross-sectional view showing a state in which exposed conductive layers 2 for charge storage electrodes below A and 3B are etched to form charge storage electrodes 2A and 2B, and the photosensitive film mask layers 3A and 3B are removed.

In the prior art described above, the minimum distance (d1) between the charge storage electrodes cannot be reduced to, for example, 6 μm or less due to the minimum relationship between the exposure and development techniques.

FIG. 3 is a layout diagram in which main mask layers for manufacturing a DRAM cell having a multilayer capacitor structure according to the present invention are arranged. MOSFET
Mask A in a region where source and drain electrodes (not shown) are formed, a mask B for a gate electrode in which a gate electrode (not shown) of a MOSFET is formed long, and a predetermined upper portion between gate electrodes and an active region. A first charge storage electrode mask C1 and a second charge storage electrode mask C2 are arranged around the first charge storage electrode mask C1.
Comparing FIG. 1 with FIG. 3, the sizes of the active mask A and the mask B for the gate electrode are the same, but the sizes of the first and second charge storage electrode masks C1 and C2 are different. The area between the masks C1 and C2 for the first and second charge storage electrodes (d3 and d4) is larger than the area (d1 and d) between the masks C for the charge storage electrodes in FIG.
The drawing narrower than 2) is shown.

FIGS. 4 (A) to 4 (C) and FIGS. 5 (A) to 5 (C) show steps of cutting the bb 'end face of FIG. 3 to form a charge storage electrode. FIG.

FIG. 4A shows the upper part of the active region A where the source and drain electrodes of the MOSFET are formed and the mask region B for the gate electrode through which the gate electrode of the MOSFET passes, as shown in FIG. Masks C1 and C for the first and second charge storage electrodes illustrated by upper dotted lines
Assuming that a charge storage electrode connected to a source electrode is formed in two regions, an insulating layer 11 and a conductive layer 12 for a charge storage electrode (for example, polysilicon, single crystal silicon, or amorphous silicon) are formed on a substrate 20 including a MOSFET.
FIG. 4 is a cross-sectional view illustrating a state where a first photosensitive film 13 is sequentially applied.

FIG. 4 (B) shows in advance a first charge storage electrode mask 14 composed of glass 14A and chromium 14B for blocking light formed on one side only on the first photosensitive film 13. FIG. 6 is a cross-sectional view showing a state where only a part of the exposed first photosensitive film 13 is arranged to be exposed to ultraviolet rays only in a region where the first photosensitive film 13 is exposed.

It should be noted that, for example, the MO
If a first charge storage electrode mask having four surfaces connected to the SFET is arranged, four second charge storage electrode masks must be arranged around the four surfaces.

FIG. 4 (C) shows that the first photosensitive film 13 exposed in the above process is removed by putting it in a developing solution to form a first photosensitive film mask layer 13A, and a charge storage electrode underlying the same. A part of the conductive layer 12 is exposed, and the first photosensitive film mask layer 13 is exposed.
FIG. 3 is a cross-sectional view showing a state in which A is baked at a temperature of 100 to 150 ° C. for about 10 to 60 minutes and cured.

FIG. 5A shows that the second photosensitive film 15 is applied on the first photosensitive film mask layer 13A and the exposed conductive layer 12 to form a glass 16A and light formed only on one side. FIG. 9 is a cross-sectional view showing a state in which a second charge storage electrode mask 16 made of blocking chromium 16B is arranged at a desired distance from the periphery of four surfaces of a first photosensitive film mask layer 13A and exposed to ultraviolet rays from above.

FIG. 5B is a cross-sectional view showing a state in which the second photosensitive film 15 exposed in the above process is removed by putting it in a developing solution to form a second photosensitive film mask layer 15A. At this time, the first photosensitive film mask layer 13A has already been cured and remains.

FIG. 5 (C) shows that each of the charge storage electrodes is etched by etching the charge storage electrode conductive layer 12 in a region exposed between the first photosensitive film mask layer 13A and the second photosensitive film mask layer 15A. 12A and 12B, and the first
Photosensitive film mask layer 13A and second photosensitive film mask layer 15A
It is sectional drawing which shows the state which removed. Here, the distance d3 between the charge storage electrode 12A and the charge storage electrode 12B is set to 0.1 μm for the effective misalignment distance due to the sequential use of two masks and the margin between the charge storage electrodes 12A and 12B. 0.2 μm considering only distance 0.1 μm
Interval.

[0028]

As described above, according to the present invention, the distance between the charge storage electrodes can be reduced by about 0.4 μm in the same chip area as compared with the prior art, and the area of the charge storage electrodes is increased by about 60%. can do. Further, when the technology of the present invention is applied to a semiconductor wiring manufacturing technology, the width of the wiring and the distance between the wirings can be reduced, which can contribute to high integration.

[Brief description of the drawings]

FIG. 1 is a layout diagram in which main mask layers are arranged in order to manufacture a large number of DRAM cells having a multilayer capacitor according to the related art.

FIG. 2 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting the line aa ′ of FIG. 1;

FIG. 3 is a layout diagram in which main mask layers are arranged in order to manufacture a large number of DRAM cells having a multilayer capacitor according to the present invention.

FIG. 4 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting a line bb ′ of FIG. 3;

FIG. 5 is a cross-sectional view illustrating a step of forming a charge storage electrode by cutting a line Kbb ′ in FIG. 3;

[Explanation of symbols]

A: active mask, B: gate mask, C: charge storage electrode mask, C1: first charge storage electrode mask, C2: second charge storage electrode mask, 1 and 11: insulating layer, 2 and 1
2: Charge storage electrode conductive layer, 2A, 2B, 12A and 1
2B: charge storage electrode, 3, 13 and 15: photosensitive film
4: Mask for charge storage electrode 3A, 3B, 13A and 15A: Photosensitive film mask layer 14, 16: First and second mask for charge storage electrode

Claims (6)

(57) [Claims] Providing a substrate having a conductive layer on which a mask pattern is to be formed, forming a first photosensitive layer on the entire structure, and forming only a predetermined portion on the first photosensitive film. Arranging a first mask configured to be exposed, exposing a portion of the first photosensitive film exposed by the first mask to ultraviolet light, and placing the structure in a developer to be exposed to ultraviolet light. Removing the first photosensitive film and forming a first photosensitive film mask layer; and forming the first photosensitive film at a temperature of 100 to 150 ° C. for 10 to 60 minutes.
Hard baking for about a minute, forming a second photosensitive film on the exposed entire structure, and forming a second photosensitive film on the second photosensitive film at a predetermined distance from one side of the first photosensitive mask layer. Arranging two masks; exposing a portion of the second photosensitive film exposed by the second mask to ultraviolet light; placing the structure in a developing solution to remove the second photosensitive film exposed to ultraviolet light; (1) forming a second photosensitive film mask having a predetermined distance from one side surface of the photosensitive film mask layer to expose a conductive layer to be etched; Forming a mask pattern of the conductive layer except for the conductive layer exposed at a predetermined interval therebetween, whereby the width of the mask pattern of the conductive layer can be minimized. The symptom, the mask pattern formation method of a semiconductor device. 2. The method according to claim 1, wherein the conductive layer uses a single-crystal polysilicon layer, a silicon layer, or an amorphous silicon layer. 3. The second mask has a minimum misalignment effective distance required in a mask process from one side surface of the first photosensitive film mask and a minimum insulation interval between mask pattern widths of a conductive layer formed later. The method according to claim 1, wherein the semiconductor device is arranged in consideration of only the pattern. 4. Providing a substrate (20), and sequentially forming an insulating layer (11), a conductive layer for a charge storage electrode (12) and a first photosensitive film layer (13) on the substrate (20). Arranging a first charge storage electrode mask configured to expose only a predetermined portion on the first photosensitive film; and forming a first charge storage electrode mask on the first photosensitive film. Exposing a portion of the first photosensitive film 13 exposed by the mask 14 to ultraviolet light; removing the first photosensitive film exposed to ultraviolet light by putting the structure in a developer; Forming a film mask layer (13A) and exposing a portion of the underlying conductive layer (12) for charge storage electrodes; and curing the first photosensitive film mask layer (13A) at 100 ° C. Baking at a temperature of ~ 150 ° C for about 10-60 minutes And forming a second photosensitive layer (15) on top of the exposed entire structure, the second photosensitive layer (15) first photosensitive film mask layer on top (1
3A) arranging a second charge storage mask (16) at a predetermined distance from one side surface, and exposing a part of the second photosensitive film exposed by the second mask to ultraviolet rays. And removing the second photosensitive film (15) exposed to ultraviolet rays by putting the structure in a developer and removing a predetermined distance from one side of the cured first photosensitive film mask (13A). Forming a second photosensitive film mask layer (15A) having a conductive layer (12) for a charge storage electrode to be etched, and a predetermined distance between the first and second photosensitive film mask layers. The conductive layer for charge storage electrode (1
Forming the charge storage electrodes (12A, 12B) except for 2), whereby the charge storage electrodes (12A, 12B) are formed.
12B) a method of forming a mask pattern for a semiconductor device, characterized in that the interval between the two can be minimized. 5. The method according to claim 4, wherein the charge storage electrode conductive layer comprises a single crystal silicon layer, a polysilicon layer, or an amorphous silicon layer. 6. The second charge storage electrode mask (16).
Takes into account only the minimum misalignment effective distance required in the masking process from one side of the first photosensitive film mask (13A) and the minimum insulation interval between the charge storage electrodes (12A and 12B) formed later. 5. The method according to claim 4, wherein the mask patterns are arranged in a matrix.