JPS62165329A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the manufacturing yield of semiconductor integrated circuit device while enabling the device to be highly integrated by a method wherein, before the forming process of a conductive film or an insulating film, another process is set up to form the main surface of semiconductor substrate in the fine region below the conductive film lower than the main surface of semiconductor substrate in the rough region below the former main surface. CONSTITUTION:A conductive film 12C is formed electrically connecting to an extending part of gate electrode 8A, a source region and drain region 9B through a connecting hole 11 while covering an interlayer insulating film 10. At this time, before the forming process of the conductive film 12C, another process is set up to form the main surface of semiconductor substrate 1 in the fine region C wherein the memory cell M below the conductive film 12C is finely arranged lower than the main surface of the rough region H wherein MISFET Qn below the main surface of semiconductor substrate 1 is toughly arranged. Through these procedures, the level of the fine region L is previously lowered so that the difference in levels of photoresist films in the fine region L and the rough region H may be reduced to form the photoresist films in both regions within the focal length.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is particularly effective when applied to a semiconductor integrated circuit device having a process of forming a mask with a photoresist film. It's about technology.

[Conventional technology]

The manufacturing process of semiconductor integrated circuit devices requires a mask forming process for etching conductive films and insulating films, or introducing and diffusing impurities. For example, a mask for forming aluminum wiring is formed as follows. A photoresist (photosensitive resin) film is applied on the aluminum film. Thereafter, the photoresist film is exposed with a reticle and developed to form a mask in the unexposed or exposed areas.

Regarding exposure (light lithography) technology, for example, see Science Forum Co., Ltd.'s Ultra LSI Device Handbook, published on November 28, 1980, p.139.
- It is described in P143.

[Problem that the invention seeks to solve]

In the above-mentioned mask forming process, the inventor of the present invention

It has been found that the following problems arise.

The photoresist film coated on the aluminum film partially has an elevation difference (difference in height of the photoresist film from the substrate). In other words, in a photoresist film, an area where semiconductor elements are densely arranged on the underlying layer or an area with a large number of conductive films or insulating films (hereinafter referred to as the actual area) is different from an area where semiconductor elements are arranged sparsely on the underlying layer. This is higher than areas where the number of films is reduced or areas where the number of films is small (hereinafter referred to as sparse areas). This is because, during film exposure, the photoresist is formed outside the depth of focus (an allowable range in which a pattern can be resolved even if the photoresist film deviates from the focal plane in the optical axis direction). For this reason,
Since there are portions on the photoresist film where the desired pattern is not resolved, the manufacturing yield is reduced due to mask defects. This problem becomes more noticeable as the depth of focus becomes smaller due to higher integration.

An object of the present invention is to provide a technique that can improve the manufacturing yield of semiconductor integrated circuit devices.

Another object of the present invention is to provide a technology that improves the manufacturing yield of semiconductor integrated circuit devices and enables high integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

A method for manufacturing a semiconductor integrated circuit device comprising the steps of applying a photoresist film on a predetermined conductive film or insulating film and exposing the photoresist film to form a mask, the method comprising forming the conductive film or insulating film. The present invention is characterized by comprising a step of forming the main surface of the semiconductor substrate in which the underlying layer is a real region to be lower than the main surface of the semiconductor substrate in which the underlying layer is in the sparse region.

[Effect]

According to the above-mentioned means, it is possible to reduce the elevation difference between the photoresist films in both regions and form the photoresist films in both regions within the depth of focus, thereby preventing mask defects and improving manufacturing yield. can do.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below using an example in which the present invention is applied to a semiconductor integrated circuit device (hereinafter referred to as DRAM) equipped with an open bit line type dynamic random access memory.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

A memory cell array of a DRAM that is an embodiment of the present invention is shown in FIG. 1 (a plan view of main parts), and a cross section taken along the line ■-■ in FIG.
A cross section (right side) of T is shown in FIG. In FIG. 1, insulating films other than the field insulating film provided between the conductive films are not shown in order to make the configuration of this embodiment easier to understand. Moreover, FIG. 2 shows a real area where memory cells are arranged on the left side,
The right side shows a sparse area where MISFETs are arranged.

In FIGS. 1 and 2, 1 is a p-type semiconductor substrate (or well region) made of single crystal silicon, 2 is a field insulating film, and 3 is a p-type channel stopper region.

The field insulating film 2 and the channel stopper region 3 are provided on the main surface of the semiconductor substrate 1 between the semiconductor element formation regions, and are configured to electrically isolate the semiconductor elements.

A memory cell M of the DRAM is formed of a series circuit of an information storage capacitive element C and a switching element Q in a real area formed on the lower main surface of the semiconductor substrate 1.

The information storage capacitive element C is composed of an MIS type capacitive element including a semiconductor substrate 1, a dielectric film 4, and a plate electrode 5. 6 is an insulating film that covers the plate electrode 5.

The switch element Q includes a semiconductor substrate 1, a gate insulating film 7A,
It has an MIS type structure consisting of a gate electrode 8A.

9A is an n1 type semiconductor region, which is electrically connected to one end of the switch element Q and forms a data line DL. 10 is an interlayer insulating film, 11 is a connection hole, and 12 is a word line WL.

The word line 12 is connected to the gate electrode 8A through the connection hole 11.
is electrically connected to a portion extending on the plate electrode 5, and is made of a material with a low specific resistance value, such as an aluminum film, for example.

In order to increase the capacity, the memory cells M configured in this manner are configured with the minimum processing dimensions in the manufacturing process, and are densely arranged. In addition, in order to reduce the planar area of the memory cell M,
It is constructed by partially overlapping the information storage capacitive element C and the switching element Q, and includes a conductive film (5, 8A) and an insulating film (
6, etc.).

M I S F E T Q n constituting the peripheral circuit is formed in a line region H formed by the high main surface of the semiconductor substrate 1 . That is, M I S F E T Q
n represents the semiconductor substrate 1, the gate insulating film 7B, and the gate electrode 8.
B, n-type source region and drain region 9B. A wiring 12B is electrically connected to the source region or drain region 9B through the connection hole 11.

The MISFETQn configured in this manner is arranged sparsely or has a smaller number of films than the memory cells M.

Next, a method for manufacturing the DRAM will be explained using FIGS. 3 to 7 (cross-sectional views for each manufacturing process).

First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared. Then, a silicon oxide film is formed by oxidizing the main surface of the semiconductor substrate 1 in the memory cell array formation region that will become the phase region. This silicon oxide film has M
It can be formed by forming an oxidation-resistant mask (silicon nitride film) in the ISFETQn formation region and performing oxidation using this mask.

The silicon oxide film is formed to have a thickness of, for example, about 1.0 to 2.0 [μm] so that the difference in elevation of the photoresist film, which will be described later, between the phase region and the line region 14 can be reduced.

Thereafter, the silicon oxide film is removed, and as shown in FIG. 3, the main surface of the semiconductor substrate 1 in the phase region is formed low, and the main surface of the semiconductor substrate 1 in the line region H is formed high.

After the step of forming the phase region and line region H shown in FIG. 3, a field insulating film 2 and a p-type channel stopper region 3 are formed on the main surface of the semiconductor substrate 1 between the semiconductor element forming regions.

After this, as shown in FIG.
A dielectric film 4 is formed on the main surface of the semiconductor 8 integrated substrate 1 in the area where the information storage capacitive element C is formed. Dielectric film 4
is formed using, for example, a silicon oxide film formed by oxidation technology.

After the step of forming the dielectric film 4 shown in FIG.

A plate electrode 5 is formed on the dielectric film 4 on the area where the information storage capacitive element C is formed. The plate electrode 5 is formed, for example, by etching a polycrystalline silicon film doped with impurities to reduce resistance into a predetermined shape. In the step of forming this plate electrode 5, the information storage capacitive element C is formed.

Furthermore, in the step of forming the plate electrode 5, the dielectric film 4 in the region where the switching elements Q, MT, and SFETQn are formed is removed.

Then, as shown in FIG. 5, switch elements Q and M
Gate insulating films 7A and 7B are formed on the main surface of semiconductor substrate 1 in the ISFETQn formation region.

Then, the insulating film 6 covering the plate electrode 5 is formed in the same manufacturing process as the process of forming the gate insulators [7A and 7B]. The gate insulating films 7A, 7B and the insulating film 6 are, for example,
It is formed using a silicon oxide film formed using oxidation technology.

After this, as shown in FIG. 6, gate insulating films 7A and 7
Gate electrodes 8A and 8B are formed on predetermined portions of B, respectively. The gate electrodes 8A and 8B are formed of, for example, a polycrystalline silicon film doped with impurities that reduce resistance. In the memory cell M formation region, the switch element Q is formed in the step of forming the gate electrode 8A.

After the step of forming gate electrodes 8A and 8B shown in FIG.
Introduced into the main surface of the As a result, a RI type semiconductor region 9A used as the data line DL and an RI'' type source region and drain region 9B are formed.
Qn is formed.

Thereafter, an interlayer insulating film 10 is formed on the entire surface, and predetermined portions of the interlayer insulating film 10 and the like are removed to form connection holes 11.

Then, through the connection hole 11, it is electrically connected to the extended portion of the gate electrode 8A, the source region and the drain region 9B,
Also, a conductive film 12C is formed to cover the interlayer insulating film 10. The conductive film 12C is formed of, for example, an aluminum film having a small specific resistance value.

Thereafter, a positive type photoresist film is applied to form a mask for patterning the conductive film 12C into a predetermined shape. Then, the photoresist film is exposed using a reticle, and as shown in FIG.
A non-exposed area (portion not irradiated with light and not exposed) 13A is formed.

The photosensitive portion 13A is removed by development, and the non-photosensitive portion 13B is not removed by development and forms an etching mask.

A method for manufacturing a DRAM including the step of exposing a photoresist film to form a mask, in which the conductive film 1
2C, the main surface of the semiconductor substrate 1 in the dense region where the memory cells M underlying the conductive film 12c are densely arranged is replaced with the line region H where the MI1l-8FETQn underlying the conductive film 12c is sparsely arranged. Since the height of the dense area is lowered in advance by forming it lower than the main surface of the line area, the height difference of the photoresist film between the dense area and the line area H is reduced, and both A photoresist film of a region can be formed within the depth of focus. Therefore, mask defects can be prevented and manufacturing yields can be improved. In particular, when a predetermined film (for example, an insulating film) is formed during the manufacturing process in dense areas in order to reduce the elevation difference of the photoresist film, the thickness of the insulating film between conductive layers increases, resulting in contact holes etc. Since etching becomes a major problem, it is more effective to carry out the process as in the present invention.

Furthermore, the difference in elevation of the photoresist film between the dense area and the line area H can be reduced, and both areas can be exposed at once, so productivity can be improved.

In addition, the difference in elevation of the photoresist film between the dense area and the line area H can be reduced, and the depth of focus can be reduced.
A mask with minute dimensions can be formed, and the degree of integration can be improved.

After the step of forming the photosensitive area 13A and the non-photosensitive area 13B, development is performed to remove the photosensitive area 13A, and the non-photosensitive area 1
3B is left to form a mask. Then, using this mask, the conductive film 12G is etched, and the first
As shown in the figure and FIG. 2, a word line (WL) 12A and a wiring 12B are formed.

In the step of forming this word line 12A, the memory cell M is completed, and by performing a series of these manufacturing steps, the DRAM of this embodiment is completed.

The invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

For example, in the present invention, a negative type photoresist film may be used.

Further, in the present invention, in the mask forming step for forming the gate electrodes 8A and 8B, the main surface of the semiconductor substrate 1 in the dense region may be formed low so that the height difference of the photoresist film is minimized.

Further, in the present invention, an epitaxial layer may be laminated on the main surface of the semiconductor substrate 1 in the sparse region H, and the main surface of the semiconductor substrate 1 in the dense region H may be formed lower.

Furthermore, the present invention can be applied not only to photolithographic techniques that perform exposure with ultraviolet rays and deep ultraviolet rays, but also to photolithographic techniques that perform exposure with lasers, X-rays, and electrobeams. In particular, photolithography technology that performs exposure using X-rays and electrobeams can make the distance between the reticle that performs close exposure and the photoresist film uniform.

Further, the present invention can also be applied to a mask forming process for etching an insulating film.

Furthermore, the present invention is not limited to DRAMs, but can be widely applied to semiconductor integrated circuit devices having dense regions and sparse regions.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical ones are briefly explained below.

A method for manufacturing a semiconductor integrated circuit device comprising the steps of applying a photoresist film on a predetermined conductive film or insulating film and exposing the photoresist film to form a mask, the method comprising forming the conductive film or insulating film. By including a step of forming the main surface of the semiconductor substrate with a dense region as the base lower than the main surface of the semiconductor substrate with the sparse region as the base, the height of the photoresist film in both regions can be lowered. Since the difference can be reduced and the photoresist films in both regions can be formed within the depth of focus, mask defects can be prevented and manufacturing yields can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of a DRAM memory cell array according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the MISFET constituting the memory cell and peripheral circuit, taken along the line ■-■ in FIG. FIG. 3 to FIG. 7 show a DRAM which is an embodiment of the present invention.
(7) Cross-sectional view showing 1 degree for each manufacturing process'''''7'・
In the figure, 1... semiconductor substrate, 4... dielectric film, 5... plate electrode, 6... insulating film, 7A, 7B
... Gate insulating film, 8A, 8B... Gate electrode, 9
A... Semiconductor region, 9B... Source region or drain region, 10... Interlayer insulating film, 11... Connection hole, 1
2A...Word line, 12B...Wiring, M...Memory cell, C...Capacitive element for information storage, Qn...MI
SFET, Q...Switch element. −16=

Claims (1)

[Claims] 1. Coating a photoresist film on a conductive film or an insulating film,
A method for manufacturing a semiconductor integrated circuit device comprising the step of exposing the photoresist film in a predetermined shape to form a mask pattern, the method comprising the step of forming a mask pattern by exposing the photoresist film in a predetermined shape. The first main surface of the semiconductor substrate in the area where the underlying semiconductor elements are arranged densely or the area where the number of underlying films is large is replaced by the area where the underlying semiconductor elements are sparsely arranged or the area where the number of underlying films is small. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming the semiconductor integrated circuit device lower than the second principal surface of the device. 2. The first main surface is formed by selectively oxidizing the main surface of the semiconductor substrate in the formation region to form a silicon oxide film, and removing the silicon oxide film to form the first main surface lower than the second main surface. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 3. The first main surface is formed by selectively laminating an epitaxial layer on the second main surface of the semiconductor substrate, and is formed lower than the second main surface. A method for manufacturing a semiconductor integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductive film forms a wiring, an electrode, or a semiconductor element.