JPH02192724A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH02192724A
JPH02192724A JP1292389A JP1292389A JPH02192724A JP H02192724 A JPH02192724 A JP H02192724A JP 1292389 A JP1292389 A JP 1292389A JP 1292389 A JP1292389 A JP 1292389A JP H02192724 A JPH02192724 A JP H02192724A
Authority
JP
Japan
Prior art keywords
insulating film
region
hole
contact hole
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1292389A
Other languages
Japanese (ja)
Inventor
Kazuhiro Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1292389A priority Critical patent/JPH02192724A/en
Publication of JPH02192724A publication Critical patent/JPH02192724A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the interval width between a contact hole and other region as much as possible and to improve the integration of a device by a method wherein after the contact hole is opened in an interlayer insulating film, an insulating film is formed on the side well surface in the hole.
CONSTITUTION: A gate oxide film 2 and gate electrodes 3 are formed on a substrate 1 and an impurity is implanted in the surface of the substrate 1 and is diffused to form a diffused region 4. Then, an interlayer insulating film 5 is provided on the whole surface, a contact hole 6 is opened and at the same time, a connecting part of the region 4 is exposed. Moreover, after an insulating film is applied on the whole surface, the insulating film is removed by anisotropic etching excluding an insulating film 7b on the sidewall surface in the hole 6. Moreover, an Al wiring layer 8 is provided on the film 5 and is connected to the region 4 through the hole 6.
COPYRIGHT: (C)1990,JPO&Japio
JP1292389A 1989-01-20 1989-01-20 Semiconductor device and its manufacture Pending JPH02192724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1292389A JPH02192724A (en) 1989-01-20 1989-01-20 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292389A JPH02192724A (en) 1989-01-20 1989-01-20 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH02192724A true JPH02192724A (en) 1990-07-30

Family

ID=11818857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1292389A Pending JPH02192724A (en) 1989-01-20 1989-01-20 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH02192724A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6921876B2 (en) 2003-05-29 2005-07-26 Fanuc Ltd Method for adjusting nozzle gap

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6514811B2 (en) 1993-12-17 2003-02-04 Stmicroelectronics, Inc. Method for memory masking for periphery salicidation of active regions
US6661064B2 (en) 1993-12-17 2003-12-09 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6921876B2 (en) 2003-05-29 2005-07-26 Fanuc Ltd Method for adjusting nozzle gap

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