JPS59182558A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve integration by means of vertically supplying a substrate with an electric charge by a method wherein, in a memory utilizing a memory cell comprising a single transistor and a single capacitor as minimum unit, a channel region pierced by a word line is provided on the part where the word line and a bit line intersect while one end and the other end are respectively abutted against an electric charge storing capacitor and a bit line. CONSTITUTION:A low resistance Si layer 32 to be a bit line is deposited on an insulating substrate 31 to form an Si layer 33 to be a channel region on the central part of the surface of the layer 32. Next the layer 33 is encircled by an insulating film 34 wherein a word line 35 is buried while a capacitor comprising a metal layer 36 to be one side electrode and a metal oxide film 37 with high permittivity is formed to coat the oxide film 37 with a metal grounding electrode 38. Through these procedures, a memory with integration much higher than a plane memory may be produced by means of vertically supplying the substrate 31 with electric charge being stored as memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic memory suitable for high integration.

[Background technology]

In a conventional dynamic memory composed of a single transistor and a single capacitor, as shown in FIG. There are limits to the direction of integration. In Figure 1, figure number 1
1 is the substrate, 12 is the gate insulating film of MO8F'ET, 13
14 represents a low resistance diffusion layer, 14 represents a capacitor insulating film, 15 represents a word line, and 16 represents a bit line.

Conventionally, increasing the degree of integration has been achieved by reducing the size and shape of devices at a certain rate, but various problems have emerged as the charge storage capacity decreases due to miniaturization of devices. Examples include a decrease in the signal-to-noise ratio and soft errors caused by alpha rays. For this reason, the charge storage capacitor section cannot be made very small, which is an obstacle to high integration.

One solution to the above-mentioned problem is to reduce the area occupied by the device by directing the charge perpendicular to the substrate rather than parallel to it. SI as shown in Figure 2
'J' (Static Induction Tran
sistorl structure (for example, Patent Publication: 1983)
-355911° In this device, since charges flow perpendicularly to the substrate 21 from the source electrode 23 provided on the bottom surface of the substrate toward the drain electrode 27, the device can be reduced in size compared to a planar structure. Here, 22 is the junction of the gate part,
24 is a gate electrode, 25 is an insulator, and 26 is a drain junction. When this structure is used, the dimensions of the channel region can be reduced by improving the processing accuracy of the substrate, making it suitable for high integration. However, complicated manufacturing steps are required, such as a process for embedding the bonding portion 22 in contact with the gate electrode 24 inside the substrate.

[Purpose of the invention]

The purpose of the present invention is to reduce the area of the element and improve the degree of integration in a semiconductor memory device by causing charges stored as memory to flow perpendicularly to the substrate.

[Summary of the invention]

The feature of the memory cell according to the present invention is that, as shown in FIG. 3, a channel portion is provided at the intersection of the word line and the pitch so as to penetrate the word line, so that charges flow perpendicularly to the substrate. The objective is to reduce the area occupied by the element. Another feature is that a metal oxide with a high dielectric constant is used as the dielectric material of the capacitor in order to prevent the amount of stored charge from decreasing due to miniaturization of the device.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the invention.゛Here,
The semiconductor memory cell includes a low resistance 5i 32 formed on an insulating substrate 31h to serve as a bit line, an S layer 33 epitaxially grown on Si 32 to serve as a channel, and
The capacitors 36, 37, and 38 are formed thereon. The capacitor is formed on an insulating film 34 that is insulated from the word line 35, and one end of the capacitor is connected to S at the opening of the insulating film.
It is in contact with the i layer. The dielectric material of the capacitor is a material obtained by oxidizing the surface of the metal 36 that becomes one electrode of the capacitor.
7, or using an oxide film deposited on top of the metal layer. 38 is the other polarization of the capacitor and is at ground potential.

Next, an example of manufacturing the semiconductor device shown in FIG. 3 will be shown using FIG. 4.

First, as shown in FIG. 4(a), a low-resistance n-type 5i 42 that will become a bit line is epitaxially grown on an insulating single-crystal substrate 41 such as a single-crystal alumina substrate. When it is desired to avoid auto-doping of impurities from an insulating substrate to a Si layer, a known SIM is used in which oxygen atom ions are implanted into a single crystal SI substrate to form an insulating film layer inside the substrate.
It is also possible to use an OX substrate and lower the resistance of single crystal Si on the insulating film layer. Next, as shown in FIG. 4(b), a resist 43 is applied and the low resistance Si layer is etched, leaving only the portion that will become the bit line. Furthermore, as shown in FIG. 4(C), an insulating film 44 such as 5jCh is formed to a thickness approximately equal to that of the low resistance Si layer 42 using a low-temperature evaporation method such as the snow ivy method while leaving the resist 43. Deposit with. After forming the insulating film 44, the resist is ashed in oxygen plasma, and only one layer of the insulating film on the resist is removed. Further, it is exposed to an oxygen atmosphere to oxidize the exposed surface of the bit line 42 to form a structure as shown in FIG. 4(d). In the above process, the bit line is buried in the oxide layer 1i, and the surface becomes almost flat. Next, in order to form a single crystal Si layer in contact with the bit line and to serve as a channel, a portion of the oxide film on the bit line is removed, and the Si layer 45 is selectively removed as shown in FIG. 4(e).
grown epitaxially. To simplify the drawing, in the structure shown in FIG. 4(e), ABCD
Only the cross section cut at is shown. After selective epitaxial growth of MO8F'ET.

Si is grown in a high temperature acidic atmosphere to form a gate insulating film.
The surface of layer 45 is lightly oxidized. This is shown at 44' in FIG. 4(f). Next, in order to facilitate ohmic contact with the metal layer that will become one electrode of the charge storage capacitor, impurity ions are implanted through the oxide film as shown at 46 in FIG. Lower resistance. MO8F' to cover the protrusion made in the above steps.
A metal layer 47 is deposited which will become the word line of the ET. This is shown in FIG. 4(h). At this time, in order to improve adhesion between the side wall of the protrusion and the word line, a method with good step coverage, such as a low-pressure CDD method, is used to form the metal layer.

When a film deposited on a stepped portion is etched using a dry etching method capable of anisotropic etching, the portion deposited on the side wall of the stepped portion generally remains. Utilizing this phenomenon, a word @47 surrounding the protrusion is formed as shown in FIG. 4(i). Next, as shown in FIG. 2G4 (j), an I-interlayer 48 such as 8102 is deposited using a known bias sputtering method or the like to flatten the surface.

Furthermore, a hole is made in a part to expose the low resistance Si layer 46.

Next, as shown in FIG. 4(k), the oxide', Tf
A metal 49 having a high j'cIt rate, such as tantalum, niobium, or titanium hafnium, is deposited and patterned so that it comes into ohmic contact with the low resistance layer 3i and forms one electrode of the capacitor. The surface of this metal layer is thinly oxidized using a known anodic oxidation method to form a dielectric material 50 of a charge storage capacitor as shown in FIG. A metal 51, which will become the other electrode of the capacitor, is deposited over the entire surface of the substrate.

Furthermore, although the metal 49 is used in this embodiment, polycrystalline Si or the like may be used instead of the metal 49, and the dielectric insulating film 50 may be deposited by a sputtering method, an anodic oxidation method, or the like.

〔Effect of the invention〕

By using the semiconductor device described in the present invention, it is possible to create a memory with a much higher integration density than the planar memory shown in FIG. 1. Since the word line covers the outer periphery of the protruding Si layer that becomes the channel, the effective ratio of channel width to channel length can be increased, which has a great effect on improving the characteristics of MO8F'ET. Furthermore, since the capacitor for storing the load is located on the top floor, soft errors due to incidence of α particles are less likely to occur.

Furthermore, since a high dielectric constant material such as mental oxide is used as the dielectric of the charge storage capacitor, a capacitor with a large amount of stored charge can be obtained even with a small area.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional planar dynamic memory.
FIG. 2 is a cross-sectional view of an electrostatic induction transistor that allows charges to flow perpendicularly to the substrate, and FIG. 3 is a cross-sectional view showing a memory cell of the present invention. Insulating film, 35... Word line, 36... Metal, 37...
・Oxide film of metal 36, 37... Gold χ 4 (α) Pregnancy 1 (b) (h) 47

Claims (1)

[Claims] 1. In a semiconductor memory device whose minimum unit is a memory cell composed of a single transistor and a single capacitor, the word line is connected directly to the bit line at the intersection of the word line and the bit line. 1. A semiconductor memory device comprising a channel region, one end of which is in contact with a charge storage capacitor, and the other end of which is in contact with a bit line. 2. In a semiconductor memory device composed of a single transistor and a single capacitor, the semiconductor according to claim 1, wherein the bit line is made of single crystal silicon formed on an insulating substrate. Storage device. 3. Claims characterized in that in a semiconductor memory device composed of a single transistor and a single capacitor, a metal oxide with a relative conductivity of 4 or more is used as a dielectric for a charge storage capacitor. 2. The semiconductor memory device according to item 1. 4. Claim 1, characterized in that in a semiconductor memory device configured with a single transistor and a single capacitor, the charge storage capacitor section is stacked on both a bit line and a word line. The semiconductor storage device described above.