JPS62105473A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device whose interelectrode capacitance is small, by making a second gate electrode encroach in a first gate electrode as far as a position where P-N junction planes of source region and drain region come into contact with the semiconductor substrate. CONSTITUTION:An N-type impurity diffusion region of source 11b and an N-type diffusion region of drain 11a are formed separately on a main surface side of a P-type semiconductor substrate 10 made of silicon. A first gate electrode 14 made of molybdenum silicide is formed on a gate insulating film 13 on the main surface of the P-type semiconductor substrate 10, so as to span across the source region 11b and the drain region 11a. A second gate electrode made of polysilicon is formed under the gate electrode 14 contacting with it via the gate insulating film 13, in the manner in which the gate electrode is made to encroach in the gate electrode 14 as far as a position where the P-N junction planes of source region 11b and drain region 11a come into contact with the main surface of the semiconductor substrate 10. The overlap between the im purity diffusion regions 11a, 11b and the gate part is decreased, so that the interelectrode capacitance of gate.source drain can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to highly integrated memories such as dynamic memories.

[Conventional technology]

In high-integration memories such as dynamic memories using this type of MO8) run sister, in recent years, in order to increase the density, miniaturization of elements and wiring has been attempted.

Therefore, in order to maintain and improve the high-speed operation of the device, the gate electrode material also needs to have a low resistance, so instead of the conventional single layer polysilicon film, metal silicide such as molybdenum silicide or tiegesten silicide is used on the polysilicon film.・There is a trend toward creating a double gate structure with a lead film and achieving lower resistance.

However, the increase in the number of elements associated with higher density memory has resulted in an increase in the parasitic capacitance between the gate electrode and the source/drain electrode compared to the past, which has become an impediment to high-speed operation of the device.

FIG. 6 shows an example of a conventional gate structure in a semiconductor device. In the figure, (1) is a silicon substrate, (2) is a diffusion layer, (3) is an element isolation oxide film, (4) is a gate oxide film,
(5) is a polysilicon film, (6) is a molybdenum silicide film, and the polysilicon film (5) and the molybdenum silicide film (6) constitute a gate electrode (7).

When manufacturing a semiconductor device with such a structure, first, an element isolation oxide film (3) and a gate oxide film (4) are formed on the semiconductor substrate (1), and then a film is formed on the entire surface of the semiconductor substrate (1). Polysilicon film (5) and molybdenum silicide film (6)
) to form. Next, after forming a resist pattern in the gate electrode formation region on this molybdenum silicide film (6), the molybdenum silicide film (6) is first removed by isotropic plasma etching, and then anisotropic plasma etching is performed. The polysilicon film (5) is removed by a method. After that, impurities are implanted into the semiconductor substrate (1) using the ion implantation method, and then the impurities are diffused using the thermal diffusion method to impurity diffusion 71.
1 (2) to obtain something as shown in FIG.

[Problem that the invention seeks to solve]

Since the conventional semiconductor device is as described above, the diffusion layer (2
), a diffusion layer (2) below the electrode (7) is formed.
), the capacitance between the polysilicon film (5) and the diffusion layer (2) increases, and as a result, the gate electrode (7)
) There was a problem in that the parasitic capacitance to the wiring increased and the high-speed operation of the device was inhibited.

This invention was made to solve the problems mentioned in 1.1. The purpose is to obtain a semiconductor device with small capacitance between electrodes.

[Means for solving problems]

A semiconductor device according to the present invention includes a source region and a drain region formed on one main surface of a semiconductor substrate at a distance from each other, and having a source region and a drain region of opposite conductivity type to the semiconductor substrate, and a gate insulating film on one main surface of the semiconductor substrate. A first gate electrode formed across the source region and the drain region, and a first gate electrode provided on the lower side of the electrode and in contact with the first gate electrode through the gate insulating film; and a second gate electrode formed by biting into the first gate electrode to a position where a Pn junction surface of the region and the drain region contacts one main surface of the semiconductor substrate.

[Effect]

In this invention, the second gate electrode is formed by biting into the first gate electrode to a position where the Pn junction surfaces of the source region and the drain region contact one main surface of the semiconductor substrate. , since there is almost no overlap between the second gate electrode and the source and drain regions,
Capacitance between electrodes can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 00 is a P-type semiconductor substrate made of silicon;
(lla)l (ub) are source and drain N-type impurity diffusion regions formed spaced apart from each other on one main surface side of the semiconductor substrate aCt; 1 is provided under and in contact with the gate electrode α4, and the I'N junction surface of the two former source regions (11, b) and drain regions (lla) is connected to one main surface of the semiconductor substrate αQ described in -. A second gate electrode made of polysilicon is formed by penetrating into the first gate electrode 0 until it comes into contact with it, and 0→ is the gate insulating film on the -main surface of the semiconductor substrate (1). 6) A first layer made of molybdenum silicide provided on the source region (11b) and drain region (Ila) and formed over the source region (11b) and drain region (Ila).
gate electrode, OQ is the source and drain region (t
lb), (lla) and the first and second gate electrodes (
A method for manufacturing the semiconductor device constructed as described above will be described in detail with reference to FIGS. 1 to 5.

First, as shown in FIG. 2, after forming an element isolation oxide film 0 and a gate oxide film 03 on a silicon substrate 00, a polysilicon film 0 and a molybdenum silicide film 041 for gate electrodes are formed. A resist pattern αQ is formed in the second gate electrode formation region by applying Q. and performing exposure and development.

Thereafter, using the resist pattern α as a mask, etching is carried out by an anisotropic plasma etching method to achieve what is shown in FIG. Furthermore, when etching is performed for a predetermined time using the isotropic plasma etching method, due to the difference in etching rate between molybdenum silicide (I◆) and polysilicon (A), as shown in Figure 4, the polysilicon film is etched. Since the etch rate is fast, a recessed part is formed.After that, in the ion implantation method, the implantation layer (l) shown in Figure 5 is used.
la), (11b) was made and heat treated at a high temperature of 1000°.
When C is heated in N2 for 80 minutes, the impurity diffusion region (x
la), (1xb) are formed.

In the method for manufacturing a double gate structure of the present invention, as shown in FIG.
) almost coincides with the polysilicon edge of the first gate conductive film (2), reducing the size of υ that overlaps with the gate part as in the conventional method, and reducing the capacitance between the gate and source/drain electrodes. can be reduced.

In this example, the double gate structure was etched by adding isotropic etching after anisotropic etching to achieve the bite shape, but this method was not used and various methods were used. Possible variations are:

Further, in the above embodiment, the second gate electrode (2) is made of polysilicon and the first gate electrode 0Φ is made of molybdenum silicide, but other materials may be used.
It is preferable that the etching rate of the first gate conductive film 041 is slower than the etching rate of the second gate conductive film θ. .

〔Effect of the invention〕

As explained above, in this invention, the second gate electrode is
Since the I)N junction surfaces of the source and drain regions are embedded into the first gate conductive film to the point where they are in contact with the surface of the semiconductor substrate, the contact between the second gate electrode and the source and drain regions is reduced. Since there is almost no overlap, the interelectrode condition can be reduced, which has the effect of enabling high-speed operation of the device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention, and FIGS. 2 to 5 are cross-sectional views of the semiconductor device showing the manufacturing method of the semiconductor device shown in FIG. FIG. 6 is a sectional view showing a conventional semiconductor device. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A source region and a drain region formed on one main surface of the semiconductor substrate to be spaced apart from each other and having a conductivity type opposite to that of the semiconductor substrate; a first gate electrode formed across the source region and the drain region; a first gate electrode provided under and in contact with the first gate electrode via the gate insulating film; and a Pn junction surface of the source region and the drain region. A semiconductor device comprising: a second gate electrode that is formed by biting into the first gate electrode to a position where it contacts one main surface of the semiconductor substrate. (2) The semiconductor device according to claim 1, wherein the second gate electrode is made of polysilicon and the first gate electrode is made of a metal silicide film. (3) The semiconductor device according to claim 2, wherein the first gate electrode is made of a molybdenum silicide film.