JPH08139205A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To assure electrical continuity of a conductive layer as a whole for application of substrate bias and reliably apply a substrate bias by introducing impurity for adjusting a threshold voltage to the lower part of the region which will become a gate electrode of a transistor and simultaneously introducing impurity, also to a conductive layer region, having the same conductive characteristic as the impurity for adjusting threshold voltage. CONSTITUTION: An N-type well 2 is formed within a silicon substrate 1 and moreover a field shield region 3 is also formed. Next, a gate oxide film 4 is formed to a region where the field shield region 3 is not formed and the impurity for adjusting a threshold voltage is infected to the regions 17, 18. Simultaneously, impurity is also introduced into the part which will become the conductive regions 7, 8 in order to apply a substrate bias. A polysilicon layer is formed on a P-type silicon substrate 1 and a gate electrode 5 of a P-type transistor 11, a gate electrode 15 of an N-type transistor 12 and a wiring 13 are formed simultaneously on the P-type silicon substrate 1. Thereby, electrical continuity of the conductive layer as a whole for application of substrate bias can be assured and the substrate bias can be applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a plurality of transistors whose gate electrodes are connected to each other and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device having a transistor having a CMOS structure used in a peripheral circuit of a DRAM or the like is constructed as shown in FIGS. 1 (a) and 1 (b). That is, the n-type well 22 is formed in the p-type silicon substrate 21.
And a p-type transistor 3 is formed in the well 22.
5 is formed. N at the position adjacent to the well 22
Type transistor 36 is formed. Between the transistor 35 and the transistor 36, the transistor 35
Conductive layer regions 27 and 28 for applying a substrate bias are provided so as to surround the substrate. The conductive layer region 27 located inside the well 22 is p-type, and the conductive layer region 28 located outside the well 22 is n-type.

Next, a method of forming such a semiconductor device will be described. First, as shown in FIG. 2A, a well 22 of the first conductivity type (n type) is formed in a silicon substrate 21, and a field shield 23 having a predetermined pattern is formed around the well 22. Next, as shown in FIG. 2B, a gate oxide film 24 is formed by thermal oxidation, and an impurity for adjusting a threshold voltage is introduced below a region to be a gate electrode. Further, as shown in FIG. 2C, after forming a polysilicon layer on the entire surface, the gate oxide film 24 and the polysilicon layer are removed by etching to form a gate electrode 25. Then, as shown in FIG. 2D, an impurity is sequentially introduced into the source / drain regions 26 of the respective transistors 35 and 36, and at the same time, a region forming a conductive layer having a shape surrounding the well 22 for applying a substrate bias. Impurities are also introduced into 27 and 28. Then, as shown in FIG. 1 (b),
After forming the insulating layer 29 and opening the contact hole 30, the gate electrodes 25 of both transistors 35 and 36 are connected to each other, and, for example, an aluminum wiring layer 31 is patterned to connect them to an external circuit (not shown). .

[0004]

In the above structure, since the aluminum wiring layer 31 and the gate electrode 25 are connected via the contact hole 30, the contact hole in the gate electrode 25 is formed. It is necessary to secure a large area for the portion to be processed, which causes a problem that the element becomes large and the chip integration efficiency is reduced.

Therefore, when patterning the gate electrode 25, it is conceivable that a wiring is formed of polysilicon so as to connect the gate electrodes 25 of both transistors 35 and 36 at the same time. By doing so, at least one contact hole 3 of the transistors 35 and 36 is formed.
Since it is not necessary to open 0, it is not necessary to secure a large area for the portion where the contact hole 30 is formed.

However, as described above, the gate electrode 25 is provided with a conductive layer before the impurities are introduced into the source / drain regions 26, that is, a conductive layer for applying a substrate bias so that the impurities are not unnecessarily introduced into the channel region. Area 2
Since it is formed before introducing impurities into 7, 28, the conductive layer region 2 of the portion where the wiring is laminated by polysilicon is formed.
Impurities cannot be introduced into 7 and 28, and conduction cannot be ensured in those portions, which causes a problem that the substrate bias cannot be successfully applied.

The present invention has been made in view of the above-mentioned problems of the prior art, and its main purpose is to apply a substrate bias surely and to provide a wide area for opening a contact hole. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which it is not necessary to secure each gate electrode.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a plurality of MOS transistors having gate electrodes connected to each other and a substrate bias applying conductive layer provided between the transistors. A method of manufacturing a semiconductor device, comprising a step of forming a gate oxide film, a threshold voltage being simultaneously applied to a region to be a channel region under a gate and a region to be a conductive layer for applying a substrate bias located between the transistors. The process of introducing impurities for adjustment,
The process of forming a polysilicon layer on the gate oxide film and the patterning of the polysilicon layer and the gate oxide film form a gate electrode of each transistor and a wiring for connecting the gate electrode in the same layer. The process of doing
And a step of simultaneously introducing impurities into the source / drain region, the gate electrode, the wiring, and the portion to be the conductive layer for applying the substrate bias.

By introducing the impurity for adjusting the threshold voltage below the region to be the gate and at the same time introducing the impurity also in the conductive layer region for applying the substrate bias, the source / drain regions are then removed. Even if the wiring pattern is formed on the conductive layer before the introduction of the impurity into the conductive layer, the conductive layer can be properly ensured to be conductive and the substrate bias can be surely applied.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION As one embodiment of a semiconductor device of the present invention, a CMO as shown in FIGS. 3 (a) to 3 (c).
A pair of S-structure transistors (p-type transistor 1
A semiconductor device having 1 and n-type transistors 12) will be described.

In this semiconductor device, the p-type silicon substrate 1 is used.
An n-type well 2 is formed in the. The well 2 has a gate electrode 5 and a p-type source / drain region 6 as shown in FIGS. 3 (a) and 3 (c).
Type transistor 11 is formed, and FIG.
As shown in (b), an n-type transistor 12 including a gate electrode 15 and n-type source / drain regions 16 on the p-type silicon substrate 1 adjacent to the well 2 is the same as the transistor 11. It is formed in a shape. Further, in this embodiment, both the p-type transistor 11 and the n-type transistor 12 have p-type and n-type impurities implanted in the channel regions 17 and 18 for adjusting the threshold voltage. Further, between the p-type transistor 11 and the n-type transistor 12, a field shield region 3 is surrounded so as to surround the p-type transistor 11, a p-type conductive layer region 7 for applying a substrate bias, and an n-type transistor. Conductive layer region 8 is formed. Here, the field shield region 3 is formed by forming an insulator 3a, a conductive layer 3b of polysilicon or the like, and an insulator 3c on a p-type silicon substrate 1 or an n-type well 2 in this order. By applying a potential, leakage of current to adjacent elements due to the electrolytic effect is prevented. In addition, the p-type conductive layer region 7 is formed in the n-type well 2,
Of the p-type silicon substrate 1 outside the well 2
Is formed to be located. The gate electrode 5 of the p-type transistor 11 and the gate electrode 15 of the n-type transistor 12 are connected to each other by the wiring 13. The wiring 13 is formed simultaneously with the patterning of the gate electrode 5 of each of the transistors 11 and 12, and is formed in the same layer as the gate electrode 15.

Next, a manufacturing procedure of the semiconductor device configured as described above will be described with reference to FIGS. 4 (a) to 4 (d).

First, as shown in FIG. 4A, an n-type well 2 is formed at a predetermined position in a silicon substrate 1, and then a field shield region 3 having a predetermined pattern is formed on the silicon substrate by a well-known process. To form.

Subsequently, as shown in FIG. 4B, a gate oxide film 4 having a film thickness of 100 Å to 200 Å is formed by thermal oxidation in a region on the silicon substrate 1 where the field shield region 3 is not formed, Further, as shown by the arrow, the gate electrode 5 below the p-type transistor 11 and the n-type transistor 1
Region 1 to be a channel region under the second gate electrode 15
Impurities for adjusting the threshold voltage are injected into 7 and 18. Also,
At the same time, a p-type transistor 1 is applied to apply a substrate bias.
P-type and n-type impurities are introduced also into the portions which should become the conductive layer regions 7 and 8 surrounding 1 respectively. As this impurity,
About 10 ¹² atoms / cm ² of a p-type impurity such as boron (B) is implanted into the region 17 of the p-type transistor 11 and the conductive layer region 7 at a dose amount, and the region 18 of the n-type transistor 12 and the conductive layer are doped. In the region 8, for example, an n-type impurity such as arsenic (As) or phosphorus (P) in a dose amount of about 10 ^{12 is used.}
Implant atoms / cm ² .

Thereafter, as shown in FIG. 4C, a polysilicon layer 5'which will be the gate electrodes 5 and 15 of the transistors 11 and 12 is formed on the entire surface of the p-type silicon substrate 1. Subsequently, the polysilicon layer 5 ′ is doped with an impurity at a high concentration to increase the conductivity, and then patterned to be gate electrode 5 of the p-type transistor 11, gate electrode 15 of the n-type transistor 12 and both gate electrodes 5. , 15 are left by etching, and the remaining polysilicon layer 5'is removed by etching, leaving a portion of the wiring 13 for connection. This gives p
The gate electrode 5 of the type transistor 11, the gate electrode 15 of the n-type transistor 12, and the wiring 13 are simultaneously formed. As a result, the gate electrode 5 as shown in FIG.
An electrode pattern in which the wiring 13 and the gate electrode 15 are continuous is formed.

Then, as indicated by an arrow in FIG.
For example, a p-type impurity such as boron (B) is added to the source / drain region 6 of the p-type transistor 11 shown in FIG.
And an n-type impurity such as arsenic (As) or phosphorus (P), which is implanted into the exposed portion of the p-type conductive layer region 7 and the source / drain region 16 of the n-type transistor 12.
And to the exposed portion of the n-type conductive region 8. The implantation amount of these impurities is about 10 ¹⁵ to ¹⁶ atom at the dose amount.
It is about s / cm ² .

Thereafter, in a step not shown, an insulating layer is formed and a wiring layer for connecting to an external circuit is formed. At this time, the gate electrode 5 of the p-type transistor 11 and the n
Since the gate electrode 15 of the n-type transistor 12 is connected by the wiring 13, the gate electrode 5 of the p-type transistor 11, the gate electrode 15 of the n-type transistor 12 and the wiring 1
If a through hole (contact hole) is formed at any one of the positions 3), the connection with the wiring layer thereabove is secured.

[0018]

As is apparent from the above description, according to the present invention, for example, a CMOS which connects gate electrodes to each other is used.
At the same time as introducing the impurity for adjusting the threshold voltage below the region that should be the gate electrode of each transistor constituting the structure, the same conductive property as the impurity for adjusting the threshold voltage is also applied to the conductive layer region for applying the substrate bias. By introducing the impurities described above, before connecting the impurities to the source / drain regions of each transistor, it is possible to connect the gate electrodes of the transistors to each other on the conductive layer region for applying the substrate bias. Even if the wiring pattern is formed, the continuity of the entire conductive layer for applying the substrate bias can be secured,
The substrate bias can be surely applied. As a result, a wiring for connecting the gate electrodes of the transistors can be formed in the same layer as the gate electrode at the same time, and thus a contact hole for connecting the gate electrode and an upper wiring layer is formed. Therefore, it is not necessary to secure a large area.

[Brief description of drawings]

1A is a plan view of a main part of a semiconductor device having a pair of transistors having a conventional CMOS structure, and FIG. 1B is a cross-sectional view taken along line BB of FIG.

2A to 2D are sectional views similar to FIG. 1B for explaining a manufacturing procedure of the semiconductor device shown in FIGS. 1A and 1B.

3 (a) is a plan view of a main part of a semiconductor device having a pair of transistors having a CMOS structure to which the present invention is applied, and FIG. 3 (b) is taken along line AA of FIG. 3 (a). Sectional drawing, (c) is a sectional view taken along line C-C in FIG.

4A to 4D are cross-sectional views similar to FIG. 3A illustrating a manufacturing procedure of the semiconductor device shown in FIGS. 3A and 3B.

[Explanation of symbols]

 1 p-type silicon substrate 2 n-type well 3 field shield region 3a insulator 3b conductive layer 3c insulator 4 gate oxide film 5 gate electrode 5'polysilicon layer 6 source / drain region 7, 8 conductive layer region 11 p-type transistor 12 n-type transistor 15 gate electrode 17, 18 region to be a channel region 13 wiring 16 source / drain region 21 p-type silicon substrate 22 n-type well 23 field shield 24 gate oxide film 25 gate electrode 27, 28 conductive layer region 29 Insulation layer 30 Contact hole 31 Aluminum wiring layer 35, 36 Transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/43 H01L 29/46 A

Claims (5)

[Claims] 1. A plurality of Ms having gate electrodes connected to each other
A method of manufacturing a semiconductor device having an OS type transistor and a substrate bias applying conductive layer provided between the respective transistors, the process of forming a gate oxide film, and a region to be a channel region under a gate electrode. And a step of simultaneously introducing an impurity for adjusting a threshold voltage into a region to be a conductive layer for applying a substrate bias located between the transistors, a step of forming a polysilicon layer on the gate oxide film, Patterning the silicon layer to form a gate electrode of each transistor and a wiring for connecting the gate electrodes in the same layer; and a source / drain region, the gate electrode, the wiring, and the substrate bias applying conductivity. And a step of simultaneously introducing impurities into a portion to be a layer. 2. A first-conductivity-type MOS transistor and a second-conductivity-type MOS transistor, which are formed in a semiconductor substrate and whose gate electrodes are connected to each other, and a substrate bias application provided between the transistors. A method of manufacturing a semiconductor device having a conductive layer, the step of forming a gate oxide film on the semiconductor substrate, a region to be a channel region under the gate electrode of the semiconductor substrate, and the semiconductor substrate A process of simultaneously introducing an impurity for adjusting a threshold voltage into a region to be a conductive layer for applying a substrate bias, and forming a polysilicon layer on the semiconductor substrate on which the gate oxide film is formed, and then forming the polysilicon. Patterning a layer to form the gate electrodes of the two transistors,
Forming a wiring for connecting the gate electrodes of the two transistors to each other in the same layer; a source / drain region and a gate oxide film of each transistor; the wiring; and a conductive layer for applying a substrate bias. A method of manufacturing a semiconductor device, comprising: simultaneously introducing an impurity into a region to be formed. 3. One of the two transistors is formed in a well formed in the semiconductor substrate, and the substrate bias applying conductive layer is formed of the two transistors in the well. The method of manufacturing a semiconductor device according to claim 2, wherein the transistor is formed so as to surround one of the transistors. 4. The substrate bias applying conductive layer has a first conductive layer formed inside the well and a second conductive layer formed outside the well. A method of manufacturing a semiconductor device according to item 1. 5. A semiconductor device using a field shield method as an element isolation method, which has a second conductivity type well on a first conductivity type semiconductor substrate and is formed on the first conductivity type semiconductor substrate. A second conductive type transistor and a first conductive type transistor formed in the second conductive type well, and a gate electrode of the first conductive type transistor and the second conductive type transistor.
A semiconductor device characterized in that the gate electrode of a conductivity type transistor is formed in the same layer.