JPH0778783A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device to be possessed of a connection wiring contact lessened in electrical resistance by a method wherein the contact is so formed as to extend into the surface of a substrate. CONSTITUTION:Field effect transistors 1 and 1' are electrically isolated from each other by an element isolating film (field oxide film) 2 formed on the surface of a substrate 10. The FETs 1 and 1' formed on the substrate 10 are electrically connected to each other with an aluminum wiring through the intermediary of contacts 3, and as contact hole 4 is over etched as far as the inside of the surface of the substrate 10 in an etching process, an aluminum wiring can be so formed as to extend into the etched surface of the substrate 10. By this setup, the junction surface between the contact 4 and the substrate 10 is increased in effective area, so that the junction surface can be remarkably lessened in electrical resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having contacts for electrically connecting wirings formed between elements formed on the surface of a semiconductor substrate.

[0002]

2. Description of the Related Art Generally, a plurality of elements formed in a semiconductor integrated circuit are electrically connected to each other by wiring such as an aluminum thin film or a polycrystalline silicon layer. In particular, in recent years, the number of contacts formed in one chip has greatly increased with the high integration of integrated circuits. With this,
The opening area of each contact hole must be formed as small as possible by reducing the rule of circuit design. When forming such an increased number of minute contacts in an integrated circuit of one chip, the contact resistance of the entire one chip increases in accordance with the increase in the degree of integration.

Under such circumstances, conventionally, for example, according to Japanese Patent Application Laid-Open No. 4-154149, insulation between the diffusion layer formed in the silicon substrate and the upper aluminum wiring layer is electrically isolated. There is disclosed a contact structure in which a substrate diffusion layer and an aluminum wiring layer are electrically connected by burying polycrystalline silicon in which an impurity such as phosphorus is diffused in an opening formed in the film.
According to this known structure, by interposing a polycrystalline silicon layer in which a high concentration impurity such as phosphorus is diffused and a metal silicide layer between the embedded polycrystalline silicon and the aluminum wiring layer, the buried polycrystalline silicon is Even if some of the diffused impurities such as phosphorus are absorbed by the use between the high-concentration impurity-diffused polycrystalline silicon layer and the metal silicide layer, it is possible to prevent the impurity concentration of the embedded polycrystalline silicon from decreasing. The contact resistance between the substrate diffusion layer and the aluminum wiring layer is prevented from increasing.

On the other hand, in Japanese Patent Laid-Open No. 3-262118, a technique of connecting a diffusion layer formed in a semiconductor substrate and an upper aluminum wiring layer through a buried contact of tungsten formed in an insulating film between these layers is disclosed. Is disclosed. According to this technique, a contact hole is formed in a thick interlayer insulating film on a semiconductor substrate, a conductor plug made of tungsten is formed in the contact hole, and the interlayer insulating film is formed until the conductor plug appears on the surface of the interlayer insulating film. By flattening the surface of the interlayer insulating film by etching the insulating film, the adhesion of the aluminum wiring layer is improved and the contact resistance is improved.

[0005]

However, any of the above-mentioned conventional techniques provides a technique for improving the electrical characteristics between the conductor used for the contact and the wiring layer which is in close contact with the conductor. However, it is impossible to positively reduce the electric resistance between the contact material and the diffusion layer of the semiconductor substrate in which the current is most likely to be concentrated at the contact portion. That is, normally, the contact hole is formed in the oxide insulating film on the substrate by the wet etching method. However, when this wet etching is used, isotropic etching is performed. As it increases, the pore size becomes smaller. Therefore, current concentration occurs at the contact interface with the substrate after the electrical wiring is applied,
The electric resistance value here increases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device having a contact for connection wiring with a reduced electric resistance value.

[0007]

To achieve the above object, according to the present invention, a semiconductor substrate of a first conductivity type, a region of a second conductivity type formed in the semiconductor substrate, and a surface of the semiconductor substrate. A semiconductor device having an insulating film formed on the insulating film, and a contact formed to electrically connect the electric wiring layer formed on the insulating film to the surface of the semiconductor substrate, the contact being the surface of the substrate. There is provided a semiconductor device formed so as to extend to the inside of the. The contact can be formed of a material including at least one of aluminum, copper, silicon, palladium, titanium, tungsten, titanium nitride, and platinum.

[0008]

Since the contact for electric wiring extends to the inside of the surface of the semiconductor substrate, the effective area of the connection interface between the contact and the substrate increases, so that when a current flows through the contact, the contact interface The electric resistance value is greatly reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an MO to which the contact of the present invention is applied.
3 shows a cross section of an S semiconductor device. In the figure, 1 and 1 ′ are field effect transistors (FETs) formed on a semiconductor substrate 10 made of silicon. These FETs are electrically isolated from each other by an element isolation film (field oxide film) 2 formed on the surface of the substrate 10. The FETs formed on the substrate are electrically connected to each other through the contacts 3 by wirings made of aluminum, for example, but the contact holes 4 are over-etched to the inside of the substrate surface by an etching process described later. Therefore, aluminum as wiring can be formed so as to extend to the inside of the etched substrate surface.

2A and 2B show enlarged cross sections of the contacts. (A) shows a cross section of a conventional contact, where the radius and the cross-sectional area of the contact on the substrate surface are a and S, respectively, and the constant determined by the material of the semiconductor substrate and the electrical resistance is α, the contact material and the semiconductor substrate. The electric resistance value at the connection interface with and can be expressed by R1 = α / S.

In the case of the present invention shown in (b), assuming that the diameter of the contact hole is the same as the conventional one, for example, assuming that the diameter of the contact hole (2a) is deepened by 20% (0.4a), the contact The electric resistance value between the substrate and the substrate is R2 = α / (πa ² + 0.8a ² π) = α / 1.8πa ² = α / 1.8S = R1 / 1.8 = 0.55R1 It can be seen that in the case of the contact according to the invention, the resistance value is reduced by 45% as compared with the conventional resistance value R1. The contact hole can be formed by either wet etching or dry etching, but a more steep and steep contact hole can be formed by using dry etching.

Next, a method of forming a contact according to the present invention will be described. In FIG. 3, FETs 1 and 1 ′ separated by a device isolation film by a known method are formed on a silicon substrate. Each FET has a source region S, a drain region D, and a gate G insulated by the source and drain regions and the gate oxide film 5 (FIG. 3).
(A)). CV is formed on the entire surface of the substrate on which the element is formed in this way.
By the method D, SiO ₂ is deposited to a thickness of, for example, 6000 Å to form the interlayer insulating film 7 (FIG. 3B). Next, a photoresist mask 8 is formed on the interlayer insulating film 7 in a predetermined pattern, and after the substrate surface is exposed by penetrating the oxide film downward through the uncovered portion, etching is performed to a desired depth. By continuing, the contact hole 4 dug down to the inside of the substrate surface is formed (FIG. 3C). Then, the photoresist layer on the interlayer insulating film 7 is removed, and aluminum is deposited on the contact portion and the wiring portion to obtain the semiconductor device of the present invention (FIG. 3D).

Although aluminum is used as the wiring material in the above-mentioned embodiments, a material such as aluminum, copper, silicon, palladium, titanium, tungsten, titanium nitride or platinum can be used instead.

In the above embodiment, a silicon substrate was used as the substrate for forming the element, but instead of this, GaAs was used.
It can also be applied to a semiconductor device on a substrate.

[0016]

As described in detail above, the semiconductor device of the present invention has a semiconductor substrate of the first conductivity type, a second conductivity type region formed in the semiconductor substrate, and a surface of the semiconductor substrate. A contact formed so as to electrically connect the formed insulating film and the electric wiring layer formed on the insulating film to the surface of the semiconductor substrate, and the contact is inside the substrate surface. Since it is formed so as to extend up to, the effective area of the connection interface between the contact and the substrate increases, so that the electric resistance value at this connection interface can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device of the present invention.

FIG. 2 is an explanatory diagram showing a contact area between a contact material and a semiconductor substrate.

FIG. 3 is an explanatory view showing a method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 2 element isolation film 3 contact 4 contact hole 5 gate oxide film 7 interlayer insulating film 8 photoresist layer 9 aluminum wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display H01L 21/90 D

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type, a region of a second conductivity type formed in the semiconductor substrate, an insulating film formed on the surface of the semiconductor substrate, and an insulating film formed on the insulating film. A semiconductor device having a contact formed to electrically connect the electric wiring layer to the surface of the semiconductor substrate, wherein the contact is formed to extend to the inside of the substrate surface. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the contact is made of a material made of at least one of aluminum, copper, silicon, palladium, titanium, tungsten, titanium nitride and platinum.