GB2083698A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- GB2083698A GB2083698A GB8123805A GB8123805A GB2083698A GB 2083698 A GB2083698 A GB 2083698A GB 8123805 A GB8123805 A GB 8123805A GB 8123805 A GB8123805 A GB 8123805A GB 2083698 A GB2083698 A GB 2083698A
- Authority
- GB
- United Kingdom
- Prior art keywords
- polycrystalline silicon
- layer
- region
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011810 insulating material Substances 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
- H01L23/4855—Overhang structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A polycrystalline silicon region 8 is provided under an overhang at the edge of a layer 3. In a first embodiment layer 3 is a polycrystalline silicon gate and region 8 connects the gate to a diffused region 1. In a second embodiment (Figure 3) the overhanging layer is of insulating material and region 8 forms a conductive track or resistor completely surrounded by insulating material. Impurities may be diffused into the region 8 from gate layer 3 and substrate diffused layer 1, by a heat treatment step to produce an ohmic contact between gate layer 3 and substrate diffused layer 1. Other methods of forming the electrical connection are also described. <IMAGE>
Description
SPECIFICATION
Semiconductor device
This invention relates to semiconductor devices.
According to the present invention there is provided a semiconductor device having a semiconductor substrate, an insulating film formed thereon, and electrically conductive material or an insulating material on said insulating film, the area of said insulating film being smaller than that of said electrically conductive material or said insulating material, a region of polycrystalline silicon being provided in the space formed between said insulating film and said electrically conductive material or said insulating material.
In one embodiment a current path is formed between said semiconductor substrate and said electrically conductive material by said region of polycrystalline silicon.
In another embodiment said semiconductor device includes an insulating film between said region of polycrystalline silicon and the semiconductor substrate, said region of polycrystalline silicon acting as a resistor or a current path.
The invention is illustrated, merely by way of example, in the accompanying drawings, in which:
Figure 1 illustrates a conventional semiconductor deyice;
Figure 2, consisting of Figures 2(a) to 2(e) shows, by sectional views, the steps of making one embodiment of a semiconductor device according to the present invention; and
Figure 3 is a sectional view of part of another embodiment of a semiconductor device according to the present invention.
A conventional silicon gate MOSAIC semiconductor device using polycrystalline silicon as gate material as shown in Figure 1. In Figure 1 reference numeral 1 indicates a substrate diffused layer, reference numeral 2 indicates a gate insulating film, reference numeral 3 indicates a polycrystalline silicone gate layer, reference numeral 4 indicates a field insulating film, reference numeral 5 indicates an aluminium film and reference numeral 11 indicates a substrate of silicon.
In this conventional semiconductor device, electrical contact between the polycrystalline silicon gate layer 3 and the substrate diffused layer 1 is obtained by growing the field insulating film thereon and forming a contact hole in the field insulating film 4 and then electrically connecting the polycrystalline silicon gate layer 3 and the substrate diffused layer 1 by the aluminium film 5 through the contact hole. To take account of the fact that the polycrystalline silicon gate layer, the contact hole and the aluminium film etc. are not always in alignment with one another, even without any aberration in photoetching techniques used, the semiconductor device needs a relatively large area for its construction and thus integration cannot be substantially improved.
Figure 2 illustrates the steps of a method of making one embodiment of a semiconductor device according to the present invention to overcome the disadvantages of the conventional semiconductor device shown in Figure 1. Referring first to Figure 2(a), the steps of-patterning of the polycrystalline silicon gate layer 3, etching of the gate insulating film 2 and impurity diffusion have been effected by conventional techniques. The etching causes the gate insulating film 2 beneath the polycrystalline silicon gate layer 3 to be undercut. In other words, the area of the gate insulating film 2 is less than the area of the polycrystalline silicon gate layer 3.Next, a gate silicon oxide (SiO2) film is grown by a chemical vapour deposition (CVD) technique and part of the film 6 where an electrical connection between the polycrystalline silicon gate layer 3 and the substrate diffused layer 1 is to be made, is removed by a photo-etching technique (Figure 2(b)).
Athin polycrystalline silicon film 7 is then grown over the whole surface as shown in Figure 2(c). The thickness of the polycrystalline silicon film 7 may be between 500 A and 1500A. Next, the polycrystalline silicon film 7 is etched using a CF4 plasma technique or converted into a silicon oxide film by a thermal oxidation technique or an an anodizing technique (Figure 2(d)). As shown in Figure 2(d), only a region 8 of the polycrystalline silicon film 7 remains adjacent the undercut portion of the gate insulating film 2 beneath the polycrystalline gate layer 3. The region 8 of the polycrystalline silicon film 7 electrically connects the polycrystalline silicon gate layer 3 and the substrate diffused layer 1.Next, a heat-treatment step is carried out at an appropriate temperature between 9000C and 1000'Cto cause impurities to be diffused into the region 8 of the polycrystalline silicon film 7 from the polycrystalline silicon gate layer 3 and the substrate diffused layer 1, and a complete ohmic contact can be expected between the polycrystalline silicon gate layer 3 and the substrate diffused layer 1.
Then a second field insulating film 12 is grown over the whole surface by a CVD technique (Figure 2(e)). Subsequent processes such as photo-etching to form a contact hole, deposition of an aluminium film, and photo-etching of the aluminium film are effected in the conventional manner.
Other methods to electrically connect the polycrystalline silicone gate layer 3 and the substrate diffused layer 1 by way of the region 8 of the polycrystalline silicon film 7 are possible. For example, after the gate oxide film 6 is etched, the polycrystalline silicon film 7 is grown and impurities are diffused therein. The impurities diffisued in the polycrystalline silicon film 7 will also be diffused into the substrate diffused layer 1 through the polycrystalline silicon film 7. After that, all the polycrystalline silicon film 7 except for the region 8 for connecting the polycrystalline silicon gate layer 3 and the substrate diffused layer 1, is removed by a photoetching technique.
Another possibility is that, after forming the polycrystalline silicon gate layer 3, the part of the gate oxide film 6 where an electrical connection between the polycrystalline silicon gate layer 3 and the substrate diffused layer 1 is to be formed, is removed by photo-etching. Then the polycrystalline silicon film 7 is grown and etched to leave the region 8 under the polycrystalline silicon gate layer 3.
From the above it will be appreciated that it is now possible to make an electrical connection between the polycrystalline silicon gate layer 3 and the substrate diffused layer 1 with a small area thereby to improve greatly the integration of an IC.
Figure 3 shows another embodiment of a semiconductor device according to the present invention wherein a silicon oxide insulating film 9, such as silicon nitride, which is not easily etched, is used in place of the polycrystalline silicon gate layer 3 of
Figure 2. Thus a remarkably fine current path on a field insulating film 10 is formed. This current path can be used as an ordinary electrical lead or as a resistor. By applying this construction to an IC, a minute interconnection can be achieved.
Claims (5)
1. A semiconductor device having a semiconductor substrate, an insulating film formed thereon, and electrically conductive material or an insulating material on said insulating film, the area of said insulating film being smaller than that of said electrically conductive material or said insulating material, a region of polycrystalline silicon being provided in the space formed between said insulating film and said electrically conductive material or said insulating material.
2. A semiconductor device as claimed in claim 1 in which a current path is formed between said semiconductor substrate and said electrically conductive material by said region of polycrystalline silicon.
3. A semiconductor device as claimed in claim 1 including an insulating film between said region of polycrystalline silicon and the semiconductor substrate, said region of polycrystalline silicon acting as a resistor or a current path.
4. A semiconductor device substantially as herein described with reference to and as shown in
Figures 2 and 3 of the accompanying drawings.
5. A semiconductor device having a semiconductor substrate, an insulating film formed thereon, an electrical conductive material or an insulating material formed on said insulating film being characterised in that plane area of said insulating film is smaller than that of said electrical conductive material or said insulating material and thereby polycrystalline silicon is filled up in the space formed by said insulating film and said electrical conductive material or said insulating material.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12426480A JPS5748270A (en) | 1980-09-08 | 1980-09-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2083698A true GB2083698A (en) | 1982-03-24 |
| GB2083698B GB2083698B (en) | 1984-10-31 |
Family
ID=14881022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8123805A Expired GB2083698B (en) | 1980-09-08 | 1981-08-04 | Semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5748270A (en) |
| DE (1) | DE3135103A1 (en) |
| FR (1) | FR2490011B1 (en) |
| GB (1) | GB2083698B (en) |
| NL (1) | NL188606C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04194693A (en) * | 1990-11-28 | 1992-07-14 | Mitsui Eng & Shipbuild Co Ltd | Radar system for detecting cavity under road |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583380B2 (en) * | 1977-03-04 | 1983-01-21 | 株式会社日立製作所 | Semiconductor device and its manufacturing method |
-
1980
- 1980-09-08 JP JP12426480A patent/JPS5748270A/en active Granted
-
1981
- 1981-07-28 NL NL8103565A patent/NL188606C/en not_active IP Right Cessation
- 1981-08-04 GB GB8123805A patent/GB2083698B/en not_active Expired
- 1981-09-04 DE DE19813135103 patent/DE3135103A1/en active Granted
- 1981-09-04 FR FR8116853A patent/FR2490011B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2490011B1 (en) | 1985-09-27 |
| DE3135103C2 (en) | 1988-07-14 |
| NL8103565A (en) | 1982-04-01 |
| FR2490011A1 (en) | 1982-03-12 |
| NL188606C (en) | 1992-08-03 |
| DE3135103A1 (en) | 1982-05-06 |
| NL188606B (en) | 1992-03-02 |
| JPS5748270A (en) | 1982-03-19 |
| JPH0216019B2 (en) | 1990-04-13 |
| GB2083698B (en) | 1984-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920804 |