NL8103565A - SEMICONDUCTOR DEVICE. - Google Patents
SEMICONDUCTOR DEVICE. Download PDFInfo
- Publication number
- NL8103565A NL8103565A NL8103565A NL8103565A NL8103565A NL 8103565 A NL8103565 A NL 8103565A NL 8103565 A NL8103565 A NL 8103565A NL 8103565 A NL8103565 A NL 8103565A NL 8103565 A NL8103565 A NL 8103565A
- Authority
- NL
- Netherlands
- Prior art keywords
- poly
- gate
- semiconductor device
- diffused
- layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims 3
- 238000010276 construction Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
- H01L23/4855—Overhang structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
-1--1-
vo 2Ï6Uvo 2Ï6U
HalfgeleiderinrichtingSemiconductor device
De uitvinding heeft betrekking op een halfgeleiderinrichting en in het bijzonder op de opbouw van een MOS-IC en een werkwijze voor het fabriceren daarvan. Conventionele MOS-IC's met een sliciumpoort, waarbij gebruik wordt gemaakt van polykristallijn silicium (dat in het 5 hierna volgende poly-Si genoemd zal worden) als poortmateriaal, bezitten een opbouw, zoals die in fig. 1 getoond is. In deze figuur is met 1 een gediffundeerde substraatlaag aangegeven, 2 is een de poort isolerende dunne laag, 3 is een poly-Si poort, U is een tweede veldisolerende dunne laag, 5 is een dunne Al-laag en 11 is een substraat 10 (silicium). Bij de conventionele in fig. 1 getoonde opbouw wordt een elektrisch contact tussen de poly-Si-poort 3 en de gediffundeerde substraatlaag 1 verkregen door daarop de tweede veldisolerende dunne laag h te laten groeien en door een contactgat te vormen in de tweede dunne veldlaag U en vervolgens de poly-Si-poort 3 en de gediffundeerde 15 substraatlaag 1 via de dunne aluminiumlaag -5 te verbinden. Aangezien echter het poly-Si de contactgaten, de dunne aluminiumlaag en dergelijke bij het foto-etsen niet nauwkeurig met elkaar in lijn liggen, is er een relatief groot oppervlak nodig -voor de constructie volgens de conventionele werkwijze en dat is een belangrijk punt voor de 20 verbetering van de integratie van MOS-IC's.The invention relates to a semiconductor device and in particular to the construction of a MOS-IC and a method for manufacturing it. Conventional MOS-ICs with a silicon gate using polycrystalline silicon (which will be referred to hereinafter as poly-Si) as gate material have a structure such as that shown in Figure 1. In this figure, 1 denotes a diffused substrate layer, 2 is a gate insulating thin layer, 3 is a poly-Si gate, U is a second field insulating thin layer, 5 is a thin Al layer, and 11 is a substrate 10 ( silicon). In the conventional construction shown in Fig. 1, an electrical contact between the poly-Si gate 3 and the diffused substrate layer 1 is obtained by growing the second field insulating thin layer h thereon and by forming a contact hole in the second thin field layer U and then connecting the poly-Si gate 3 and the diffused substrate layer 1 via the thin aluminum layer -5. However, since the poly-Si do not accurately align the contact holes, the thin aluminum layer and the like during photo-etching, a relatively large surface area is required - for the construction according to the conventional method and this is an important point for the 20 improving the integration of MOS ICs.
Om het genoemde nadeel te vermijden en de integratie van MOS-IC's te verbeteren, voorziet de uitvinding in een nieuwe opbouw en een nieuw fabricageproces voor een IC.In order to avoid the said drawback and to improve the integration of MOS ICs, the invention provides a new construction and a new manufacturing process for an IC.
Fig. 2 toont een aantal dwarsdoorsneden van een deel van een 25 halfgeleiderinrichting welke de opbouw en de fabricage volgens de uitvinding tonen.Fig. 2 shows a number of cross-sections of a part of a semiconductor device, showing the construction and manufacture according to the invention.
Fig. 2a is een dwarsdoorsnede van de halfgeleiderinrichting in een fase, waarbij de patroonvoiming van poly-Si, het etsen van de poortoxydefilm en de diffusie van verontreinigingen voltooid is.Fig. 2a is a cross-sectional view of the semiconductor device in one phase, with the pattern voiding of poly-Si, the etching of the gate oxide film and the diffusion of impurities.
30 De fabricage tot op dit punt is dezelfde als die bij een conventionele inrichting. In dit stadium wordt de de poort 'isolerende dunne laag 2 onder het poortpoly-Si 3 ondersneden. Vervolgens laat men een CVD SiO^-film 6 aangroeien en daarna wordt een deel van de CVD-film, daar waar een elektrisch contact tussen het poortpoly-Si 3 en een gediffundeerde 8103565 ' ~~............ .........*........................... ..................-2-.........................Manufacturing to this point is the same as that of a conventional device. At this stage, the gate insulating thin layer 2 under the gate poly-Si 3 is undercut. Then, a CVD SiO 2 film 6 is allowed to grow and then part of the CVD film becomes where there is an electrical contact between the gate poly-Si 3 and a diffused 8103565 ~~ .......... .. ......... * ........................... ........... .......- 2 -.........................
substraatlaag 1 gemaakt moet worden, door foto-etsen verwijderd (fig. 2b).substrate layer 1 must be made, removed by photo-etching (fig. 2b).
Vervolgens laat men poly-Si aangroeien over het gehele oppervlak. Dit is het aangroeien van het tweede poly-Si 7 (fig. 2c). De dikte 5 van deze tweede poly-Si-film 7 kan 50-150 nanometer bedragen. Hierin wordt de tweede poly-Si-film 7 verwijderd met behulp van CF^-plasma of iets dergelijks of veranderd door middel van thermische oxydatie of anodi-seren in een silicium (fig. 2d). Bij deze werkwijze is, zoals getoond in fig. 2d, nog slechts een deel van de tweede poly-Si-laag 7 aanwezig 10 aan de onderzijde van het poort-poly-Si, daar waar de poort-isolerende film ondersneden is. Dit resterende poly-Si 8 verbindt het. poortpoly-Si met de gediffundeerde substraatlaat 1. Vervolgens worden door een warmtebehandeling bij een geschikte temperatuur (900-1000°C) verontreinigingen in het poly-Si 8 gediffundeerd vanuit het poortpoly-Si 3 15 en vanuit de gediffundeerde substraatlaag 1 en er is dan een volledig ohmscontact, tussen het poortpoly-Si 3 en de gediffundeerde substraatlaag 1.Poly-Si is then allowed to grow over the entire surface. This is the growth of the second poly-Si 7 (fig. 2c). The thickness 5 of this second poly-Si film 7 can be 50-150 nanometers. Herein, the second poly-Si film 7 is removed using CF 4 plasma or the like or changed by thermal oxidation or anodizing in a silicon (Fig. 2d). In this method, as shown in Fig. 2d, only part of the second poly-Si layer 7 is still present at the bottom of the gate poly-Si, where the gate insulating film is undercut. This remaining poly-Si 8 connects it. gate poly-Si with the diffused substrate plate 1. Subsequently, by a heat treatment at a suitable temperature (900-1000 ° C), impurities in the poly-Si 8 are diffused from the gate poly-Si 3 and from the diffused substrate layer 1 and there is then a full ohmic contact, between the gate poly-Si 3 and the diffused substrate layer 1.
Vervolgens laat men de tweede veldisolerende film 12 aangroeien met behulp van CVD (fig. 2e). De daarop volgende stappen, zoals 20 het foto-etsen voor het vormen van een contactgat, het neerslaan van aluminium en het foto-etsen van de aluminiumfilm, zijn dezelfde als bij de conventionele werkwijze.Then, the second field insulating film 12 is allowed to grow using CVD (Fig. 2e). The subsequent steps, such as photo-etching to form a contact hole, depositing aluminum and photo-etching the aluminum film, are the same as in the conventional method.
Naast de boven beschreven werkwijze zijn er ook andere werkwijzen mogelijk om het poortpoly-Si 3 en de gediffundeerde substraat-25 laag 1 via het tweede poly-Si 8 te verbinden.. In het hierna volgende zullen twee van deze werkwijzen besproken worden.In addition to the method described above, other methods are also possible to connect the gate poly-Si 3 and the diffused substrate-25 layer 1 via the second poly-Si 8. Two of these methods will be discussed below.
Nadat de poortoxydefilm geëtst is, laat men de tweede poly-Si-laag 7 aangroeien en worden verontreinigingen gediffundeerd, (in het geval dat verontreinigingen gediffundeerd worden op het tweede poly-30 Si 7j worden zij ook gediffundeerd in de gediffundeerde substraatlaag via het tweede poly-Si 7). Vervolgens wordt het tweede poly-Si, met uitzondering van het gedeelte voor het verbinden van het poortpoly-Si en de gediffundeerde substraatlaag, verwijderd door foto-etsen.After the gate oxide film is etched, the second poly-Si layer 7 is allowed to grow and impurities are diffused, (in the case where impurities are diffused on the second poly-Si Si 7j, they are also diffused into the diffused substrate layer via the second poly -Si 7). Then, the second poly-Si, except for the portion for joining the gate poly-Si and the diffused substrate layer, is removed by photo-etching.
Vervolgens blijft slechts poly-Si 8 aanwezig om het poortpoly-Si 35 en de gediffundeerde substraatlaag te verbind'en. Volgens een andere werkwijze kan na het vormen van het patroon van poly-Si het gedeelte van een poortoxydefilm, daar waar een contact tussen het poortpoly-Si 3 8103565 » ' ~T"......................................................................"....... -3-........Then only poly-Si 8 remains to connect the gate poly-Si 35 and the diffused substrate layer. According to another method, after forming the pattern of poly-Si, the portion of a gate oxide film where there is a contact between the gate poly-Si 3 8103565 "~ T" ............. .................................................. ....... "....... -3 -........
en de gediffundeerde substraatlaag 1 gemaakt moet worden, verwijderd worden door foto-etsen. Vervolgens laat men het tweede poly-Si 7 aangroeien. Dit tweede poly-Si 7 wordt op zodanige wijze geëtst, dat alleen het tweede poly-Si 8 dat onder het poortpoly-Si 3 geplaatst 5 is, d.w.z. in het gedeelte dat ondersneden is nabij het uiteinde van het poortpoly-Si 3, aanwezig blijft.and the diffused substrate layer 1 is to be made, removed by photo-etching. The second poly-Si 7 is then allowed to grow. This second poly-Si 7 is etched in such a way that only the second poly-Si 8 placed under the gate poly-Si 3 remains, ie in the portion undercut near the end of the gate poly-Si 3, remains .
Zoals bovenstaand beschreven is, is het door het toepassen van de uitvinding mogelijk cm elektrisch contact te maken tussen poortpoly-Si en een gediffundeerde substraatlaag, waarbij slechts 10 een klein oppervlak voor het elektrische contact nodig is, waardoor dus de mate van integratie van een IC aanzienlijk verbeterd kan worden.As described above, by applying the invention it is possible to make electrical contact between gate poly-Si and a diffused substrate layer, requiring only a small area for the electrical contact, thus increasing the degree of integration of an IC can be significantly improved.
De uitvinding kan ook toegepast worden bij een opbouw, zoals getoond in fig. 3, door in plaats van poortpoly-Si gebruik te maken ;15 van een isolerende siliciumoxydefilm, zoals siliciumnitride, dat niet gemakkelijk geëtst kan worden door een etsmiddel en door op die wijze te voorzien in een bijzonder dunne stroombaan op een eerste veldisolerende film 10. Deze stroombaan kan gebruikt worden als een gewone geleider of als weerstand. Door deze constructie toe te 20 passen bij IC*s kan men de onderlinge verbindingen in 'een IC bijzonder klein maken.The invention can also be applied to a structure, as shown in Fig. 3, by using instead of gate poly-Si, an insulating silicon oxide film, such as silicon nitride, which cannot be easily etched by an etchant and by providing a particularly thin current path on a first field insulating film 10. This current path can be used as a regular conductor or as a resistor. By applying this construction to ICs, the interconnections in an IC can be made particularly small.
81035658103565
Claims (3)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12426480 | 1980-09-08 | ||
| JP12426480A JPS5748270A (en) | 1980-09-08 | 1980-09-08 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| NL8103565A true NL8103565A (en) | 1982-04-01 |
| NL188606B NL188606B (en) | 1992-03-02 |
| NL188606C NL188606C (en) | 1992-08-03 |
Family
ID=14881022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL8103565A NL188606C (en) | 1980-09-08 | 1981-07-28 | METHOD FOR MANUFACTURING A FIELD EFFECT TRANSISTOR WITH INSULATED GATE |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5748270A (en) |
| DE (1) | DE3135103A1 (en) |
| FR (1) | FR2490011B1 (en) |
| GB (1) | GB2083698B (en) |
| NL (1) | NL188606C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04194693A (en) * | 1990-11-28 | 1992-07-14 | Mitsui Eng & Shipbuild Co Ltd | Radar system for detecting cavity under road |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583380B2 (en) * | 1977-03-04 | 1983-01-21 | 株式会社日立製作所 | Semiconductor device and its manufacturing method |
-
1980
- 1980-09-08 JP JP12426480A patent/JPS5748270A/en active Granted
-
1981
- 1981-07-28 NL NL8103565A patent/NL188606C/en not_active IP Right Cessation
- 1981-08-04 GB GB8123805A patent/GB2083698B/en not_active Expired
- 1981-09-04 FR FR8116853A patent/FR2490011B1/en not_active Expired
- 1981-09-04 DE DE19813135103 patent/DE3135103A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2490011A1 (en) | 1982-03-12 |
| GB2083698A (en) | 1982-03-24 |
| JPH0216019B2 (en) | 1990-04-13 |
| DE3135103A1 (en) | 1982-05-06 |
| DE3135103C2 (en) | 1988-07-14 |
| GB2083698B (en) | 1984-10-31 |
| FR2490011B1 (en) | 1985-09-27 |
| NL188606B (en) | 1992-03-02 |
| JPS5748270A (en) | 1982-03-19 |
| NL188606C (en) | 1992-08-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A85 | Still pending on 85-01-01 | ||
| BA | A request for search or an international-type search has been filed | ||
| BB | A search report has been drawn up | ||
| BC | A request for examination has been filed | ||
| V1 | Lapsed because of non-payment of the annual fee |