CA1251285A - Semiconductor device having electrode and first level inteconnection embedded in two-layer insulating film - Google Patents

Abstract

Abstract:
A semiconductor device includes a semiconductor substrate and a two-layer insulating film formed on the substrate and constituted by upper and lower insulating layers made of insu-lating materials different in chemical properties from each other. An electrode and a first level interconnection are em-bedded in an opening formed in the two-layer insulating film.
The invention also relates to a method of forming this device.
The distribution of threshold voltage among field effect tran-sistors made in accordance with the present invention is more uniform than among those made by prior art methods.

Description

~25~1~Si Semiconductor device and method of manufacturing the same The present invention relates generally to a semiconductor device, and to a method of manufacturing a semiconductor device, and, more particularly, to a semiconductor device of flat con~
figuration suitable for multilayer interconnection, and a method of manufacturing such a device, in which, by employing a lift-off method in an integrated circuit, an electrode and a first level interconnection can be formed with a high yield.
When a field effect transistor (FET) or an integrated cir-cuit is produced on a substrate made of a compound semiconduc-tor, the lift-off method is generally employed for forming var-ious electrodes or a first level interconnection on the surface of the substrate. This is because, if the wet etching method that is used generally in the manufacture of a large scale in-tegrated circuit (LSI) made of Si, i.e., a method in which themetal of the electrodes or the metal of the first level inter-connection is etched by an acid or a basic agent is applied to the manufacture of a substrate of a compound semiconductor, the problem arises that a chemical reaction takes place between the agent and the substrate. Furthermore, in view of the fact that micro processing with an accuracy similar to that needed for the manufacture of a very large scale integrated circuit (VLSI) of Si is required for the manufacture of the substrate *

~25~ 5 of a compound semiconductor, the wet etching method is inap-propriate for this latter manufacture. In order to micromini-aturize the substrate of a compound semiconductor, there has been proposed either a so-called plasma etching method using, in place of the agent, ions generated in a gas plasma, or a reactive ion etching method. However, these two known methods present the same problem as the wet etching method, because the substrate of a compound semiconductor has a low selec-tivity for the materials to be etched. Furthermore, these two known methods are disadvantageous in that the substrate may be damaged by plasmatic irradiation or ion bombardment.
To enable the prior art to be described with the aid of diagrams, the figures of the drawings will first be listed.
Figs. l(A) and l(B~ are views explanatory of the for-mation of an electrode using the prior art lift-off method;
Figs. 2(A) to 2(D) are views explanatory of a prior art multilayer resist method;
Figs. 3(A) to 3(D) are views explanatory of a prior art insulating film (spacer) lift-off method;
Fig. 4 is a sectional view indicative of the configur-ation of a semiconductor device according to an embodiment of the present invention;
Figs. 5(A) to 5(G) are views indicative of a method of manufacturing a semiconductor device, according to one pre-ferred embodiment of the present invention;
Fig. 6 is a graph indicative of distribution of a thresh-old voltage of a field effect transistor (FET) produced by a method of the present invention on a wafer having a two-layer insulating film; and Fig. 7 is a graph similar to Fig. 6, particularly show-ing the distribution of threshold voltage of a field effect transistor (FET) produced by the prior art insulating film (spacer) lift-off method of Fig. 3.
In order to reduce the electrical resistances of elec-trodes and wires in microminiaturization of an integrated circuit, the e]ectrodes and the wires are required to be ~25~Z~

increased in thickness. If the lift-off method is employed for forming the electrodes and the wires, burrs 30, for ex-ample, are produced on a gate electrode 2 as shown in Figs.
l(Aj and l(B). If the gate electrode 2 is used for multi-layer interconnection without removing the burrs 30, suchinconveniences are caused that, since a layer of insulation film is damaged where it confronts the burrs 30 or a con-centration of electric field occurs between the upper and lower wires, a shortcircuiting phenomenon can take place, resulting in a drop in the yield of the integrated circuits.
In Fig. l(A), reference numeral 21 represents a photoresist~
In order to remove the burrs 30 from the gate electrode

2, the multilayer resist method shown in Figs. 2~AJ to 2(D) has been tried. This method aims to prevent the production of the burrs 30 by increasing the thickness of the resist for use in the lift-off and, at the same time, forming a cross section of the resist into a trapezoidal shape. However, in the multilayer resist method, since the lowermost resist is generally subjected to reactive ion etching from a micromini-ature standpoint, damage to the surface of the semiconductorcan take place. In addition, the multilayer resist method has the disadvantage that its steps are numerous and compli-cated, thus resulting not only in poor controllability and reproducibility but also in a low yield and productivity.
In Fig. 2, reference numerals 21 and 23 represent photo-resists and reference numeral 22 represents an intermediate layer.
To solve these problems, there is, for example, the in-sulating film (spacer) lift-off method shown in Figs. 3(A) to 3(D~. In this method, the lower resist layer of the multilayer resist method is replaced by an insulating film 11, thus gaining the advantage that the integrated circuit is formed, after the lift-off, into a flat configuration.
However, in the insulating film lift-off method, since re-active ion etching is performed for processing the insulatingfilm, there is still a problem of damage to the surface of the semiconductor substrate. For example, when a field effect 5~ 5 transistor (FET) was produced on a GaAs substrate in the spacer lift-off method using a silicon nitride film as the insulating film, it was found by the p~esent inventor that the threshold voltage (Vth) of the FET was widely scattered.
Accordingly, an essential object of the present invention is to provide a semiconductor device and a method of manufac-turing the same that eliminate the above-described disadvantages of the various conventional semiconductor devices and methods.
To this end, the invention consists of a semiconductor device comprising: a semiconductor substrate; a two-layer in-sulating film formed on a surface of said semiconductor sub-strate and constituted by a first insulating layer disposed on said surface and a second insulating layer disposed on said first insulating layer; said first and second insulating layers being respectively made of first and second insulating materials that are different in chemical properties from each other; an electrode; and a first level interconnection; said two-layer insulating film having a thickness equal to or larger than the thicknesses of said electrode and said first level intercon-nection; said two-layer insulating film being formed with an opening in which said electrode and said first level intercon-nection are embedded.
The invention also consists of a method of manufacturing a semiconductor device comprising the steps of: forming a two-layer insulating film on a surface of a substrate made of acompound semiconductor; said two-layer insulating film being constituted by a first insulating layer and a second insulat-ing layer so that said first and second insulating layers are respectively disposed on said surface and on said first insul-ating layer; said first and second insulating layers being res-pectively made of first and second insulating materials; form-ing a predetermined photoresist pattern on said second insula-ting layer; performing reactive ion etching, of said second insulating layer using said photoresist pattern as a mask for the etching and subsequently performing wet etching, of said first insulating layer using said photoresist pattern and said ~25~285 second insulating layer as a mask for the wet etshing so as to form or. said two-layer insulating film an opening identical in contour to said photoresist pattern; depositing in said open-ing metal for forming both an electrode and a first level inter-connection; and performing a lift-off operation.
Referring now to the drawings, there is shown in Fig. 4 a configuration of a semiconductor device K embodying the present invention. The device K characteristically includes a semicon-ductor substrate 1, a two-layer insulating film 10 on the sur-face of the substrate 1, a gate electrode 2, an ohmic electrode

3 and a first level interconnection 4. The film lO is consti-tuted by a lower insulating layer 12 disposed on the surface of the substrate 1 and an upper insulating layer 11 disposed on the lower layer 12. The layers 11 and 12 are respectively made of insulating materials different in chemical properties from each other. The gate electrode 2, the ohmic electrode 3 and the interconnection 4 are embedded in an opening formed on the two-layer insulating film 10.
A method of manufacturing a semiconductor device according to one preferred embodiment of the present invention will now be described with reference to Figs. 5(A) to 5(G). In this em-bodiment, a field effect transistor (FET) is produced on a semi-conductor substrate 1, e.g., a GaAs substrate. Initially, the lower or first insulating layer 12, e.g., a silicon dioxide (SiO2) layer having a thickness of 1000 A, is formed using an ordinary chemical vapor deposition (CVD) method on a surface of the sub-strate 1 provided with an electrically conductive layer 5. Then, the upper or second insulating layer 11 made of an insulating material different from that of the SiO2 layer 12, e.g., a sil-icon nitride (Si-N) layer having a thickness of 3500 A, is formed on the SiO2 layer 12 using a plasma CVD method, so that the two-layer insulating film 10 is constituted by the SiO2 layer 12 and the Si-N layer 11 (Fig. 5(A)).
Subsequently, as shown in Fig. 5(B), a predetermined photo-resist pattern 21 is formed on the insulating film 10.

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Then, as shown in Fig. 5(C), the upper Si-N layer 11 is sub~ected to reactive ion etching, using, for example, a plasma of carbon tetrafluoride (CF4) gas at a pressure of 5xlO Torr and at an electric power of 100 W for 2 min., using the photoresist pattern 21 as a mask for the etching so that an opening 31 identical in contour to the photoresist pattern 21 is formed on the Si-N layer 11. At this time, since the etching speed of the lower SiO2 layer 12 is one-fifth of that of the upper Si-N layer 11, the reactive ion etching is substantially blocked by the lower SiO2 layer 12.
Thereafter, as shown in Fig. 5(D), the lower SiO2 layer 12 is subjected, for example, to wet etching, e.g., etching for 30 sec. by using a buffer solution of hydrofluoric acid using photoresist pattern 21 and the upper Si-N layer 11 as a mask for the wet etching so that an opening 32 identical in contour to the photoresist pattern 21 is formed on the SiO2 layer 12.
Immediately after the step of Fig. 5(D), a three-layer metal film having a lower layer made of a Au-Ge alloy, an intermediate layer made of Ni and an upper layer made of Au is deposited in the opening 32 to a film thickness of 4000 A
and then a lift-off operation is performed so that an ohmic electrode 3 is formed in the opening 32 as shown in Fig. 5(E).
Subsequently, after the unfinished semiconductor device has been heat treated at 450C, an insulating layer made of an insulating material identical to that of the Si-N layer 11, i.e., a Si-N layer 13 3000 A thickness, is formed on the Si-N
layer 11 using the plasma CVD method so that the Si-N layers 11 and 13 constitute a unitary upper Si-N layer 15 as shown in Fig. 5(F).
Finally, openings are formed on the lower SiO2 layer 12 and the upper Si-N layer 15 employing the steps shown in Figs.
5(A) to 5(D) and then a two-layer metal film having a lower layer made of Ti and an upper layer made of Au is deposited in the openings to a film thickness of 7000 A. Subsequently, a lift-off operation is performed so that a gate electrode 2 ~.Z5~285 and a first level interconnection 4 are formed in the openings as shown in Fig. 5(G).
Fig. 6 shows the distribution of threshold voltage of field effect transistors produced by a method according to the present invention on a wafer having a two-layer insula-ting film. For comparison, Fig. 7 shows a typical example of the distribution of threshold voltage of the FETs produced by the conventional insulating film (spacer) lift-off method (Fig. 3) in which the lower insulating layer 12 is not pro-vided. In Figs. 6 and 7, the abscissa represents the thresh-old voltage Vth of the FET, while the ordinate represents a performance index K factor (mA/V2), indicating the current driving capability of the FET. It will be seen from Fig. 7 that the surface of the semiconductor substrate is damaged by reactive ion etching, thereby resulting in an aggravation of the characteristics of the FET. The effectiveness of the present invention will be understood from a comparison be-tween Figs. 6 and 7.
The present invention has the feature that when the upper and lower insulating layers of the two-layer insulating film are sequentially subjected to reactive ion etching and wet etching respectively, the upper and lower insulating layers respectively have selectivity for reactive ion etching and wet etching. Since the object of the present invention can be accomplished if the semiconductor substrate is not damaged by etching of the lower insulating layer, etching of the lower insulating layer is not limited to the wet etching of the above described embodiment. Thus, plasma etching, etc. can also be employed for etching the lower insulating layer. In this con-nection, the combination of materials of the upper and lowerinsulating layers of the two-layer insulating film is not re-stricted to that of the above described embodiment, i.e., a combination of an upper insulating layer made of Si-N and a lower insulating layer made of SiO2. The two-layer insulating film can be formed by upper and lower insulating layers made of arbitrary materials, for example, the upper insulating ~L25~L~85 layer can be made of polyimide resin, e.g., "PIQ" ~name used in trade and manufactured by Hitachi Chemical Co., Ltd. of Japan3 and the lower insulating layer can be made of Si-N, or the upper layer made of SiO2 and the lower layer made of "PIQ", or the upper layer made of "PIQ" and the lower layer made of SiO2.
Furthermore, in the above described embodiment, when the lower insulating layer, i.e., the SiO2 layer, is subjected to wet etching, side etching is minimized by forming the SiO2 layer with a small thickness of 1000 A so that the accuracy of micro processing is improved. However, the lower insu-lating layer can be set at an arbitrary thickness in accord-ance with the accuracy required for micro processing.
As is clear from the foregoing description, the electrodes and the first level interconnection are so formed as to be em-bedded in the two-layer insulating film so that the semicon-ductor device is formed in a flat configura~ion.
Furthermore, since the upper insulating layer have a large thickness is processed by reactive ion etching having a high anisotropy, it becomes possible to perform high precision micro processing of the upper insulating layer. In addition, since the reactive ion etching is blocked by the lower insu-lating layer, the surface of the semiconductor substrate is protected from damage from ion bombardment.
Moreover, since the lower insulating layer is subjected to wet etching so as to have a clean surface, it becomes pos-sible to deposit the metallic materials of the electrodes and the first level interconnection on the etched clean surface of the lower insulating layer.
Although the present invention has been fully described by way of example with reference to the accompanying drawings, it is to be noted here that various changes and modifications will be apparent to those skilled in the art. Therefore, un-less otherwise such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.

Claims (10)

Claims:

1. A semiconductor device comprising:
a semiconductor substrate;
a two-layer insulating film formed on a surface of said semiconductor substrate and constituted by a first insulating layer disposed on said surface and a second insulating layer disposed on said first insulating layer;
said first and second insulating layers being respec-tively made of first and second insulating materials that are different in chemical properties from each other;
an electrode; and a first level interconnection;
said two-layer insulating film having a thickness equal to or larger than the thicknesses of said electrode and said first level interconnection;
said two-layer insulating film being formed with an opening in which said electrode and said first level inter-connection are embedded.

2. A semiconductor device as claimed in Claim 1, wherein said first and second insulating layers are respectively made of silicon oxide and silicon nitride.

3. A semiconductor device as claimed in Claim 1, wherein said first and second insulating layers are respectively made of silicon oxide and polyimide resin.

4. A semiconductor device as claimed in Claim 2, wherein said first insulating layer has a thickness of not more than 2000 .ANG..

5. A semiconductor device as claimed in Claim 3, wherein said first insulating layer has a thickness of not more than 2000 .ANG..

6. A method of manufacturing a semiconductor device com-prising the steps of:
forming a two-layer insulating film on a surface of a substrate made of a compound semiconductor;
said two-layer insulating film being constituted by a first insulating layer and a second insulating layer so that said first and second insulating layers are respectively disposed on said surface and on said first insulating layer;
said first and second insulating layers being respec-tively made of first and second insulating materials;
forming a predetermined photoresist pattern on said second insulating layer;
performing reactive ion etching of said second insu-lating layer using said photoresist pattern as a mask for the etching and subsequently performing wet etching, of said first insulating layer using said photoresist pattern and said second insulating layer as a mask for the wet etching so as to form on said two-layer insulating film an opening identi-cal in contour to said photoresist pattern;
depositing in said opening metal for forming both an electrode and a first level interconnection; and performing a lift-off operation.

7. A method as claimed in Claim 6, wherein said first and second insulating layers are respectively made of silicon oxide and silicon nitride.

8. A method as claimed in Claim 6, wherein said first and second insulating layers are respectively made of silicon oxide and polyimide resin.

9. A method as claimed in Claim 7, wherein said first in-sulating layer has a thickness of not more than 2000 .ANG..

10. A method as claimed in Claim 8, wherein said first in-sulating layer has a thickness of not more than 2000 .ANG..