JPS6260241A - Manufacture of multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To improve throughput and to reduce wiring resistance by a method wherein one or more holes are provided at least in an area near to the center of a third wiring layer and an etchant is allowed to penetrate through the holes for the removal by etching of an organic film positioned just under the third wiring layer. CONSTITUTION:On the surface of a GaAs semiconductor substrate 1, a first wiring layer 2 and second wiring layer 3 are formed. An organic film 4 is formed to cover the first wiring layer 2 and the second wiring layer 3 with some portion of the second wiring layer 3 remaining uncovered. The entire surface is covered by a metal coating 5, which is then covered by a photoresist film 6. The photoresist film 6 serves as a mask in a process wherein the metal coating 5 undergoes Au-plating for the formation of an Au film 7. The metal coating 5 is then patterned to assume the same shape as the Au film 7. A third wiring layer 8 is formed and through its center a hole 9 is provided. The organic film 4 is exposed to O2 plasma etching or wet etching using hydrazine or the like for removal for the formation of a cavity 10 under the wiring layer 8. In a structure designed as such, cross talk is reduced among signal during their transmission and interlayer capacity is decreased, which results in improved wiring structure throughput.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer wiring structure in a semiconductor device, and particularly to a method for manufacturing a multilayer wiring structure having an air bridge structure.

[Conventional technology]

2. Description of the Related Art In recent years, as semiconductor devices have become smaller and more highly integrated, wiring formed in semiconductor devices has become more multilayered. Conventionally, this type of multilayer wiring structure is roughly divided into two types of structures that have been put into practical use.

The first structure consists of an insulating layer 21 of a semiconductor device as shown in FIG.
A first wiring layer 22 is formed thereon, and an interlayer insulating film 23 is formed thereon.
This is a structure in which a second wiring layer 24 is formed on top of the second wiring layer 24 for interconnection through contacts. In the wiring structure of this configuration, each of the first and second wiring layers 2
The capacitance between both wiring layers increases due to the dielectric constant of the interlayer insulating film 23 existing between 2.2 and 24, which tends to cause crosstalk of transmission signals, making it difficult to respond to miniaturization of elements.

The second structure is also called an air bridge wiring structure, and as shown in FIG. 3, a first wiring layer 32 is formed on an insulating film layer 31 of a semiconductor device, and a second wiring layer 33 is formed on both sides of the first wiring layer 32. A third wiring layer 3 is formed so as to straddle this first wiring layer 32.
This is the structure in which 4 was formed. In this wiring structure, the first
Since the wiring layer 32 and the third wiring layer 34 are formed of air, which has the lowest dielectric constant, as an insulating layer, the crosstalk of transmission signals between the two wiring layers is extremely small, and the wiring capacitance can also be reduced.

As a method for manufacturing this air bridge wiring structure, for example, after forming the first and second wiring layers 32 and 33, an organic film that can be removed in a later process is applied to the area where the third wiring layer 34 is to be formed. is selectively formed, and then a third wiring layer 34 is formed on this organic film. Thereafter, a method is used in which only the organic film is selectively removed by a dry etching method, a wet etching method, etc., and this portion is hollowed out.

[Problem that the invention seeks to solve]

In the conventional air bridge wiring structure manufacturing method described above,
The width dimension of the third wiring layer 34 formed on the organic film is
If it is large compared to the length dimension, the etchant will be obstructed by the third wiring layer when etching the organic film and will not penetrate sufficiently into the inside of the third wiring layer, leaving an unetched organic film under the third wiring layer. It may be done. Furthermore, even if it is completely removed, the etching time will be longer.

Therefore, the remaining organic film causes the dielectric constant between the wiring layers to be larger than that in the initial case of only air, making it impossible to obtain the original effect of the air bridge wiring structure.

Furthermore, the longer etching time may adversely affect other elements and reduce throughput. Furthermore, in order to allow the etchant to penetrate sufficiently, the width of the third wiring layer 34 is limited, which may be disadvantageous in terms of wiring resistance and design.

[Means for solving problems]

In order to realize an air bridge wiring structure without causing the various problems described above, the method for manufacturing a multilayer wiring structure of the present invention involves forming an organic film to cover a first wiring layer, and forming an organic film on the organic film. Next, a third wiring layer is formed so as to straddle this first wiring layer and connect to the second wiring layer placed on both sides of the first wiring layer, and then the organic film is etched away to form an air bridge. When forming the wiring structure, one or more holes are formed at least at a position near the center of the third wiring layer, and an etchant for the organic film is allowed to enter through the holes to remove the organic material directly under the third wiring layer. The method includes a step of etching away the film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention according to the manufacturing process, (a,) to (gl) are plan configuration diagrams, and (a2) to (
g2) is a cross-sectional configuration diagram taken along line AA.

First, as shown in (a+) and (a2) in the same figure, GaAs
A first wiring layer 2 and a second wiring layer 3 are formed in a predetermined planar pattern on the surface of a semi-insulating semiconductor substrate 1. These wiring layers 2 and 3 are made of, for example, 1000 Ti, P
It has a multilayer structure in which T is laminated to a thickness of 1000 and Au is laminated to a thickness of 2 μm. Further, the semiconductor substrate 1 may be an insulating substrate such as a quartz glass substrate or a semiconductor substrate made of silicon or the like on which an insulating film such as silicon oxide is formed.

Next, as shown in (b+) and (bz) in the figure, at locations where a third wiring layer to be described later is to be formed, the first wiring layer 2 is covered and at least a part of the second wiring layer 3 is formed. The organic material film 4 is applied so as not to cover the surface. This organic film 4 can be formed by depositing an organic film on the entire surface and then selectively etching it using photolithography or the like.

Next, a metal coating 5 is deposited on the entire surface as shown in FIGS. 2C and 2C. This metal coating 5 is used in the next process.
It is used as a power supply path for Au plating.
For example, Ti is laminated to a thickness of 1,000 layers and Au to a thickness of 4,000 layers by sputtering or vacuum evaporation. This metal coating 5
Although other metal compositions may be used, it is important to have a low resistance construction so as not to cause a voltage drop during plating.

Then, as shown in (di) and (d2) in the same figure, the metal coating 5 is covered with a photoresist film 6, and using this as a mask, Au plating is applied to the surface of the metal coating 5 to form an Au plating film 7. . This Au plating film 7 has a thickness of about 3 μm, and is arranged so that it straddles the first wiring layer 2 and has both ends located on the second wiring layer 3, that is, the third wiring layer to be formed from now on. Formed in the same planar pattern as the wiring layer.

Then, as shown in FIGS. 3(el) and (C2), the metal film 5 is patterned into the same shape as the Au plating film 7 using photolithography, thereby forming the third wiring layer 8.

Subsequently, as shown in FIGS. 3(fl) and (f2), a hole 9 is formed in the center of the third wiring layer 8 so as to pass through it. The hole 9 can be formed by selective etching using a photoresist as a mask, and wet etching as well as dry etching such as ion milling and reactive ion etching can be used as the etching method. Further, in this example, when the third wiring layer 8 is formed into a strip shape with a length of 25 μm and a width of 50 μm, the hole 9 has a diameter of 7
It is formed as a μm circular hole. Of course, the hole 8 only needs to be of a size that maintains the shape of the third wiring layer 8, does not impair its conductivity, and allows the etchant of the organic film, which will be described later, to pass through the hole. is not limited to this configuration. For example, it may be polygonal or rectangular. Further, a plurality of holes 8 may be provided, and in some cases, a large number of holes may be arranged in a line to form the third wiring layer 8 in a mesh shape.

Next, as shown in the same figure (g+) and (gz), the front −
The organic material film 4 is removed by 0□ plasma or wet etching using hydrazine or the like. At this time, the etchant not only enters from both sides of the third wiring layer 8 and etches and removes the organic film 4, but also enters through the holes 9 and etches the organic film 4 immediately below the third wiring layer 8. This hole 9 can be used as a starting point for etching to be removed.

As a result, even if the width dimension of the third wiring layer 8 is larger than the length dimension, the organic film 4 under the third wiring layer 8 can be reliably and quickly etched away, and the third wiring layer 8 can be etched away. layer 8
A cavity 10 can be formed below.

Through the above steps, an air bridge wiring structure with no etching residue of the organic film can be easily and quickly formed without being limited by the width dimension of the third wiring layer, and the original effects of the air bridge wiring structure can be obtained. Moreover, the throughput can be improved.

Here, each of the above steps can be modified as follows.

The second wiring layer 3 may not be formed simultaneously with the first wiring layer 2, but may be formed simultaneously as part of the third wiring layer 8 later.

Furthermore, before forming the organic film 4, an insulating film different from the organic film 4, for example Si02, is formed to a thickness of 2000 nm, and the third wiring layer 8, here a metal film, is formed. A contact hole may be formed in this 5iOz film before forming the 5iOz film. however,
Even in this case, if the second wiring layer 3 is formed at the same time as the third wiring layer 8 as described above, contact holes are not required.

Furthermore, in the case where the second wiring layer 3 is formed simultaneously with the third wiring layer 8, in the Au mesolithography process for forming the third wiring layer 8, the first Au plating is also not applied to the portion where the second wiring layer is to be formed.

Further, the holes 9 in the third wiring layer 8 may be etched at the same time as the metal coating 5 is etched, and in this case, Au plating is not applied to the areas where the holes are to be formed in the previous step.

〔Effect of the invention〕

As explained above, the present invention forms one or more holes at least in a position near the center of the third wiring layer, allows the etchant of the organic film to penetrate through the holes, and
Since the organic film directly under the wiring layer is removed by etching, the organic film under the third wiring layer can be reliably etched and removed in a short time without being limited by the width dimension of the third wiring layer. can. As a result, it is possible to obtain the low dielectric constant effect inherent to the air bridge wiring structure, thereby reducing the crosstalk of transmitted signals and the capacitance between wiring layers, and at the same time achieving an improvement in the manufacturing throughput of the wiring structure.

[Brief explanation of drawings]

Figure 1 (a+) ~ (g+), (ax)
~(g2) is a plan view and a cross-sectional view along the line AA for explaining the method of the present invention step by step, FIG. 2 is a cross-sectional view of a wiring structure using an interlayer insulating film, and FIG. 3 is a cross-sectional view of an air bridge wiring structure. FIG. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 2... First wiring layer, 3...
- Second wiring layer, 4... Organic film, 5... Metal coating, 6... Photoresist, 7... Au plating film, 8
... third wiring layer, 9 ... hole, 10 ... cavity,
21.31... Insulating layer, 22.32... First wiring layer, 23... Interlayer insulating film, 24.33... Second wiring layer, 34... Third wiring layer . Figure 1 (dl) Figure 1 (fl) (d2) (e2) (f2) Procedural amendment (formality)

Claims (1)

[Claims] 1. A step of forming a first wiring layer on an insulating layer of a semiconductor device, a step of forming an organic material film so as to cover this first wiring layer, and a step of forming a first wiring layer on an insulating layer of a semiconductor device; a step of forming a third wiring layer so as to straddle the first wiring layer and connect to a second wiring layer disposed on both sides of the first wiring layer, and then etching away the organic film to form an air bridge. forming a wiring structure, at least before the step of etching away the organic film, one or more holes are formed at least at a position closer to the center of the third wiring layer; 1. A method for manufacturing a multilayer wiring structure, comprising the steps of: forming an organic film, and infiltrating an etchant for the organic film through the hole to etch away the organic film directly below the third wiring layer. 2. The process of forming the third wiring layer includes a process of forming a metal film on the entire surface, a process of selectively applying Au plating on the metal film using this metal film as a power supply path, and a process of forming a metal film on the metal film not plated with Au. 2. The method of manufacturing a multilayer wiring structure according to claim 1, further comprising the step of etching away a portion. 3. The method for manufacturing a multilayer wiring structure according to claim 1 or 2, wherein the second wiring layer is formed simultaneously with the first wiring layer.