JPS5893351A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce electrostatic capacitance formed to a parallel wiring layer by previously shaping unevenness according to a predetermined pattern with steep difference at a stage to the surface of an insulating film and forming the wiring layer isolated by the stage difference section of the unevenness. CONSTITUTION:The three mutually parallel and adjacent wiring layers 131-133 are formed onto an Si substrate 11 to which an element region is shaped. The uneven pattern, the surface thereof has steep difference at the stage, is molded while being made correspond to a wiring pattern in the film 12. According to such wiring structure, the degree of integration can largely be increased through the improvement of wiring density because electrostatic capacitance formed to the wiring layers can be reduced and a separated distance is made approximately zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a wiring structure and a method for forming the same in a semiconductor device, which has become extremely highly integrated and miniaturized.

[Technical Background of the Invention and Problems Therewith] Recently, lithography technology, processing, and processing technology in semiconductor device manufacturing have progressed, and semiconductor devices are becoming more highly integrated and miniaturized. As semiconductor devices become increasingly finer, wiring patterns also become finer, and the spacing between adjacent wires also becomes finer.

As a result, a problem arises in that stray capacitance between adjacent wirings increases, which increases signal propagation delay.

FIG. 1 shows an example in which three parallel wiring layers 31 to 3s are formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. now,
Assuming that the width W and the spacing S of the wiring layers 31 to 3s are equal, and focusing on the three wiring layers in the middle, the unit length associated therewith is
The capacitance 1c is the capacitance of the insulating film 2, C, and the gear between the wiring layers.

It is expressed as C=C1+2 Cm, where C is the capacitance due to the plug. The solid line in FIG. 2 shows the change in capacitance C when the value of W=S is changed. The one-dot chain line represents the case where only the capacitance 01 due to the insulating film 2 is present. As is clear from the figure, the capacity -1c is such that W=S is the film original TOX of the insulating film 2.
It shows a minimum value at point A, which is almost equal to , and increases as the dimensions become finer than this. This is because the rate of increase in the capacitance Cm becomes larger than the rate of decrease in the capacity CI.

When a single wiring is miniaturized in this way, a delay in signal propagation due to an increase in capacitance becomes a serious problem. Further, the miniaturization of wiring by conventional methods results in a decrease in current capacity, an increase in wiring resistance, and disconnection due to electromigration, leading to a decrease in the reliability of semiconductor devices.

[Purpose of the invention]

The present invention significantly reduces the capacitance associated with wiring layers, thereby suppressing delay in signal propagation due to miniaturization of wiring.
``Also, using conventional phosphorography technology, it is possible to easily achieve high integration without further miniaturization (such as wiring).
The present invention provides a semiconductor device with improved reliability and a method for manufacturing the same.

[Summary of the invention]

The present invention provides a semiconductor device in which a wiring layer is formed on a semiconductor substrate through an insulating film in the same conductive film forming process and has portions adjacent to each other in parallel, in which a steep step is formed on the surface of the insulating film. providing unevenness with a predetermined number of turns, and arranging one of the mutually parallel adjacent portions of the wiring layer on the recess and the other on the protrusion so that the distance in the horizontal direction is approximately zero; In other words, it is characterized by providing parallel wiring layers separated by uneven step portions.

The present invention also provides that when forming the wiring structure as described above, first, an unevenness corresponding to the arm turn of the wiring is formed on the surface of the insulating film on the semiconductor substrate on which the element region is formed, and then the entire surface is formed on the surface of the insulating film. A conductive film is deposited, and then a masking material with a high etching rate is deposited on the entire surface of the conductive film at the stepped portions, the entire surface is etched, and this masking material is selectively removed at the uneven steps, and the remaining masking material is removed. The method is characterized in that the conductive film is selectively etched using a method of etching to form parallel adjacent wiring layers separated by uneven step portions.

〔Effect of the invention〕

According to the present invention, unevenness/? One of the parallel and adjacent portions of the wiring layer made of the same conductive film is arranged in the concave portion and the other in the convex portion in a self-aligned state with the turns. Therefore, adjacent wiring layers do not directly oppose each other, or even if they do, the opposing area can be made extremely small, which reduces the capacitance between wirings and improves signal propagation in the wirings. delay becomes smaller. In addition, the horizontal separation distance between adjacent wiring layers is almost zero, so that the wiring density can be increased without making the wiring width so fine, thereby achieving even higher integration of the device. Further, since the wiring width does not have to be made so small, it is possible to easily achieve high integration of the semiconductor device using conventional lithography technology.

For the same reason, the reliability of the semiconductor device can be improved by preventing a decrease in the current capacity of the wiring, disconnection due to electromigration, and an increase in resistance.

[Embodiments of the invention]

FIG. 3 shows a cross section of a main part of an embodiment of the present invention. 1
1 is an 81 substrate on which an element region is formed;
This is a turtle in which three wiring layers 131 to 131 are formed parallel to each other and adjacent to each other with a 102 film 12 in between. S10. Membrane 1
2 is for example Id, with a thickness of 1.5 μm and about 1
A concavo-convex pattern with steep steps of μm is formed corresponding to the wiring pattern, and three wiring layers 13 to 13 layers are formed.
The middle wiring layer 13 is disposed in the concave portion, and the wiring layers 131 on both sides are disposed in the convex portion by using the same conductive film which is thinner than the uneven steps. The horizontal separation distance between the wiring layers 751 to 131 is approximately #1 and zero.

With such a wiring structure, the capacitance associated with the wiring layer is extremely small, as is clear from a comparison with Figure 1.
Also, since the separation distance is almost zero, the wiring density is improved)
It can be seen that a significant increase in integration is achieved.

This is an example. That is, three first-layer wiring layers 23 are formed on a separate substrate 21 via a 5tO2 film 22 and separated by the unevenness of its surface.
231 is formed, and three second-layer wiring layers 251 to 253 separated by unevenness are formed on the surface thereof via sto and MIXz 4. As a result, a high-density multilayer wiring structure can be realized.

Next, one embodiment of the method of the present invention will be described using FIGS. First, a Si substrate 3 on which an element region is formed
A film 32 having a thickness of about 2 μm is formed on the 8SO3 film 320, and a recess with a step difference of about 1 μm is formed on the surface of the 8SO3 film 320 by reactive ion etching using a photoresist as a mask. In this case, the concave portion corresponds to the middle wiring of the three parallel wiring layers formed on the 5102 film 32. So, 1.: After 1°, cylinder is applied to the entire surface by CVD method! A polycrystalline silicon film 33 is deposited by about 500X, and then a mask material is used on top of it by plasma CVD! 810. Membrane 34 50'
001 is deposited (a). After this, the entire surface was etched using NH4F, and etching was performed using 810. The stepped portion of the film 340 is selectively etched and removed (b).

For the 810□ film 34f14F produced by the plasma CVD method, the etching rate at the stepped portion is approximately 2 times that of the flat portion.
Since it is 0 times larger, only the stepped portion can be removed by etching the entire surface.

Then, using the remaining 81O1 film 34 as a mask, the polycrystalline silicon film at the stepped portion is etched away using a carbide dry etching method to form three wiring layers 331 to 338 separated by the stepped portion (c). Wiring layer 1 on the convex part
31 and JJs are further processed by a normal pip process to form a resist J5 (d), using this resist J5 as a mask.

The wiring width is set to the specified width (,).

According to this embodiment, by using the conventional phosphorography technique as is, it is possible to reduce the capacitance between wiring layers and realize high-density wiring without performing any difficult microfabrication. Particularly when applied to a large-scale integrated circuit with a large wiring area such as a CPU, the effects of reduced chip area, higher integration, and higher reliability can be obtained.

In this embodiment, polycrystalline silicon is used as the conductor film, but metals such as AI, Muj-8i, W, and various metal silicides can also be used.

In addition, as a mask material, 810 made by plasma CVD method,
Although a film was used, it can be used as a similar mask material as long as the etching rate at the stepped portion is higher than that at the flat portion. Specifically, 81 by the snow ivy method
0. Membranes are preferred.

6. FIGS. 4(a) to 4(,) are diagrams for explaining another embodiment of the present invention. 1. First, a 5SO2 film 42 is deposited to a thickness of about 2 μm on an St substrate 41 on which an element region is formed. formed into
9810. by reactive ion etching using photoresist as a mask. A recess with a step difference of about 1 μm is formed on the surface of the film 420. As in the previous embodiment, the recess with is
, corresponds to the middle wiring pattern among the three parallel marking line layers formed on the film 42. After that, an AI-81 film thinner than 1/2 of the step of one concave portion is coated on the entire surface by the Softuta method, and a step break is made at the step portion to form a layer separated from each other. -81 wiring layers 411 to 43. form (,). Next, the precyst 44 is formed by a normal PEP process.
AJ is formed using this resist 44 as a mask.
-81 wiring 43 Remove unnecessary portions of 4J1 by etching to obtain a predetermined wiring width (,).

It is clear that this embodiment also provides the same effects as the previous embodiment. Furthermore, according to Jin's embodiment, wiring that is automatically separated at a stepped portion can be formed with a simpler process than in the previous embodiment.

FIG. 7 shows a wiring structure obtained by modifying the above embodiment. That is, 81 substrate J I K glo.

A film 52 is formed, and a predetermined uneven pattern is formed on its surface. As in the above embodiment, 1/2 of the level difference between the convex and concave surfaces is
By depositing a thinner An-11 film, the AJ-B1 is separated by uneven steps and is circular and parallel to each other.
Wiring layers 531 to 531 are formed. In this case, in the step of etching away unnecessary portions of the wiring layer ss1 531 in the flat portion, the wiring 53-, which requires a large wiring width, such as a power supply line, is formed at the same time.

In this way, according to this embodiment, the signal wiring sections that are closely adjacent to each other in parallel with each other, and the power supply wiring sections and pipes in flat areas that require large current capacities can coexist skillfully while satisfying the performance requirements of each. be able to.

In the embodiment shown in FIG. 6, it is important to control the depth of the recess formed in the 8102 film 11 and the thickness of the mul-Sl films 31 to 33. Variations in the etching process and etching of uneven etching inevitably occur, which makes it difficult to control the etching end point.
Further, it brings about inconveniences such as variations in capacitance between wiring layers. To prevent this, for example, the 8102 film J2 must be made thicker than necessary.

FIGS. 8(a) to 8(,) are rounded diagrams for explaining nine embodiments with improved features. First, a first insulating film is formed on an 810.81 substrate 61 by CVD. l [# J is 1 μm
Further, a 1 μm thick I-ion resin film 63 is formed as a second insulating film on this by baking with J) Ik cloth L400C using a spin code. Then using photo-etching? The reimide resin film 63 is selectively etched to form a recess (b). At this time, CF4
When using chemical dry etching using a mixed gas of
Even when denguing is performed, Bib and @σ2 are hardly etched, and the 810. Membrane-2 can be exposed. That is, it is possible to obtain a state in which the level difference in the recessed portion is constant. After this, similarly to the embodiment shown in Fig. 6, the Muno 8 film is applied using a sputtering method so as to create a step cut at the step of the concave portion, and the unnecessary portions are removed using a photoetching method to make parallel contact. 84 layers to M4s of M-J-81 wiring layer are formed (, ).

According to this embodiment, there is no variation in the level difference due to overburden or tinder, and therefore the capacitance between wiring layers can be made uniform and small, making it possible to further improve the performance of the semiconductor device. In addition, since the -Liden resin film has a specific electric charge rate of about 3.0, S10. This is also preferable in terms of reducing the capacitance associated with the wiring layer compared to the case of using only a film.

In the above example, 4limide/8tO was used as the insulating film combination, but 81. N4/5iio.

Yamuj20. / 810. It is also possible to use other combinations, such as. Further, as a method for separating wiring layers at a step portion, the method of the embodiment shown in FIG. 5 may be applied instead of the method using step breaks.

FIGS. 9(a) to 9(d) are diagrams for explaining an embodiment including the process of forming a contact portion between a wiring layer and a substrate! be. First, the 81 substrate rlK approximately 2 fi on which the element region was formed
An 8102 film 12 of m is formed using the CVD method, and contact holes 131 to y3 are selectively formed using a photolithography method (1). Next, in the same manner as in the previous example,
A recess corresponding to the middle wiring pattern of the three parallel wiring layers formed on the StO film 12 is formed so as to overlap the contact hole VX (b).

Thereafter, contact holes 7J, 7J and KAj films 141 to 14m are deposited using, for example, a lift-off technique (c). Then, in the same state as in the previous embodiment, or by the method in the embodiment shown in FIG. 5, wiring layers 751 to 151 are formed which are adjacent to each other in parallel and separated by uneven step portions ( d).

FIG. 10 is a plan view of the obtained wiring pattern 1, and the cross section of Moom' in FIG. 10 corresponds to FIG. 9(d) K.

According to this embodiment, even if the contact hole in the wiring layer on the convex portion 41 is deep, the connection member is embedded in the contact hole in advance, so that the wiring is not disconnected at the contact hole portion. is prevented.

In this example, the connection member was embedded in the contact hole after forming the unevenness corresponding to the wiring pattern.
A connection member may be buried in the contact hole in the form shown in FIG. 9(&), and then selective etching may be performed to form a concavo-convex pattern to obtain the state shown in FIG. 9(,).

Further, as is clear from FIG. 10, when there is almost no horizontal separation between adjacent wiring layers and the wiring width is small, the contact hole becomes even smaller in size. This is unfavorable for making good contact.

In order to improve this point, contact holes RA' to 111' may be formed at positions slightly shifted from those in FIG. 10, as shown in FIG. 11. By doing this, the dimensions of the contact holes IJν to 73a' can be adjusted to the wiring layer 7j.
The width can be made approximately equal to the width of i to 151, and reliable contact can be made.

In each of the above embodiments, the case where three parallel wiring layers are mainly formed has been described.

Therefore, after separating the wiring layers at the uneven step portions, the wiring layers at the flat portions are subjected to a 1111:1 process by an ordinary PEP engineer. However, for example, when a large number of wiring patterns are arranged parallel to each other over the entire surface of the board, adjacent wiring layers are simply separated by a repeated uneven pattern on the surface of the insulating film corresponding to the wiring patterns. The PEP process becomes unnecessary. Further, in the case where the conductor film remaining on the flat part is left as it is, for example, as a shield film after the wiring pattern is separated by uneven step parts, the subsequent PEPI process can be similarly omitted. Furthermore, in each of the above embodiments, the middle layer of the three parallel adjacent wiring layers is placed in the concave part and separated from the wiring on both sides, but the uneven pattern is formed so that the middle layer is placed in the convex part. Of course, you can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the wiring structure of a conventional semiconductor device, FIG. 2 is a diagram showing the relationship between the wiring width and capacitance, and FIG. 3 is a diagram showing the wiring structure of an embodiment of the present invention. , Fig. 4 is a diagram showing an example in which two similar wiring layers are stacked, and Fig. 5 (,) to (・
) is a diagram for explaining the manufacturing process of one embodiment of the method of the present invention, FIGS. 6(,) to (,) are diagrams for explaining other manufacturing processes, and FIG. Figures 8(a) to 8(a) are diagrams showing the wiring structure of the present invention, and Figure 10 is a diagram for explaining the manufacturing process of an embodiment of the method of the present invention, which is an improved implementation of the method of the present invention. Plan view of 9 turns of wiring, 11th
The figure is a plan view of wiring/f-turn according to an embodiment that improves the process of FIG. 9. 11.22, jJ, 4J, 51, il, rl
...81 board, 11.22, 14.31.42°12
, il, 6J, '12...810□ membrane, 131-II
s e23* ~231 1151 ~25B
. 331~J 31 e 431~43m, 531~5
16 e g 4maro~64m m151~rtsl
...Wiring layer, 34...Plasma CVD-810, film (i-sulfur material) Applicant's representative Patent attorney Takehiko Suzue $111 A-W (=S) M3 Figure 4 jI5 Figure 4 No. 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure s9 Figure 10 Figure 11

Claims (5)

[Claims] (1) In a semiconductor device in which a wiring layer having parallel adjacent portions formed in the same conductive film forming step via an insulating film is provided on a semiconductor substrate on which an element region is formed, the insulating M#i A predetermined surface with steep steps on its surface.
The wiring layer has a 9-turf unevenness, and the wiring layer is arranged so that parallel adjacent portions are separated by step portions of the unevenness so that the distance apart in the horizontal direction is approximately zero. Semiconductor equipment. (2) Make the level difference between the concave and convex portions larger than the thickness of the wiring layer, and make sure that the adjacent parallel parts of the wiring layer do not face each other.
A semiconductor device according to claim 1. (3) a step of forming an insulating film on the semiconductor substrate on which the element region is formed, and forming unevenness corresponding to the patterned pattern on the surface of the insulating film; and a step of depositing a conductor film on the entire surface of the insulating film. , a step of depositing a masking material having a high etching rate at the stepped portions on the entire surface of the conductor film, etching the entire surface, and selectively removing the thick masking material at the uneven stepped portions; and using the remaining masking material. A method of manufacturing a semiconductor device, comprising the step of selectively etching the conductor film to form parallel adjacent wiring layers separated by the uneven step portions. (4) The q surface material is a silicon oxide film made by the CVD method or the snow vine method. The method of manufacturing a semiconductor device according to claim M3, wherein the method is a method of manufacturing a semiconductor device. (5) The method of forming unevenness/4 turns on the surface of the insulating film is as follows:
4. The method of manufacturing a semiconductor device according to claim 3, wherein selective etching is performed by a reactive ion etching method.